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370 lines
14 KiB
C++
370 lines
14 KiB
C++
//
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// 68000Storage.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 08/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "../68000.hpp"
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#include <algorithm>
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namespace CPU {
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namespace MC68000 {
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struct ProcessorStorageConstructor {
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ProcessorStorageConstructor(ProcessorStorage &storage) : storage_(storage) {}
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using BusStep = ProcessorStorage::BusStep;
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/*!
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Installs BusSteps that implement the described program into the relevant
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instance storage, returning the offset within @c all_bus_steps_ at which
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the generated steps begin.
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@param access_pattern A string describing the bus activity that occurs
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during this program. This should follow the same general pattern as
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those in yacht.txt; full description below.
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@discussion
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The access pattern is defined, as in yacht.txt, to be a string consisting
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of the following discrete bus actions. Spaces are ignored.
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* n: no operation; data bus is not used;
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* -: idle state; data bus is not used but is also not available;
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* p: program fetch; reads from the PC and adds two to it;
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* W: write MSW of something onto the bus;
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* w: write LSW of something onto the bus;
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* R: read MSW of something from the bus;
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* r: read LSW of soemthing from the bus;
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* S: push the MSW of something onto the stack;
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* s: push the LSW of something onto the stack;
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* U: pop the MSW of something from the stack;
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* u: pop the LSW of something from the stack;
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* V: fetch a vector's MSW;
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* v: fetch a vector's LSW;
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* i: acquire interrupt vector in an IACK cycle;
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* F: fetch the SSPs MSW;
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* f: fetch the SSP's LSW.
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Quite a lot of that is duplicative, implying both something about internal
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state and something about what's observable on the bus, but it's helpful to
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stick to that document's coding exactly for easier debugging.
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p fetches will fill the prefetch queue, attaching an action to both the
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step that precedes them and to themselves. The SSP fetches will go straight
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to the SSP.
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Other actions will by default act via effective_address_ and bus_data_.
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The user should fill in the steps necessary to get data into or extract
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data from those.
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*/
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size_t assemble_program(const char *access_pattern, const std::vector<uint32_t *> &addresses = {}, bool read_full_words = true) {
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auto address_iterator = addresses.begin();
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RegisterPair32 *scratch_data_read = storage_.bus_data_;
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RegisterPair32 *scratch_data_write = storage_.bus_data_;
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using Action = BusStep::Action;
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std::vector<BusStep> steps;
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// Parse the access pattern to build microcycles.
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while(*access_pattern) {
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ProcessorBase::BusStep step;
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switch(*access_pattern) {
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case '\t': case ' ': // White space acts as a no-op; it's for clarity only.
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++access_pattern;
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break;
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case 'n': // This might be a plain NOP cycle, in which some internal calculation occurs,
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// or it might pair off with something afterwards.
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switch(access_pattern[1]) {
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default: // This is probably a pure NOP; if what comes after this 'n' isn't actually
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// valid, it should be caught in the outer switch the next time around the loop.
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steps.push_back(step);
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++access_pattern;
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break;
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case '-': // This is two NOPs in a row.
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steps.push_back(step);
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steps.push_back(step);
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access_pattern += 2;
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break;
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case 'F': // Fetch SSP MSW.
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case 'f': // Fetch SSP LSW.
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_;
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step.microcycle.value = isupper(access_pattern[1]) ? &storage_.stack_pointers_[1].halves.high : &storage_.stack_pointers_[1].halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementEffectiveAddress;
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steps.push_back(step);
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access_pattern += 2;
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break;
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case 'V': // Fetch exception vector low.
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case 'v': // Fetch exception vector high.
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_;
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step.microcycle.value = isupper(access_pattern[1]) ? &storage_.program_counter_.halves.high : &storage_.program_counter_.halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementEffectiveAddress;
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steps.push_back(step);
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access_pattern += 2;
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break;
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case 'p': // Fetch from the program counter into the prefetch queue.
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
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step.microcycle.address = &storage_.program_counter_.full;
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step.microcycle.value = &storage_.prefetch_queue_[1];
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step.action = Action::AdvancePrefetch;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementProgramCounter;
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steps.push_back(step);
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access_pattern += 2;
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break;
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case 'r': // Fetch LSW (or only) word (/byte)
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case 'R': // Fetch MSW word
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case 'w': // Store LSW (or only) word (/byte)
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case 'W': { // Store MSW word
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const bool is_read = tolower(access_pattern[1]) == 'r';
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RegisterPair32 **scratch_data = is_read ? &scratch_data_read : &scratch_data_write;
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
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step.microcycle.address = *address_iterator;
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step.microcycle.value = isupper(access_pattern[1]) ? &(*scratch_data)->halves.high : &(*scratch_data)->halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte) | (is_read ? Microcycle::Read : 0);
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steps.push_back(step);
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++address_iterator;
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if(!isupper(access_pattern[1])) ++(*scratch_data);
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access_pattern += 2;
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} break;
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}
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break;
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default:
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std::cerr << "MC68000 program builder; Unknown access type " << *access_pattern << std::endl;
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assert(false);
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}
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}
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// Add a final 'ScheduleNextProgram' sentinel.
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BusStep end_program;
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end_program.action = Action::ScheduleNextProgram;
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steps.push_back(end_program);
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// If the new steps already exist, just return the existing index to them;
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// otherwise insert them.
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const auto position = std::search(storage_.all_bus_steps_.begin(), storage_.all_bus_steps_.end(), steps.begin(), steps.end());
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if(position != storage_.all_bus_steps_.end()) {
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return size_t(position - storage_.all_bus_steps_.begin());
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}
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const auto start = storage_.all_bus_steps_.size();
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std::copy(steps.begin(), steps.end(), std::back_inserter(storage_.all_bus_steps_));
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return start;
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}
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/*!
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Disassembles the instruction @c instruction and inserts it into the
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appropriate lookup tables.
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install_instruction acts, in effect, in the manner of a disassembler. So this class is
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formulated to run through all potential 65536 instuction encodings and attempt to
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disassemble each, rather than going in the opposite direction.
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This has two benefits:
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(i) which addressing modes go with which instructions falls out automatically;
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(ii) it is a lot easier during the manual verification stage of development to work
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from known instructions to their disassembly rather than vice versa; especially
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(iii) given that there are plentiful disassemblers against which to test work in progress.
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*/
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void install_instructions() {
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enum class Decoder {
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Decimal,
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RegOpModeReg,
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SizeModeRegisterImmediate,
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DataSizeModeQuick,
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RegisterModeModeRegister
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};
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using Operation = ProcessorStorage::Operation;
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using Action = ProcessorStorage::MicroOp::Action;
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struct PatternMapping {
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uint16_t mask, value;
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Operation operation;
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Decoder decoder;
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};
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/*
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Inspired partly by 'wrm' (https://github.com/wrm-za I assume); the following
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table draws from the M68000 Programmer's Reference Manual, currently available at
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https://www.nxp.com/files-static/archives/doc/ref_manual/M68000PRM.pdf
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After each line is the internal page number on which documentation of that
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instruction mapping can be found, followed by the page number within the PDF
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linked above.
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NB: a vector is used to allow easy iteration.
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*/
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const std::vector<PatternMapping> mappings = {
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{0xf1f0, 0x8100, Operation::SBCD, Decoder::Decimal}, // 4-171 (p275)
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{0xf1f0, 0xc100, Operation::ABCD, Decoder::Decimal}, // 4-3 (p107)
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{0xf000, 0x8000, Operation::OR, Decoder::RegOpModeReg}, // 4-150 (p226)
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{0xf000, 0x9000, Operation::SUB, Decoder::RegOpModeReg}, // 4-174 (p278)
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{0xf000, 0xb000, Operation::EOR, Decoder::RegOpModeReg}, // 4-100 (p204)
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{0xf000, 0xc000, Operation::AND, Decoder::RegOpModeReg}, // 4-15 (p119)
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{0xf000, 0xd000, Operation::ADD, Decoder::RegOpModeReg}, // 4-4 (p108)
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{0xff00, 0x0600, Operation::ADD, Decoder::SizeModeRegisterImmediate}, // 4-9 (p113)
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{0xff00, 0x0600, Operation::ADD, Decoder::DataSizeModeQuick}, // 4-11 (p115)
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{0xf000, 0x1000, Operation::MOVEb, Decoder::RegisterModeModeRegister}, // 4-116 (p220)
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{0xf000, 0x2000, Operation::MOVEl, Decoder::RegisterModeModeRegister}, // 4-116 (p220)
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{0xf000, 0x3000, Operation::MOVEw, Decoder::RegisterModeModeRegister}, // 4-116 (p220)
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};
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std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
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// The arbitrary_base is used so that the offsets returned by assemble_program into
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// storage_.all_bus_steps_ can be retained and mapped into the final version of
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// storage_.all_bus_steps_ at the end.
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BusStep arbitrary_base;
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// Perform a linear search of the mappings above for this instruction.
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for(size_t instruction = 0; instruction < 65536; ++instruction) {
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for(const auto &mapping: mappings) {
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if((instruction & mapping.mask) == mapping.value) {
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const auto micro_op_start = storage_.all_micro_ops_.size();
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switch(mapping.decoder) {
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// Decodes the format used by ABCD and SBCD.
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case Decoder::Decimal: {
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const int destination = (instruction >> 9) & 7;
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const int source = instruction & 7;
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if(instruction & 8) {
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storage_.instructions[instruction].source = &storage_.bus_data_[0];
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storage_.instructions[instruction].destination = &storage_.bus_data_[1];
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storage_.all_micro_ops_.emplace_back(
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Action::PredecrementSourceAndDestination1,
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&arbitrary_base + assemble_program("n nr nr np nw", { &storage_.address_[source].full, &storage_.address_[destination].full, &storage_.address_[destination].full }, false));
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storage_.all_micro_ops_.emplace_back(Action::PerformOperation);
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} else {
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storage_.instructions[instruction].source = &storage_.data_[source];
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storage_.instructions[instruction].destination = &storage_.data_[destination];
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storage_.all_micro_ops_.emplace_back(
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Action::PerformOperation,
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&arbitrary_base + assemble_program("np n"));
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storage_.all_micro_ops_.emplace_back();
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}
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} break;
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// Decodes the format used by all the MOVEs.
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case Decoder::RegisterModeModeRegister: {
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const int source_register = instruction & 7;
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const int source_mode = (instruction >> 3) & 7;
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const int destination_mode = (instruction >> 6) & 7;
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const int destination_register = (instruction >> 9) & 7;
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if(!source_mode) {
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storage_.instructions[instruction].source = &storage_.data_[source_register];
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}
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if(!destination_mode) {
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storage_.instructions[instruction].destination = &storage_.data_[destination_register];
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}
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// TODO: all other types of mode.
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if(!destination_mode && !source_mode) {
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storage_.all_micro_ops_.emplace_back(Action::PerformOperation, &arbitrary_base + assemble_program("np"));
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storage_.all_micro_ops_.emplace_back();
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} else {
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continue;
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}
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} break;
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default:
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std::cerr << "Unhandled decoder " << int(mapping.decoder) << std::endl;
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continue;
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}
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// Install the operation and make a note of where micro-ops begin.
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storage_.instructions[instruction].operation = mapping.operation;
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micro_op_pointers[instruction] = micro_op_start;
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// Don't search further through the list of possibilities.
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break;
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}
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}
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}
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// Finalise micro-op and program pointers.
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for(size_t instruction = 0; instruction < 65536; ++instruction) {
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if(micro_op_pointers[instruction] != std::numeric_limits<size_t>::max()) {
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storage_.instructions[instruction].micro_operations = &storage_.all_micro_ops_[micro_op_pointers[instruction]];
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auto operation = storage_.instructions[instruction].micro_operations;
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while(!operation->is_terminal()) {
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const auto offset = size_t(operation->bus_program - &arbitrary_base);
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assert(offset >= 0 && offset < storage_.all_bus_steps_.size());
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operation->bus_program = &storage_.all_bus_steps_[offset];
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++operation;
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}
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}
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}
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}
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private:
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ProcessorStorage &storage_;
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};
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}
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}
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CPU::MC68000::ProcessorStorage::ProcessorStorage() {
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ProcessorStorageConstructor constructor(*this);
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// Create the exception programs.
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const size_t reset_offset = constructor.assemble_program("n- n- n- n- n- nn nF nf nV nv np np");
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// Install operations.
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constructor.install_instructions();
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// Realise the exception programs as direct pointers.
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reset_program_ = &all_bus_steps_[reset_offset];
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// Set initial state. Largely TODO.
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active_step_ = reset_program_;
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effective_address_ = 0;
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is_supervisor_ = 1;
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}
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