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107 lines
2.9 KiB
C++
107 lines
2.9 KiB
C++
//
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// Sequencer.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 29/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_68k_Sequencer_hpp
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#define InstructionSets_68k_Sequencer_hpp
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#include "Instruction.hpp"
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#include "Model.hpp"
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#include <cassert>
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namespace InstructionSet {
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namespace M68k {
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static constexpr uint8_t FetchOp1 = (1 << 0);
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static constexpr uint8_t FetchOp2 = (1 << 1);
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static constexpr uint8_t StoreOp1 = (1 << 2);
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static constexpr uint8_t StoreOp2 = (1 << 3);
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/*!
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Provides a bitfield with a value in the range 0–15 indicating which of the provided operation's
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operands are accessed via standard fetch and store cycles.
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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*/
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template <Model model, Operation t_operation = Operation::Undefined> uint8_t operand_flags(Operation r_operation = Operation::Undefined) {
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switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
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default:
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assert(false);
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//
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// No operands are fetched or stored.
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//
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case Operation::LEA:
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case Operation::PEA:
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return 0;
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//
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// Single-operand read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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return FetchOp1;
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//
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// Single-operand write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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return StoreOp1;
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//
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// Single-operand read-modify-write.
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//
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case Operation::NBCD:
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case Operation::EXTbtow: case Operation::EXTwtol:
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return FetchOp1 | StoreOp1;
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//
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// Two-operand; read both.
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//
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case Operation::CMPb: case Operation::CMPw: case Operation::CMPl:
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case Operation::CMPAw: case Operation::CMPAl:
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return FetchOp1 | FetchOp2;
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//
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// Two-operand; read source, write dest.
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//
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case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
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case Operation::MOVEAw: case Operation::MOVEAl:
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return FetchOp1 | StoreOp2;
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//
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// Two-operand; read both, write dest.
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//
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case Operation::ABCD: case Operation::SBCD:
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case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
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case Operation::ADDAw: case Operation::ADDAl:
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case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
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case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
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case Operation::SUBAw: case Operation::SUBAl:
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case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl:
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return FetchOp1 | FetchOp2 | StoreOp2;
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//
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// Two-operand; read both, write both.
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//
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case Operation::EXG:
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return FetchOp1 | FetchOp2 | StoreOp1 | StoreOp2;
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}
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}
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}
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}
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#endif /* InstructionSets_68k_Sequencer_h */
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