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CLK
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Thomas Harte
e9972aa0dd
Added respect for the index-hole limit on reading, and an error phase.
2017-08-06 19:25:44 -04:00
..
1770
Fixed WAIT_FOR_TIME macro.
2017-08-06 12:08:54 -04:00
6522
Standardises on
const [Half]Cycles
as the thing called and returned, rather than
const [Half]Cycles &
as it's explicitly defined to be only one
int
in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
6532
Standardises on
const [Half]Cycles
as the thing called and returned, rather than
const [Half]Cycles &
as it's explicitly defined to be only one
int
in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
6560
Standardises on
const [Half]Cycles
as the thing called and returned, rather than
const [Half]Cycles &
as it's explicitly defined to be only one
int
in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
6845
Permitted register 3 to dictate vertical sync length.
2017-08-04 08:56:36 -04:00
8255
Fixed: of course this should take a reference to an existing port handler rather than hatching its own; otherwise additional communication with a port handler by an i8255 owner doesn't work as intended.
2017-08-01 17:01:20 -04:00
8272
Added respect for the index-hole limit on reading, and an error phase.
2017-08-06 19:25:44 -04:00
AY38910
Attempted to move to more accurate bus reading — if control lines are set then all subsequent data inputs should act according to the current control lines; changes to port input should be reflected live upon readings, etc.
2017-08-02 19:45:58 -04:00