Thomas Harte 62eef8cb40 Reinstates proper ready behaviour.

2018-06-18 21:35:39 -04:00

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Controller

Commutes Sleeper to ClockingHint::Source, making state more granular.

2018-05-27 23:17:06 -04:00

DiskImage

Moves gap 1 into proper ownership.

2018-06-09 17:28:08 -04:00

DPLL

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Encodings

Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32.

2018-05-23 22:21:57 -04:00

Parsers

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Track

Adds necessary header for assert.

2018-06-10 21:02:19 -04:00

Disk.hpp

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Drive.cpp

Reinstates proper ready behaviour.

2018-06-18 21:35:39 -04:00

Drive.hpp

Creates the through-path that will be necessary for RWTS acceleration.

2018-06-09 12:51:53 -04:00