Thomas Harte cc8f316941 Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).		2017-06-19 20:51:28 -04:00
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Z80.cpp	First tentative steps towards adding a Z80 implementation.	2017-05-14 17:46:41 -04:00
Z80.hpp	Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).	2017-06-19 20:51:28 -04:00
Z80AllRAM.cpp	Explained refresh cycles to the all-RAM Z80.	2017-06-19 07:36:11 -04:00
Z80AllRAM.hpp	Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.	2017-06-18 22:03:13 -04:00