mirror of
https://github.com/TomHarte/CLK.git
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353 lines
12 KiB
C++
353 lines
12 KiB
C++
//
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// Disassembler6502.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/11/2016.
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// Copyright 2016 Thomas Harte. All rights reserved.
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//
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#include "6502.hpp"
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#include "Kernel.hpp"
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using namespace Analyser::Static::MOS6502;
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namespace {
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using PartialDisassembly = Analyser::Static::Disassembly::PartialDisassembly<Disassembly, uint16_t>;
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struct MOS6502Disassembler {
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static void AddToDisassembly(
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PartialDisassembly &disassembly,
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const std::vector<uint8_t> &memory,
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const std::function<std::size_t(uint16_t)> &address_mapper,
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uint16_t entry_point
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) {
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disassembly.disassembly.internal_calls.insert(entry_point);
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uint16_t address = entry_point;
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while(true) {
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std::size_t local_address = address_mapper(address);
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if(local_address >= memory.size()) return;
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Instruction instruction;
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instruction.address = address;
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++address;
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// Get operation.
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const uint8_t operation = memory[local_address];
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// Decode addressing mode.
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switch(operation&0x1f) {
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case 0x00:
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if(operation >= 0x80) instruction.addressing_mode = Instruction::Immediate;
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else if(operation == 0x20) instruction.addressing_mode = Instruction::Absolute;
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else instruction.addressing_mode = Instruction::Implied;
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break;
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case 0x08: case 0x18: case 0x0a: case 0x1a: case 0x12:
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instruction.addressing_mode = Instruction::Implied;
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break;
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case 0x10:
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instruction.addressing_mode = Instruction::Relative;
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break;
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case 0x01: case 0x03:
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instruction.addressing_mode = Instruction::IndexedIndirectX;
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break;
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case 0x02: case 0x09: case 0x0b:
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instruction.addressing_mode = Instruction::Immediate;
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break;
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case 0x04: case 0x05: case 0x06: case 0x07:
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instruction.addressing_mode = Instruction::ZeroPage;
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break;
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case 0x0c: case 0x0d: case 0x0e: case 0x0f:
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instruction.addressing_mode = (operation == 0x6c) ? Instruction::Indirect : Instruction::Absolute;
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break;
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case 0x11: case 0x13:
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instruction.addressing_mode = Instruction::IndirectIndexedY;
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break;
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case 0x14: case 0x15: case 0x16: case 0x17:
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instruction.addressing_mode =
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(operation == 0x96 || operation == 0xb6 || operation == 0x97 || operation == 0xb7)
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? Instruction::ZeroPageY : Instruction::ZeroPageX;
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break;
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case 0x19: case 0x1b:
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instruction.addressing_mode = Instruction::AbsoluteY;
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break;
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case 0x1c: case 0x1d: case 0x1e: case 0x1f:
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instruction.addressing_mode =
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(operation == 0x9e || operation == 0xbe || operation == 0x9f || operation == 0xbf)
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? Instruction::AbsoluteY : Instruction::AbsoluteX;
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break;
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}
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// Decode operation.
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#define RM_INSTRUCTION(base, op) \
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case base+0x09: case base+0x05: case base+0x15: case base+0x01: \
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case base+0x11: case base+0x0d: case base+0x1d: case base+0x19: \
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instruction.operation = op; \
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break;
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#define URM_INSTRUCTION(base, op) \
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case base+0x07: case base+0x17: case base+0x03: case base+0x13: case base+0x0f: case base+0x1f: case base+0x1b: \
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instruction.operation = op; \
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break;
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#define M_INSTRUCTION(base, op) \
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case base+0x0a: case base+0x06: case base+0x16: case base+0x0e: case base+0x1e: \
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instruction.operation = op; \
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break;
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#define IM_INSTRUCTION(base, op) \
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case base: instruction.operation = op; break;
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switch(operation) {
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default:
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instruction.operation = Instruction::KIL;
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break;
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IM_INSTRUCTION(0x00, Instruction::BRK)
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IM_INSTRUCTION(0x20, Instruction::JSR)
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IM_INSTRUCTION(0x40, Instruction::RTI)
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IM_INSTRUCTION(0x60, Instruction::RTS)
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case 0x4c: case 0x6c:
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instruction.operation = Instruction::JMP;
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break;
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IM_INSTRUCTION(0x10, Instruction::BPL)
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IM_INSTRUCTION(0x30, Instruction::BMI)
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IM_INSTRUCTION(0x50, Instruction::BVC)
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IM_INSTRUCTION(0x70, Instruction::BVS)
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IM_INSTRUCTION(0x90, Instruction::BCC)
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IM_INSTRUCTION(0xb0, Instruction::BCS)
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IM_INSTRUCTION(0xd0, Instruction::BNE)
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IM_INSTRUCTION(0xf0, Instruction::BEQ)
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IM_INSTRUCTION(0xca, Instruction::DEX)
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IM_INSTRUCTION(0x88, Instruction::DEY)
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IM_INSTRUCTION(0xe8, Instruction::INX)
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IM_INSTRUCTION(0xc8, Instruction::INY)
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IM_INSTRUCTION(0xaa, Instruction::TAX)
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IM_INSTRUCTION(0x8a, Instruction::TXA)
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IM_INSTRUCTION(0xa8, Instruction::TAY)
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IM_INSTRUCTION(0x98, Instruction::TYA)
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IM_INSTRUCTION(0xba, Instruction::TSX)
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IM_INSTRUCTION(0x9a, Instruction::TXS)
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IM_INSTRUCTION(0x68, Instruction::PLA)
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IM_INSTRUCTION(0x48, Instruction::PHA)
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IM_INSTRUCTION(0x28, Instruction::PLP)
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IM_INSTRUCTION(0x08, Instruction::PHP)
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IM_INSTRUCTION(0x18, Instruction::CLC)
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IM_INSTRUCTION(0x38, Instruction::SEC)
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IM_INSTRUCTION(0xd8, Instruction::CLD)
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IM_INSTRUCTION(0xf8, Instruction::SED)
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IM_INSTRUCTION(0x58, Instruction::CLI)
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IM_INSTRUCTION(0x78, Instruction::SEI)
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IM_INSTRUCTION(0xb8, Instruction::CLV)
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URM_INSTRUCTION(0x00, Instruction::SLO)
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URM_INSTRUCTION(0x20, Instruction::RLA)
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URM_INSTRUCTION(0x40, Instruction::SRE)
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URM_INSTRUCTION(0x60, Instruction::RRA)
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RM_INSTRUCTION(0x00, Instruction::ORA)
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RM_INSTRUCTION(0x20, Instruction::AND)
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RM_INSTRUCTION(0x40, Instruction::EOR)
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case 0x24: case 0x2c:
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instruction.operation = Instruction::BIT;
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break;
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RM_INSTRUCTION(0x60, Instruction::ADC)
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RM_INSTRUCTION(0xc0, Instruction::CMP)
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RM_INSTRUCTION(0xe0, Instruction::SBC)
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M_INSTRUCTION(0x00, Instruction::ASL)
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M_INSTRUCTION(0x20, Instruction::ROL)
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M_INSTRUCTION(0x40, Instruction::LSR)
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M_INSTRUCTION(0x60, Instruction::ROR)
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case 0xe0: case 0xe4: case 0xec: instruction.operation = Instruction::CPX; break;
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case 0xc0: case 0xc4: case 0xcc: instruction.operation = Instruction::CPY; break;
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case 0xc6: case 0xd6: case 0xce: case 0xde: instruction.operation = Instruction::DEC; break;
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case 0xe6: case 0xf6: case 0xee: case 0xfe: instruction.operation = Instruction::INC; break;
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RM_INSTRUCTION(0xa0, Instruction::LDA)
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case 0x85: case 0x95: case 0x81: case 0x91: case 0x8d: case 0x9d: case 0x99:
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instruction.operation = Instruction::STA;
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break;
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case 0xa2: case 0xa6: case 0xb6: case 0xae: case 0xbe:
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instruction.operation = Instruction::LDX;
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break;
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case 0x86: case 0x96: case 0x8e:
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instruction.operation = Instruction::STX;
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break;
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case 0xa0: case 0xa4: case 0xb4: case 0xac: case 0xbc:
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instruction.operation = Instruction::LDY;
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break;
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case 0x84: case 0x94: case 0x8c:
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instruction.operation = Instruction::STY;
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break;
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case 0x04: case 0x0c: case 0x14: case 0x1a: case 0x1c:
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case 0x34: case 0x3a: case 0x3c: case 0x44: case 0x54: case 0x5a: case 0x5c:
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case 0x64: case 0x74: case 0x7a: case 0x7c:
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case 0x80: case 0x82: case 0x89:
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case 0xc2: case 0xd4: case 0xda: case 0xdc:
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case 0xe2: case 0xea: case 0xf4: case 0xfa: case 0xfc:
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instruction.operation = Instruction::NOP;
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break;
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case 0x87: case 0x97: case 0x83: case 0x8f:
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instruction.operation = Instruction::AXS;
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break;
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case 0xa7: case 0xb7: case 0xa3: case 0xb3: case 0xaf: case 0xbf:
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instruction.operation = Instruction::LAX;
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break;
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URM_INSTRUCTION(0xc0, Instruction::DCP)
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URM_INSTRUCTION(0xe0, Instruction::ISC)
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case 0x0b: case 0x2b:
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instruction.operation = Instruction::ANC;
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break;
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IM_INSTRUCTION(0x4b, Instruction::ALR)
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IM_INSTRUCTION(0x6b, Instruction::ARR)
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IM_INSTRUCTION(0x8b, Instruction::XAA)
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IM_INSTRUCTION(0xab, Instruction::LAX)
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IM_INSTRUCTION(0xcb, Instruction::SAX)
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IM_INSTRUCTION(0xeb, Instruction::SBC)
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case 0x93: case 0x9f:
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instruction.operation = Instruction::AHX;
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break;
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IM_INSTRUCTION(0x9c, Instruction::SHY)
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IM_INSTRUCTION(0x9e, Instruction::SHX)
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IM_INSTRUCTION(0x9b, Instruction::TAS)
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IM_INSTRUCTION(0xbb, Instruction::LAS)
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}
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#undef RM_INSTRUCTION
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#undef URM_INSTRUCTION
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#undef M_INSTRUCTION
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#undef IM_INSTRUCTION
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// Get operand.
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switch(instruction.addressing_mode) {
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// Zero-byte operands.
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case Instruction::Implied:
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instruction.operand = 0;
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break;
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// One-byte operands.
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case Instruction::Immediate:
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case Instruction::ZeroPage: case Instruction::ZeroPageX: case Instruction::ZeroPageY:
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case Instruction::IndexedIndirectX: case Instruction::IndirectIndexedY:
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case Instruction::Relative: {
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std::size_t operand_address = address_mapper(address);
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if(operand_address >= memory.size()) return;
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++address;
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instruction.operand = memory[operand_address];
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}
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break;
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// Two-byte operands.
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case Instruction::Absolute: case Instruction::AbsoluteX: case Instruction::AbsoluteY:
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case Instruction::Indirect: {
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std::size_t low_operand_address = address_mapper(address);
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std::size_t high_operand_address = address_mapper(address + 1);
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if(low_operand_address >= memory.size() || high_operand_address >= memory.size()) return;
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address += 2;
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instruction.operand = memory[low_operand_address] | uint16_t(memory[high_operand_address] << 8);
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}
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break;
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}
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// Store the instruction.
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disassembly.disassembly.instructions_by_address[instruction.address] = instruction;
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// TODO: something wider-ranging than this
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if(
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instruction.addressing_mode == Instruction::Absolute ||
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instruction.addressing_mode == Instruction::ZeroPage
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) {
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const size_t mapped_address = address_mapper(instruction.operand);
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const bool is_external = mapped_address >= memory.size();
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switch(instruction.operation) {
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default: break;
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case Instruction::LDY: case Instruction::LDX: case Instruction::LDA:
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case Instruction::LAX:
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case Instruction::AND: case Instruction::EOR: case Instruction::ORA: case Instruction::BIT:
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case Instruction::ADC: case Instruction::SBC:
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case Instruction::LAS:
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case Instruction::CMP: case Instruction::CPX: case Instruction::CPY:
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(is_external ? disassembly.disassembly.external_loads : disassembly.disassembly.internal_loads)
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.insert(instruction.operand);
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break;
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case Instruction::STY: case Instruction::STX: case Instruction::STA:
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case Instruction::AXS: case Instruction::AHX: case Instruction::SHX: case Instruction::SHY:
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case Instruction::TAS:
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(is_external ? disassembly.disassembly.external_stores : disassembly.disassembly.internal_stores)
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.insert(instruction.operand);
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break;
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case Instruction::SLO: case Instruction::RLA: case Instruction::SRE: case Instruction::RRA:
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case Instruction::DCP: case Instruction::ISC:
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case Instruction::INC: case Instruction::DEC:
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case Instruction::ASL: case Instruction::ROL: case Instruction::LSR: case Instruction::ROR:
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(is_external ? disassembly.disassembly.external_modifies : disassembly.disassembly.internal_modifies)
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.insert(instruction.operand);
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break;
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}
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}
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// Decide on overall flow control.
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// All relative instructions are flow control.
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if(instruction.addressing_mode == Instruction::Relative) {
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uint16_t destination = uint16_t(address + int8_t(instruction.operand));
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disassembly.remaining_entry_points.push_back(destination);
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}
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switch(instruction.operation) {
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default: break;
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case Instruction::KIL:
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case Instruction::RTS:
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case Instruction::RTI:
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case Instruction::BRK: // TODO: check whether IRQ vector is within memory range.
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disassembly.implicit_entry_points.push_back(address);
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return;
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case Instruction::JMP:
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// Adding a new entry point for relative jumps was handled above.
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if(instruction.addressing_mode == Instruction::Absolute) {
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disassembly.remaining_entry_points.push_back(instruction.operand);
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}
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return;
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case Instruction::JSR:
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disassembly.remaining_entry_points.push_back(instruction.operand);
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break;
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}
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}
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}
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};
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} // end of anonymous namespace
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Disassembly Analyser::Static::MOS6502::Disassemble(
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const std::vector<uint8_t> &memory,
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const std::function<std::size_t(uint16_t)> &address_mapper,
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std::vector<uint16_t> entry_points) {
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return Analyser::Static::Disassembly::Disassemble<Disassembly, uint16_t, MOS6502Disassembler>(
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memory,
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address_mapper,
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entry_points,
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false
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);
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}
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