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803 lines
26 KiB
C++
803 lines
26 KiB
C++
//
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// Instruction.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 15/01/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_x86_Instruction_h
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#define InstructionSets_x86_Instruction_h
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#include <cstddef>
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#include <cstdint>
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#include <type_traits>
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namespace InstructionSet {
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namespace x86 {
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/*
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Operations are documented below to establish expectations as to which
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instruction fields will be meaningful for each; this is a work-in-progress
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and may currently contain errors in the opcode descriptions — especially
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where implicit register dependencies are afoot.
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*/
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enum class Operation: uint8_t {
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Invalid,
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//
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// 8086 instructions.
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//
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/// ASCII adjust after addition; source will be AL and destination will be AX.
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AAA,
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/// ASCII adjust before division; destination will be AX and source will be a multiplier.
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AAD,
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/// ASCII adjust after multiplication; destination will be AX and source will be a divider.
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AAM,
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/// ASCII adjust after subtraction; source will be AL and destination will be AX.
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AAS,
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/// Decimal adjust after addition; source and destination will be AL.
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DAA,
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/// Decimal adjust after subtraction; source and destination will be AL.
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DAS,
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/// If data size is word, convert byte into word; source will be AL, destination will be AH.
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/// If data size is DWord, convert word to dword; AX will be expanded to fill EAX.
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/// In both cases, conversion will be by sign extension.
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CBW,
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/// If data size is Word, converts word to double word; source will be AX and destination will be DX.
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/// If data size is DWord, converts double word to quad word (i.e. CDW); source will be EAX and destination will be EDX:EAX.
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/// In both cases, conversion will be by sign extension.
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CWD,
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/// Escape, for a coprocessor; perform the bus cycles necessary to read the source and destination and perform a NOP.
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ESC,
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/// Stops the processor until the next interrupt is fired.
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HLT,
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/// Waits until the WAIT input is asserted; if an interrupt occurs then it is serviced but returns to the WAIT.
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WAIT,
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/// Add with carry; source, destination, operand and displacement will be populated appropriately.
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ADC,
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/// Add; source, destination, operand and displacement will be populated appropriately.
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ADD,
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/// Subtract with borrow; source, destination, operand and displacement will be populated appropriately.
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SBB,
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/// Subtract; source, destination, operand and displacement will be populated appropriately.
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SUB,
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/// Unsigned multiply; multiplies the source value by AX or AL, storing the result in DX:AX or AX.
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MUL,
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/// Single operand signed multiply; multiplies the source value by AX or AL, storing the result in DX:AX or AX.
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IMUL_1,
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/// Unsigned divide; divide the source value by AX or AL, storing the quotient in AL and the remainder in AH.
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DIV,
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/// Signed divide; divide the source value by AX or AL, storing the quotient in AL and the remainder in AH.
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IDIV,
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/// Increment; source, destination, operand and displacement will be populated appropriately.
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INC,
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/// Decrement; source, destination, operand and displacement will be populated appropriately.
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DEC,
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/// Reads from the port specified by source to the destination.
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IN,
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/// Writes from the port specified by destination from the source.
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OUT,
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// Various jumps; see the displacement to calculate targets.
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JO, JNO, JB, JNB, JE, JNE, JBE, JNBE,
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JS, JNS, JP, JNP, JL, JNL, JLE, JNLE,
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/// Far call; see the segment() and offset() fields.
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CALLfar,
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/// Relative call; see displacement().
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CALLrel,
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/// Near call.
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CALLabs,
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/// Return from interrupt.
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IRET,
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/// Near return; if source is not ::None then it will be an ::Immediate indicating how many additional bytes to remove from the stack.
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RETfar,
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/// Far return; if source is not ::None then it will be an ::Immediate indicating how many additional bytes to remove from the stack.
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RETnear,
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/// Near jump with an absolute destination.
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JMPabs,
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/// Near jump with a relative destination.
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JMPrel,
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/// Far jump to the indicated segment and offset.
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JMPfar,
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/// Relative jump performed only if CX = 0; see the displacement.
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JPCX,
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/// Generates a software interrupt of the level stated in the operand.
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INT,
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/// Generates a software interrupt of level 4 if overflow is set.
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INTO,
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/// Load status flags to AH.
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LAHF,
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/// Load status flags from AH.
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SAHF,
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/// Load a segment and offset from the source into DS and the destination.
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LDS,
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/// Load a segment and offset from the source into ES and the destination.
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LES,
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/// Computes the effective address of the source and loads it into the destination.
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LEA,
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/// Compare [bytes or words, per operation size]; source and destination implied to be DS:[SI] and ES:[DI].
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CMPS,
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/// Load string; reads from DS:SI into AL or AX, subject to segment override.
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LODS,
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/// Move string; moves a byte or word from DS:SI to ES:DI. If a segment override is provided, it overrides the the source.
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MOVS,
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/// Scan string; reads a byte or word from DS:SI and compares it to AL or AX.
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SCAS,
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/// Store string; store AL or AX to ES:DI.
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STOS,
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// Perform a possibly-conditional loop, decrementing CX. See the displacement.
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LOOP, LOOPE, LOOPNE,
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/// Loads the destination with the source.
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MOV,
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/// Negatives; source and destination point to the same thing, to negative.
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NEG,
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/// Logical NOT; source and destination point to the same thing, to negative.
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NOT,
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/// Logical AND; source, destination, operand and displacement will be populated appropriately.
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AND,
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/// Logical OR of source onto destination.
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OR,
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/// Logical XOR of source onto destination.
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XOR,
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/// NOP; no further fields.
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NOP,
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/// POP from the stack to destination.
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POP,
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/// POP from the stack to the flags register.
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POPF,
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/// PUSH the source to the stack.
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PUSH,
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/// PUSH the flags register to the stack.
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PUSHF,
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/// Rotate the destination left through carry the number of bits indicated by source; if the source is a register then implicitly its size is 1.
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RCL,
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/// Rotate the destination right through carry the number of bits indicated by source; if the source is a register then implicitly its size is 1.
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RCR,
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/// Rotate the destination left the number of bits indicated by source; if the source is a register then implicitly its size is 1.
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ROL,
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/// Rotate the destination right the number of bits indicated by source; if the source is a register then implicitly its size is 1.
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ROR,
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/// Arithmetic shift left the destination by the number of bits indicated by source; if the source is a register then implicitly its size is 1.
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SAL,
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/// Arithmetic shift right the destination by the number of bits indicated by source; if the source is a register then implicitly its size is 1.
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SAR,
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/// Logical shift right the destination by the number of bits indicated by source; if the source is a register then implicitly its size is 1.
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SHR,
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/// Clear carry flag; no source or destination provided.
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CLC,
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/// Clear direction flag; no source or destination provided.
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CLD,
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/// Clear interrupt flag; no source or destination provided.
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CLI,
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/// Set carry flag.
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STC,
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/// Set decimal flag.
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STD,
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/// Set interrupt flag.
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STI,
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/// Complement carry flag; no source or destination provided.
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CMC,
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/// Compare; source, destination, operand and displacement will be populated appropriately.
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CMP,
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/// Sets flags based on the result of a logical AND of source and destination.
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TEST,
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/// Exchanges the contents of the source and destination.
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XCHG,
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/// Load AL with DS:[AL+BX].
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XLAT,
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//
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// 80186 additions.
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//
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/// Checks whether the signed value in the destination register is within the bounds
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/// stored at the location indicated by the source register, which will point to two
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/// 16- or 32-bit words, the first being a signed lower bound and the signed upper.
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/// Raises a bounds exception if not.
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BOUND,
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/// Create stack frame. See operand() for the nesting level and offset()
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/// for the dynamic storage size.
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ENTER,
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/// Procedure exit; copies BP to SP, then pops a new BP from the stack.
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LEAVE,
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/// Inputs a byte, word or double word from the port specified by DX, writing it to
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/// ES:[e]DI and incrementing or decrementing [e]DI as per the
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/// current EFLAGS DF flag.
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INS,
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/// Outputs a byte, word or double word from ES:[e]DI to the port specified by DX,
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/// incrementing or decrementing [e]DI as per the current EFLAGS DF flag.]
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OUTS,
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/// Pushes all general purpose registers to the stack, in the order:
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/// AX, CX, DX, BX, [original] SP, BP, SI, DI.
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PUSHA,
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/// Pops all general purpose registers from the stack, in the reverse of
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/// the PUSHA order, i.e. DI, SI, BP, [final] SP, BX, DX, CX, AX.
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POPA,
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//
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// 80286 additions.
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//
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// TODO: expand detail on all operations below.
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/// Adjusts requested privilege level.
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ARPL,
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/// Clears the task-switched flag.
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CLTS,
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/// Loads access rights.
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LAR,
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/// Loads the global descriptor table.
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LGDT,
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/// Loads the interrupt descriptor table.
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LIDT,
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/// Loads the local descriptor table.
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LLDT,
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/// Stores the global descriptor table.
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SGDT,
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/// Stores the interrupt descriptor table.
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SIDT,
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/// Stores the local descriptor table.
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SLDT,
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/// Verifies a segment for reading.
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VERR,
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/// Verifies a segment for writing.
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VERW,
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/// Loads the machine status word.
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LMSW,
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/// Stores the machine status word.
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SMSW,
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/// Loads a segment limit
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LSL,
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/// Loads the task register.
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LTR,
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/// Stores the task register.
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STR,
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/// Three-operand form of IMUL; multiply the immediate by the source and write to the destination.
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IMUL_3,
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/// Undocumented (but used); loads all registers, including internal ones.
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LOADALL,
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//
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// 80386 additions.
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//
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/// Loads a pointer to FS.
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LFS,
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/// Loads a pointer to GS.
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LGS,
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/// Loads a pointer to SS.
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LSS,
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/// Shift left double.
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SHLDimm,
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SHLDCL,
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/// Shift right double.
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SHRDimm,
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SHRDCL,
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/// Bit scan forwards.
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BSF,
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/// Bit scan reverse.
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BSR,
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/// Bit test.
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BT,
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/// Bit test and complement.
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BTC,
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/// Bit test and reset.
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BTR,
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/// Bit test and set.
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BTS,
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/// Move from the source to the destination, extending the source with zeros.
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/// The instruction data size dictates the size of the source; the destination will
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/// be either 16- or 32-bit depending on the current processor operating mode.
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MOVZX,
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/// Move from the source to the destination, applying a sign extension.
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/// The instruction data size dictates the size of the source; the destination will
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/// be either 16- or 32-bit depending on the current processor operating mode.
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MOVSX,
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/// Two-operand form of IMUL; multiply the source by the destination and write to the destination.
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IMUL_2,
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// Various conditional sets; each sets the byte at the location given by the operand
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// to $ff if the condition is met; $00 otherwise.
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SETO, SETNO, SETB, SETNB, SETZ, SETNZ, SETBE, SETNBE,
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SETS, SETNS, SETP, SETNP, SETL, SETNL, SETLE, SETNLE,
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// Various special-case moves (i.e. those where it is impractical to extend the
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// Source enum, so the requirement for special handling is loaded into the operation).
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// In all cases the Cx, Dx and Tx Source aliases can be used to reinterpret the relevant
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// source or destination.
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MOVtoCr, MOVfromCr,
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MOVtoDr, MOVfromDr,
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MOVtoTr, MOVfromTr,
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};
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enum class DataSize: uint8_t {
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Byte = 0,
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Word = 1,
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DWord = 2,
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None = 3,
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};
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constexpr int byte_size(DataSize size) {
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return (1 << int(size)) & 7;
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}
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constexpr int bit_size(DataSize size) {
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return (8 << int(size)) & 0x3f;
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}
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enum class AddressSize: uint8_t {
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b16 = 0,
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b32 = 1,
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};
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constexpr DataSize data_size(AddressSize size) {
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return DataSize(int(size) + 1);
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}
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constexpr int byte_size(AddressSize size) {
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return 2 << int(size);
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}
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constexpr int bit_size(AddressSize size) {
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return 16 << int(size);
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}
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enum class Source: uint8_t {
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// These are in SIB order; this matters for packing later on.
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/// AL, AX or EAX depending on size.
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eAX,
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/// CL, CX or ECX depending on size.
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eCX,
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/// DL, DX or EDX depending on size.
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eDX,
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/// BL, BX or BDX depending on size.
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eBX,
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/// AH if size is 1; SP or ESP otherwise.
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eSPorAH,
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/// CH if size is 1; BP or EBP otherwise.
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eBPorCH,
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/// DH if size is 1; SI or ESI otherwise.
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eSIorDH,
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/// BH if size is 1; DI or EDI otherwise.
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eDIorBH,
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// Aliases for the dual-purpose enums.
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eSP = eSPorAH, AH = eSPorAH,
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eBP = eBPorCH, CH = eBPorCH,
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eSI = eSIorDH, DH = eSIorDH,
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eDI = eDIorBH, BH = eDIorBH,
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// Aliases for control, test and debug registers.
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C0 = 0, C1 = 1, C2 = 2, C3 = 3, C4 = 4, C5 = 5, C6 = 6, C7 = 7,
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T0 = 0, T1 = 1, T2 = 2, T3 = 3, T4 = 4, T5 = 5, T6 = 6, T7 = 7,
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D0 = 0, D1 = 1, D2 = 2, D3 = 3, D4 = 4, D5 = 5, D6 = 6, D7 = 7,
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// Selectors.
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ES, CS, SS, DS, FS, GS,
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/// @c None can be treated as a source that produces 0 when encountered;
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/// it is semantically valid to receive it with that meaning in some contexts —
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/// e.g. to indicate no index in indirect addressing.
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/// It's listed here in order to allow an [optional] segment override to fit into three bits.
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None,
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/// The address included within this instruction should be used as the source.
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DirectAddress,
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/// The immediate value included within this instruction should be used as the source.
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Immediate,
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/// The ScaleIndexBase associated with this source should be used.
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Indirect = 0b11000,
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// Elsewhere, as an implementation detail, the low three bits of an indirect source
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// are reused; (Indirect-1) is also used as a sentinel value but is not a valid member
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// of the enum and isn't exposed externally.
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/// The ScaleIndexBase associated with this source should be used, but
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/// its base should be ignored (and is guaranteed to be zero if the default
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/// getter is used).
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IndirectNoBase = Indirect - 1,
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};
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enum class Repetition: uint8_t {
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None, RepE, RepNE
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};
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/// Provides a 32-bit-style scale, index and base; to produce the address this represents,
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/// calcluate base() + (index() << scale()).
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///
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/// This form of indirect addressing is used to describe both 16- and 32-bit indirect addresses,
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/// even though it is a superset of that supported prior to the 80386.
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///
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/// This class can represent only exactly what a SIB byte can — a scale of 0 to 3, a base
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/// that is any one of the eight general purpose registers, and an index that is one of the seven
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/// general purpose registers excluding eSP or is ::None.
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///
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/// It cannot natively describe a base of ::None.
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class ScaleIndexBase {
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public:
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constexpr ScaleIndexBase() noexcept {}
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constexpr ScaleIndexBase(uint8_t sib) noexcept : sib_(sib) {}
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constexpr ScaleIndexBase(int scale, Source index, Source base) noexcept :
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sib_(uint8_t(
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scale << 6 |
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(int(index != Source::None ? index : Source::eSI) << 3) |
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int(base)
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)) {}
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constexpr ScaleIndexBase(Source index, Source base) noexcept : ScaleIndexBase(0, index, base) {}
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constexpr explicit ScaleIndexBase(Source base) noexcept : ScaleIndexBase(0, Source::None, base) {}
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/// @returns the power of two by which to multiply @c index() before adding it to @c base().
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constexpr int scale() const {
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return sib_ >> 6;
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}
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/// @returns the @c index for this address; this is guaranteed to be one of eAX, eBX, eCX, eDX, None, eBP, eSI or eDI.
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constexpr Source index() const {
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constexpr Source sources[] = {
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Source::eAX, Source::eCX, Source::eDX, Source::eBX, Source::None, Source::eBP, Source::eSI, Source::eDI,
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};
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static_assert(sizeof(sources) == 8);
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return sources[(sib_ >> 3) & 0x7];
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}
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/// @returns the @c base for this address; this is guaranteed to be one of eAX, eBX, eCX, eDX, eSP, eBP, eSI or eDI.
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constexpr Source base() const {
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return Source(sib_ & 0x7);
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}
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constexpr uint8_t without_base() const {
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return sib_ & ~0x3;
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}
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bool operator ==(const ScaleIndexBase &rhs) const {
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// Permit either exact equality or index and base being equal
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// but transposed with a scale of 1.
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return
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(sib_ == rhs.sib_) ||
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(
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!scale() && !rhs.scale() &&
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rhs.index() == base() &&
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rhs.base() == index()
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);
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}
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operator uint8_t() const {
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return sib_;
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}
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private:
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// Data is stored directly as an 80386 SIB byte.
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uint8_t sib_ = 0;
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};
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static_assert(sizeof(ScaleIndexBase) == 1);
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static_assert(alignof(ScaleIndexBase) == 1);
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/// Provides the location of an operand's source or destination.
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///
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/// Callers should use .source() as a first point of entry. If it directly nominates a register
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/// then use the register contents directly. If it indicates ::DirectAddress or ::Immediate
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|
/// then ask the instruction for the address or immediate value that was provided in
|
|
/// the instruction.
|
|
///
|
|
/// If .source() indicates ::Indirect then use base(), index() and scale() to construct an address.
|
|
///
|
|
/// In all cases, the applicable segment is indicated by the instruction.
|
|
class DataPointer {
|
|
public:
|
|
/// Constricts a DataPointer referring to the given source; it shouldn't be ::Indirect.
|
|
constexpr DataPointer(Source source) noexcept : source_(source) {}
|
|
|
|
/// Constricts a DataPointer with a source of ::Indirect and the specified sib.
|
|
constexpr DataPointer(ScaleIndexBase sib) noexcept : sib_(sib) {}
|
|
|
|
/// Constructs a DataPointer with a source and SIB; use the source to indicate
|
|
/// whether the base field of the SIB is effective.
|
|
constexpr DataPointer(Source source, ScaleIndexBase sib) noexcept : source_(source), sib_(sib) {}
|
|
|
|
/// Constructs an indirect DataPointer referencing the given base, index and scale.
|
|
/// Automatically maps Source::Indirect to Source::IndirectNoBase if base is Source::None.
|
|
constexpr DataPointer(Source base, Source index, int scale) noexcept :
|
|
source_(base != Source::None ? Source::Indirect : Source::IndirectNoBase),
|
|
sib_(scale, index, base) {}
|
|
|
|
constexpr bool operator ==(const DataPointer &rhs) const {
|
|
// Require a SIB match only if source_ is ::Indirect or ::IndirectNoBase.
|
|
return
|
|
source_ == rhs.source_ && (
|
|
source_ < Source::IndirectNoBase ||
|
|
(source_ == Source::Indirect && sib_ == rhs.sib_) ||
|
|
(source_ == Source::IndirectNoBase && sib_.without_base() == rhs.sib_.without_base())
|
|
);
|
|
}
|
|
|
|
template <bool obscure_indirectNoBase = false> constexpr Source source() const {
|
|
if constexpr (obscure_indirectNoBase) {
|
|
return (source_ >= Source::IndirectNoBase) ? Source::Indirect : source_;
|
|
}
|
|
return source_;
|
|
}
|
|
|
|
constexpr int scale() const {
|
|
return sib_.scale();
|
|
}
|
|
|
|
constexpr Source index() const {
|
|
return sib_.index();
|
|
}
|
|
|
|
template <bool obscure_indirectNoBase = false> constexpr Source base() const {
|
|
if constexpr (obscure_indirectNoBase) {
|
|
return (source_ <= Source::IndirectNoBase) ? Source::None : sib_.base();
|
|
}
|
|
return sib_.base();
|
|
}
|
|
|
|
private:
|
|
Source source_ = Source::Indirect;
|
|
ScaleIndexBase sib_;
|
|
};
|
|
|
|
template<bool is_32bit> class Instruction {
|
|
public:
|
|
Operation operation = Operation::Invalid;
|
|
|
|
bool operator ==(const Instruction<is_32bit> &rhs) const {
|
|
if( operation != rhs.operation ||
|
|
mem_exts_source_ != rhs.mem_exts_source_ ||
|
|
source_data_dest_sib_ != rhs.source_data_dest_sib_) {
|
|
return false;
|
|
}
|
|
|
|
// Have already established above that this and RHS have the
|
|
// same extensions, if any.
|
|
const int extension_count = has_length_extension() + has_displacement() + has_operand();
|
|
for(int c = 0; c < extension_count; c++) {
|
|
if(extensions_[c] != rhs.extensions_[c]) return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
using DisplacementT = typename std::conditional<is_32bit, int32_t, int16_t>::type;
|
|
using ImmediateT = typename std::conditional<is_32bit, uint32_t, uint16_t>::type;
|
|
using AddressT = ImmediateT;
|
|
|
|
private:
|
|
// Packing and encoding of fields is admittedly somewhat convoluted; what this
|
|
// achieves is that instructions will be sized:
|
|
//
|
|
// four bytes + up to three extension words
|
|
// (two bytes for 16-bit instructions, four for 32)
|
|
//
|
|
// Two of the extension words are used to retain an operand and displacement
|
|
// if the instruction has those. The other can store sizes greater than 15
|
|
// bytes (for earlier processors), plus any repetition, segment override or
|
|
// repetition prefixes.
|
|
|
|
// b7: address size;
|
|
// b6: has displacement;
|
|
// b5: has operand;
|
|
// [b4, b0]: source.
|
|
uint8_t mem_exts_source_ = 0;
|
|
|
|
bool has_displacement() const {
|
|
return mem_exts_source_ & (1 << 6);
|
|
}
|
|
bool has_operand() const {
|
|
return mem_exts_source_ & (1 << 5);
|
|
}
|
|
|
|
// [b15, b14]: data size;
|
|
// [b13, b10]: source length (0 => has length extension);
|
|
// [b9, b5]: top five of SIB;
|
|
// [b4, b0]: dest.
|
|
uint16_t source_data_dest_sib_ = 1 << 10; // So that ::Invalid doesn't seem to have a length extension.
|
|
|
|
bool has_length_extension() const {
|
|
return !((source_data_dest_sib_ >> 10) & 15);
|
|
}
|
|
|
|
// {operand}, {displacement}, {length extension}.
|
|
//
|
|
// If length extension is present then:
|
|
//
|
|
// [b15, b6]: source length;
|
|
// [b5, b4]: repetition;
|
|
// [b3, b1]: segment override;
|
|
// b0: lock.
|
|
ImmediateT extensions_[3]{};
|
|
|
|
ImmediateT operand_extension() const {
|
|
return extensions_[0];
|
|
}
|
|
ImmediateT displacement_extension() const {
|
|
return extensions_[(mem_exts_source_ >> 5) & 1];
|
|
}
|
|
ImmediateT length_extension() const {
|
|
return extensions_[((mem_exts_source_ >> 5) & 1) + ((mem_exts_source_ >> 6) & 1)];
|
|
}
|
|
|
|
public:
|
|
/// @returns The number of bytes used for meaningful content within this class. A receiver must use at least @c sizeof(Instruction) bytes
|
|
/// to store an @c Instruction but is permitted to reuse the trailing sizeof(Instruction) - packing_size() for any purpose it likes. Teleologically,
|
|
/// this allows a denser packing of instructions into containers.
|
|
size_t packing_size() const {
|
|
return
|
|
offsetof(Instruction<is_32bit>, extensions) +
|
|
(has_displacement() + has_operand() + has_length_extension()) * sizeof(ImmediateT);
|
|
|
|
// To consider in the future: the length extension is always the last one,
|
|
// and uses only 8 bits of content within 32-bit instructions, so it'd be
|
|
// possible further to trim the packing size on little endian machines.
|
|
//
|
|
// ... but is that a speed improvement? How much space does it save, and
|
|
// is it enough to undo the costs of unaligned data?
|
|
}
|
|
|
|
private:
|
|
// A lookup table to help with stripping parts of the SIB that have been
|
|
// hidden within the source/destination fields.
|
|
static constexpr uint8_t sib_masks[] = {
|
|
0x1f, 0x1f, 0x1f, 0x18
|
|
};
|
|
|
|
public:
|
|
DataPointer source() const {
|
|
return DataPointer(
|
|
Source(mem_exts_source_ & sib_masks[(mem_exts_source_ >> 3) & 3]),
|
|
((source_data_dest_sib_ >> 2) & 0xf8) | (mem_exts_source_ & 0x07)
|
|
);
|
|
}
|
|
DataPointer destination() const {
|
|
return DataPointer(
|
|
Source(source_data_dest_sib_ & sib_masks[(source_data_dest_sib_ >> 3) & 3]),
|
|
((source_data_dest_sib_ >> 2) & 0xf8) | (source_data_dest_sib_ & 0x07)
|
|
);
|
|
}
|
|
bool lock() const {
|
|
return has_length_extension() && length_extension()&1;
|
|
}
|
|
|
|
AddressSize address_size() const {
|
|
return AddressSize(mem_exts_source_ >> 7);
|
|
}
|
|
|
|
/// @returns @c Source::DS if no segment override was found; the overridden segment otherwise.
|
|
/// On x86 a segment override cannot modify the segment used as a destination in string instructions,
|
|
/// or that used by stack instructions, but this function does not spend the time necessary to provide
|
|
/// the correct default for those.
|
|
Source data_segment() const {
|
|
if(!has_length_extension()) return Source::DS;
|
|
return Source(
|
|
int(Source::ES) +
|
|
((length_extension() >> 1) & 7)
|
|
);
|
|
}
|
|
|
|
Repetition repetition() const {
|
|
if(!has_length_extension()) return Repetition::None;
|
|
return Repetition((length_extension() >> 4) & 3);
|
|
}
|
|
DataSize operation_size() const {
|
|
return DataSize(source_data_dest_sib_ >> 14);
|
|
}
|
|
|
|
int length() const {
|
|
const int short_length = (source_data_dest_sib_ >> 10) & 15;
|
|
if(short_length) return short_length;
|
|
return length_extension() >> 6;
|
|
}
|
|
|
|
ImmediateT operand() const {
|
|
const ImmediateT ops[] = {0, operand_extension()};
|
|
return ops[has_operand()];
|
|
}
|
|
DisplacementT displacement() const {
|
|
return DisplacementT(offset());
|
|
}
|
|
|
|
uint16_t segment() const {
|
|
return uint16_t(operand());
|
|
}
|
|
ImmediateT offset() const {
|
|
const ImmediateT offsets[] = {0, displacement_extension()};
|
|
return offsets[has_displacement()];
|
|
}
|
|
|
|
constexpr Instruction() noexcept {}
|
|
constexpr Instruction(Operation operation, int length) noexcept :
|
|
Instruction(operation, Source::None, Source::None, ScaleIndexBase(), false, AddressSize::b16, Source::None, Repetition::None, DataSize::None, 0, 0, length) {}
|
|
constexpr Instruction(
|
|
Operation operation,
|
|
Source source,
|
|
Source destination,
|
|
ScaleIndexBase sib,
|
|
bool lock,
|
|
AddressSize address_size,
|
|
Source segment_override,
|
|
Repetition repetition,
|
|
DataSize data_size,
|
|
DisplacementT displacement,
|
|
ImmediateT operand,
|
|
int length) noexcept :
|
|
operation(operation),
|
|
mem_exts_source_(uint8_t(
|
|
(int(address_size) << 7) |
|
|
(displacement ? 0x40 : 0x00) |
|
|
(operand ? 0x20 : 0x00) |
|
|
int(source) |
|
|
(source == Source::Indirect ? (uint8_t(sib) & 7) : 0)
|
|
)),
|
|
source_data_dest_sib_(uint16_t(
|
|
(int(data_size) << 14) |
|
|
((
|
|
(lock || (segment_override != Source::None) || (length > 15) || (repetition != Repetition::None))
|
|
) ? 0 : (length << 10)) |
|
|
((uint8_t(sib) & 0xf8) << 2) |
|
|
int(destination) |
|
|
(destination == Source::Indirect ? (uint8_t(sib) & 7) : 0)
|
|
)) {
|
|
|
|
// Decisions on whether to include operand, displacement and/or size extension words
|
|
// have implicitly been made in the int packing above; honour them here.
|
|
int extension = 0;
|
|
if(has_operand()) {
|
|
extensions_[extension] = operand;
|
|
++extension;
|
|
}
|
|
if(has_displacement()) {
|
|
extensions_[extension] = ImmediateT(displacement);
|
|
++extension;
|
|
}
|
|
if(has_length_extension()) {
|
|
// As per the rule stated for segment(), this class provides ::DS for any instruction
|
|
// that doesn't have a segment override.
|
|
if(segment_override == Source::None) segment_override = Source::DS;
|
|
extensions_[extension] = ImmediateT(
|
|
(length << 6) | (int(repetition) << 4) | ((int(segment_override) & 7) << 1) | int(lock)
|
|
);
|
|
++extension;
|
|
}
|
|
}
|
|
};
|
|
|
|
static_assert(sizeof(Instruction<true>) <= 16);
|
|
static_assert(sizeof(Instruction<false>) <= 10);
|
|
|
|
}
|
|
}
|
|
|
|
#endif /* InstructionSets_x86_Instruction_h */
|