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537 lines
18 KiB
C++
537 lines
18 KiB
C++
//
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// Amiga.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "Amiga.hpp"
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#include "../../Activity/Source.hpp"
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#include "../MachineTypes.hpp"
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#include "../../Processors/68000/68000.hpp"
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#include "../../Components/6526/6526.hpp"
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#include "../../Analyser/Static/Amiga/Target.hpp"
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#include "../Utility/MemoryPacker.hpp"
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#include "../Utility/MemoryFuzzer.hpp"
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//#define NDEBUG
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#define LOG_PREFIX "[Amiga] "
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#include "../../Outputs/Log.hpp"
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#include "Blitter.hpp"
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namespace Amiga {
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class ConcreteMachine:
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public Activity::Source,
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public CPU::MC68000::BusHandler,
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public MachineTypes::ScanProducer,
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public MachineTypes::TimedMachine,
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public Machine {
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public:
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ConcreteMachine(const Analyser::Static::Amiga::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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mc68000_(*this),
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blitter_(reinterpret_cast<uint16_t *>(memory_.chip_ram.data()), memory_.chip_ram.size()),
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cia_a_handler_(memory_),
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cia_a_(cia_a_handler_),
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cia_b_(cia_b_handler_)
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{
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(void)target;
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// Temporary: use a hard-coded Kickstart selection.
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constexpr ROM::Name rom_name = ROM::Name::AmigaA500Kickstart13;
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ROM::Request request(rom_name);
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auto roms = rom_fetcher(request);
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if(!request.validate(roms)) {
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throw ROMMachine::Error::MissingROMs;
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}
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Memory::PackBigEndian16(roms.find(rom_name)->second, memory_.kickstart.data());
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// NTSC clock rate: 2*3.579545 = 7.15909Mhz.
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// PAL clock rate: 7.09379Mhz.
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set_clock_rate(7'093'790.0);
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}
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// MARK: - MC68000::BusHandler.
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
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// Intended 1-2 step here is:
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//
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// (1) determine when this CPU access will be scheduled;
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// (2) do all the other actions prior to this CPU access being scheduled.
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//
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// (or at least enqueue them, JIT-wise).
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// Advance time.
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// TODO: I think there's a divide-by-ten here. Probably these are driven off the 68000 E clock?
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cia_a_.run_for(cycle.length);
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cia_b_.run_for(cycle.length);
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// Check for assertion of reset.
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if(cycle.operation & Microcycle::Reset) {
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memory_.reset();
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LOG("Reset; PC is around " << PADHEX(8) << mc68000_.get_state().program_counter);
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}
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// Do nothing if no address is exposed.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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// TODO: interrupt acknowledgement.
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// Grab the target address to pick a memory source.
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const uint32_t address = cycle.host_endian_byte_address();
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// if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord)) && !(cycle.operation & Microcycle::IsProgram)) {
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// printf("%06x\n", *cycle.address);
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// }
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if(!memory_.regions[address >> 18].read_write_mask) {
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if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) {
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// Check for various potential chip accesses.
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// Per the manual:
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//
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// CIA A is: 101x xxxx xx01 rrrr xxxx xxx0 (i.e. loaded into high byte)
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// CIA B is: 101x xxxx xx10 rrrr xxxx xxx1 (i.e. loaded into low byte)
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//
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// but in order to map 0xbfexxx to CIA A and 0xbfdxxx to CIA B, I think
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// these might be listed the wrong way around.
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//
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// Additional assumption: the relevant CIA select lines are connected
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// directly to the chip enables.
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if((address & 0xe0'0000) == 0xa0'0000) {
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const int reg = address >> 8;
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LOG("CIA access: " << PADHEX(4) << *cycle.address);
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if(cycle.operation & Microcycle::Read) {
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uint16_t result = 0xffff;
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if(!(address & 0x1000)) result &= 0xff00 | (cia_a_.read(reg) << 0);
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if(!(address & 0x2000)) result &= 0x00ff | (cia_b_.read(reg) << 8);
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cycle.set_value16(result);
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} else {
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if(!(address & 0x1000)) cia_a_.write(reg, cycle.value8_low());
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if(!(address & 0x2000)) cia_b_.write(reg, cycle.value8_high());
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}
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} else if(address >= 0xdf'f000 && address <= 0xdf'f1be) {
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#define RW(address) (address & 0xffe) | ((cycle.operation & Microcycle::Read) << 7)
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#define Read(address) address | 0x1000
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#define Write(address) address
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#define ApplySetClear(target) { \
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const uint16_t value = cycle.value16(); \
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if(value & 0x8000) { \
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target |= (value & 0x7fff); \
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} else { \
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target &= ~(value & 0x7fff); \
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} \
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}
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switch(RW(address)) {
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default:
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LOG("Unimplemented chipset " << (cycle.operation & Microcycle::Read ? "read" : "write") << " " << PADHEX(6) << *cycle.address);
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assert(false);
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break;
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// Disk DMA.
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case Write(0x020): case Write(0x022): case Write(0x024):
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case Write(0x026):
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LOG("TODO: disk DMA; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Refresh.
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case Write(0x028):
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LOG("TODO (maybe): refresh; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Serial port.
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case Write(0x030):
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LOG("TODO: serial data: " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x032):
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LOG("TODO: serial control: " << PADHEX(4) << cycle.value16());
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break;
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// DMA management.
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case Read(0x002):
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LOG("DMA control and status read");
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cycle.set_value16(dma_control_ | blitter_.get_status());
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break;
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case Write(0x096):
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ApplySetClear(dma_control_);
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LOG("DMA control modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{dma_control_});
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break;
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// Interrupts.
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case Write(0x09a):
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ApplySetClear(interrupt_enable_);
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update_interrupts();
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LOG("Interrupt enable mask modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_enable_});
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break;
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case Write(0x09c):
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ApplySetClear(interrupt_requests_);
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update_interrupts();
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LOG("Interrupt request modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_requests_});
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break;
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// Bitplanes.
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case Write(0x100):
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case Write(0x102):
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case Write(0x104):
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case Write(0x106):
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LOG("TODO: Bitplane control; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x108):
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case Write(0x10a):
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LOG("TODO: Bitplane modulo; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x110):
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case Write(0x112):
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case Write(0x114):
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case Write(0x116):
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case Write(0x118):
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case Write(0x11a):
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LOG("TODO: Bitplane data; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Read(0x110): case Read(0x112): case Read(0x114): case Read(0x116):
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case Read(0x118): case Read(0x11a):
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cycle.set_value16(0xffff);
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break;
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// Blitter.
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case Write(0x040): blitter_.set_control(0, cycle.value16()); break;
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case Write(0x042): blitter_.set_control(1, cycle.value16()); break;
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case Write(0x044): blitter_.set_first_word_mask(cycle.value16()); break;
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case Write(0x046): blitter_.set_last_word_mask(cycle.value16()); break;
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case Write(0x048): blitter_.set_pointer(2, 16, cycle.value16()); break;
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case Write(0x04a): blitter_.set_pointer(2, 0, cycle.value16()); break;
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case Write(0x04c): blitter_.set_pointer(1, 16, cycle.value16()); break;
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case Write(0x04e): blitter_.set_pointer(1, 0, cycle.value16()); break;
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case Write(0x050): blitter_.set_pointer(0, 16, cycle.value16()); break;
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case Write(0x052): blitter_.set_pointer(0, 0, cycle.value16()); break;
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case Write(0x054): blitter_.set_pointer(3, 16, cycle.value16()); break;
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case Write(0x056): blitter_.set_pointer(3, 0, cycle.value16()); break;
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case Write(0x058): blitter_.set_size(cycle.value16()); break;
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case Write(0x05a): blitter_.set_minterms(cycle.value16()); break;
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case Write(0x05c): blitter_.set_vertical_size(cycle.value16()); break;
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case Write(0x05e): blitter_.set_horizontal_size(cycle.value16()); break;
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case Write(0x060): blitter_.set_modulo(2, cycle.value16()); break;
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case Write(0x062): blitter_.set_modulo(1, cycle.value16()); break;
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case Write(0x064): blitter_.set_modulo(0, cycle.value16()); break;
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case Write(0x066): blitter_.set_modulo(3, cycle.value16()); break;
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case Write(0x070): blitter_.set_data(2, cycle.value16()); break;
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case Write(0x072): blitter_.set_data(1, cycle.value16()); break;
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case Write(0x074): blitter_.set_data(0, cycle.value16()); break;
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// Copper.
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case Write(0x02e):
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LOG("TODO: coprocessor control " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x080):
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LOG("TODO: coprocessor first location register high " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x082):
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LOG("TODO: coprocessor first location register low " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x084):
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LOG("TODO: coprocessor second location register high " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x086):
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LOG("TODO: coprocessor second location register low " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x088): case Read(0x088):
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LOG("TODO: coprocessor restart at first location");
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break;
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case Write(0x08a): case Read(0x08a):
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LOG("TODO: coprocessor restart at second location");
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break;
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case Write(0x08c):
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LOG("TODO: coprocessor instruction fetch identity " << PADHEX(4) << cycle.value16());
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break;
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// Sprites.
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#define Sprite(index, pointer, position) \
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case Write(pointer + 0): sprites_[index].set_pointer(16, cycle.value16()); break; \
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case Write(pointer + 2): sprites_[index].set_pointer(0, cycle.value16()); break; \
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case Write(position + 0): sprites_[index].set_start_position(cycle.value16()); break; \
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case Write(position + 2): sprites_[index].set_stop_and_control(cycle.value16()); break; \
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case Write(position + 4): sprites_[index].set_image_data(0, cycle.value16()); break; \
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case Write(position + 6): sprites_[index].set_image_data(1, cycle.value16()); break;
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Sprite(0, 0x120, 0x140);
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Sprite(1, 0x124, 0x148);
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Sprite(2, 0x128, 0x150);
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Sprite(3, 0x12c, 0x158);
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Sprite(4, 0x130, 0x160);
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Sprite(5, 0x134, 0x168);
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Sprite(6, 0x138, 0x170);
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Sprite(7, 0x13c, 0x178);
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#undef Sprite
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// Colour palette.
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case Write(0x180): case Write(0x182): case Write(0x184): case Write(0x186):
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case Write(0x188): case Write(0x18a): case Write(0x18c): case Write(0x18e):
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case Write(0x190): case Write(0x192): case Write(0x194): case Write(0x196):
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case Write(0x198): case Write(0x19a): case Write(0x19c): case Write(0x19e):
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case Write(0x1a0): case Write(0x1a2): case Write(0x1a4): case Write(0x1a6):
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case Write(0x1a8): case Write(0x1aa): case Write(0x1ac): case Write(0x1ae):
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case Write(0x1b0): case Write(0x1b2): case Write(0x1b4): case Write(0x1b6):
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case Write(0x1b8): case Write(0x1ba): case Write(0x1bc): case Write(0x1be):
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LOG("TODO: colour palette; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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}
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#undef ApplySetClear
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#undef Write
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#undef Read
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#undef RW
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} else {
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// This'll do for open bus, for now.
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if(cycle.operation & Microcycle::Read) {
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cycle.set_value16(0xffff);
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}
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LOG("Unmapped access to " << PADHEX(4) << *cycle.address);
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}
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}
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} else {
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// A regular memory access.
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cycle.apply(
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&memory_.regions[address >> 18].contents[address],
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memory_.regions[address >> 18].read_write_mask
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);
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}
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return HalfCycles(0);
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}
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private:
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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// MARK: - Memory map.
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struct MemoryMap {
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public:
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std::array<uint8_t, 512*1024> chip_ram{};
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std::array<uint8_t, 512*1024> kickstart{0xff};
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struct MemoryRegion {
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uint8_t *contents = nullptr;
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unsigned int read_write_mask = 0;
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} regions[64]; // i.e. top six bits are used as an index.
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MemoryMap() {
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// Address spaces that matter:
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//
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// 00'0000 – 08'0000: chip RAM. [or overlayed KickStart]
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// – 10'0000: extended chip ram for ECS.
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// – 20'0000: auto-config space (/fast RAM).
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// ...
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// bf'd000 – c0'0000: 8250s.
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// c0'0000 – d8'0000: pseudo-fast RAM.
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// ...
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// dc'0000 – dd'0000: optional real-time clock.
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// df'f000 - e0'0000: custom chip registers.
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// ...
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// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
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// f8'0000 — : 256kb Kickstart if 2.04 or higher.
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// fc'0000 – : 256kb Kickstart otherwise.
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set_region(0xfc'0000, 0x1'00'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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reset();
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}
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void reset() {
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set_overlay(true);
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}
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void set_overlay(bool enabled) {
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if(overlay_ == enabled) {
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return;
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}
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overlay_ = enabled;
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if(enabled) {
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set_region(0x00'0000, 0x08'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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} else {
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// Mirror RAM to fill out the address range up to $20'0000 (?)
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set_region(0x00'0000, 0x08'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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}
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}
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private:
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bool overlay_ = false;
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void set_region(int start, int end, uint8_t *base, unsigned int read_write_mask) {
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assert(!(start & ~0xfc'0000));
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assert(!((end - (1 << 18)) & ~0xfc'0000));
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base -= start;
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for(int c = start >> 18; c < end >> 18; c++) {
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regions[c].contents = base;
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regions[c].read_write_mask = read_write_mask;
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}
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}
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} memory_;
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// MARK: - Interrupts.
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uint16_t interrupt_enable_ = 0;
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uint16_t interrupt_requests_ = 0;
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void update_interrupts() {
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// TODO.
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}
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// MARK: - Sprites.
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struct Sprite {
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void set_pointer(int shift, uint16_t value) {
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LOG("Sprite pointer with shift " << shift << " to " << PADHEX(4) << value);
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}
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void set_start_position(uint16_t value) {
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LOG("Sprite start position " << PADHEX(4) << value);
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}
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void set_stop_and_control(uint16_t value) {
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LOG("Sprite stop and control " << PADHEX(4) << value);
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}
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void set_image_data(int slot, uint16_t value) {
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LOG("Sprite image data " << slot << " to " << PADHEX(4) << value);
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}
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} sprites_[8];
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// MARK: - DMA control, blitter and Paula.
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uint16_t dma_control_ = 0;
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Blitter blitter_;
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// MARK: - CIAs.
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class CIAAHandler: public MOS::MOS6526::PortHandler {
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public:
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CIAAHandler(MemoryMap &map) : map_(map) {}
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void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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// Parallel port output.
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LOG("TODO: parallel output " << PADHEX(2) << +value);
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} else {
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// b7: /FIR1
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// b6: /FIR0
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// b5: /RDY
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// b4: /TRK0
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// b3: /WPRO
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// b2: /CHNG
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// b1: /LED [output]
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// b0: OVL [output]
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LOG("LED & memory map: " << PADHEX(2) << +value);
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if(observer_) {
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observer_->set_led_status(led_name, !(value & 2));
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}
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map_.set_overlay(value & 1);
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}
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}
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uint8_t get_port_input(MOS::MOS6526::Port port) {
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if(port) {
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LOG("TODO: parallel input?");
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} else {
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LOG("TODO: CIA A, port A input — FIR, RDY, TRK0, etc");
|
||
}
|
||
return 0xff;
|
||
}
|
||
|
||
void set_activity_observer(Activity::Observer *observer) {
|
||
observer_ = observer;
|
||
if(observer) {
|
||
observer->register_led(led_name, Activity::Observer::LEDPresentation::Persistent);
|
||
}
|
||
}
|
||
|
||
private:
|
||
MemoryMap &map_;
|
||
Activity::Observer *observer_ = nullptr;
|
||
inline static const std::string led_name = "Power";
|
||
} cia_a_handler_;
|
||
|
||
struct CIABHandler: public MOS::MOS6526::PortHandler {
|
||
void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
|
||
if(port) {
|
||
// Serial port control.
|
||
//
|
||
// b7: /DTR
|
||
// b6: /RTS
|
||
// b5: /CD
|
||
// b4: /CTS
|
||
// b3: /DSR
|
||
// b2: SEL
|
||
// b1: POUT
|
||
// b0: BUSY
|
||
LOG("TODO: Serial control: " << PADHEX(2) << +value);
|
||
} else {
|
||
// Disk motor control, drive and head selection,
|
||
// and stepper control:
|
||
//
|
||
// b7: /MTR
|
||
// b6: /SEL3
|
||
// b5: /SEL2
|
||
// b4: /SEL1
|
||
// b3: /SEL0
|
||
// b2: /SIDE
|
||
// b1: DIR
|
||
// b0: /STEP
|
||
LOG("TODO: Stepping, etc; " << PADHEX(2) << +value);
|
||
}
|
||
}
|
||
} cia_b_handler_;
|
||
|
||
MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a_;
|
||
MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b_;
|
||
|
||
// MARK: - Activity Source
|
||
void set_activity_observer(Activity::Observer *observer) final {
|
||
cia_a_handler_.set_activity_observer(observer);
|
||
}
|
||
|
||
// MARK: - MachineTypes::ScanProducer.
|
||
|
||
void set_scan_target(Outputs::Display::ScanTarget *scan_target) final {
|
||
(void)scan_target;
|
||
}
|
||
|
||
Outputs::Display::ScanStatus get_scaled_scan_status() const {
|
||
return Outputs::Display::ScanStatus();
|
||
}
|
||
|
||
// MARK: - MachineTypes::TimedMachine.
|
||
|
||
void run_for(const Cycles cycles) {
|
||
mc68000_.run_for(cycles);
|
||
}
|
||
};
|
||
|
||
}
|
||
|
||
|
||
using namespace Amiga;
|
||
|
||
Machine *Machine::Amiga(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
|
||
using Target = Analyser::Static::Amiga::Target;
|
||
const Target *const amiga_target = dynamic_cast<const Target *>(target);
|
||
return new Amiga::ConcreteMachine(*amiga_target, rom_fetcher);
|
||
}
|
||
|
||
Machine::~Machine() {}
|