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1030 lines
34 KiB
C++
1030 lines
34 KiB
C++
//
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// PerformImplementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 28/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_M68k_PerformImplementation_h
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#define InstructionSets_M68k_PerformImplementation_h
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#include "../ExceptionVectors.hpp"
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#include <cassert>
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#include <cmath>
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namespace InstructionSet {
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namespace M68k {
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#define u_extend16(x) uint32_t(int16_t(x))
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#define s_extend16(x) int32_t(int16_t(x))
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namespace Primitive {
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/// @returns An int of type @c IntT with only the most-significant bit set.
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template <typename IntT> constexpr IntT top_bit() {
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static_assert(!std::numeric_limits<IntT>::is_signed);
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constexpr IntT max = std::numeric_limits<IntT>::max();
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return max - (max >> 1);
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}
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/// @returns An int with the top bit indicating whether overflow occurred when @c source and @c destination
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/// were either added (if @c is_add is true) or subtracted (if @c is_add is false) and the result was @c result.
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/// All other bits will be clear.
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template <bool is_add, typename IntT>
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static Status::FlagT overflow(IntT source, IntT destination, IntT result) {
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const IntT output_changed = result ^ destination;
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const IntT input_differed = source ^ destination;
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if constexpr (is_add) {
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return top_bit<IntT>() & output_changed & ~input_differed;
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} else {
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return top_bit<IntT>() & output_changed & input_differed;
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}
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}
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/// Performs an add or subtract (as per @c is_add) between @c source and @c destination,
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/// updating @c status. @c is_extend indicates whether this is an extend operation (e.g. ADDX)
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/// or a plain one (e.g. ADD).
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template <bool is_add, bool is_extend, typename IntT>
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static void add_sub(IntT source, IntT &destination, Status &status) {
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static_assert(!std::numeric_limits<IntT>::is_signed);
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const IntT extend = (is_extend && status.extend_flag) ? 1 : 0;
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const IntT result = is_add ?
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(destination + source + extend) :
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(destination - source - extend);
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// Extend operations can reset the zero flag only; non-extend operations
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// can either set it or reset it. Which in the reverse-logic world of
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// zero_result means ORing or storing.
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if constexpr (is_extend) {
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status.zero_result |= Status::FlagT(result);
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} else {
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status.zero_result = Status::FlagT(result);
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}
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status.extend_flag =
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status.carry_flag = is_add ? result < destination : result > destination;
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status.negative_flag = Status::FlagT(result & top_bit<IntT>());
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status.overflow_flag = overflow<is_add>(source, destination, result);
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destination = result;
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}
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/// Performs a compare of @c source to @c destination, setting zero, carry, negative and overflow flags.
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template <typename IntT>
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static void compare(IntT source, IntT destination, Status &status) {
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const IntT result = destination - source;
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status.zero_result = result;
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status.carry_flag = result > destination;
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status.negative_flag = result & top_bit<IntT>();
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status.overflow_flag = Primitive::overflow<false>(source, destination, result);
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}
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/// @returns the name of the bit to be used as a mask for BCLR, BCHG, BSET or BTST for
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/// @c instruction given @c source.
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inline uint32_t mask_bit(const Preinstruction &instruction, uint32_t source) {
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return source & (instruction.mode<1>() == AddressingMode::DataRegisterDirect ? 31 : 7);
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}
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/// Performs a BCLR, BCHG or BSET as specified by @c operation and described by @c instruction, @c source and @c destination, updating @c destination and @c status.
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/// Also makes an appropriate notification to the @c flow_controller.
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template <Operation operation, typename FlowController>
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void bit_manipulate(const Preinstruction &instruction, uint32_t source, uint32_t &destination, Status &status, FlowController &flow_controller) {
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static_assert(
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operation == Operation::BCLR ||
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operation == Operation::BCHG ||
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operation == Operation::BSET);
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const auto bit = mask_bit(instruction, source);
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status.zero_result = destination & (1 << bit);
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switch(operation) {
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case Operation::BCLR: destination &= ~(1 << bit); break;
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case Operation::BCHG: destination ^= (1 << bit); break;
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case Operation::BSET: destination |= (1 << bit); break;
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}
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flow_controller.did_bit_op(int(bit));
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}
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/// Sets @c destination to 0, clears the overflow, carry and negative flags, sets the zero flag.
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template <typename IntT> void clear(IntT &destination, Status &status) {
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destination = 0;
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status.negative_flag = status.overflow_flag = status.carry_flag = status.zero_result = 0;
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}
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template <Operation operation, typename FlowController>
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void apply_sr_ccr(uint16_t source, Status &status, FlowController &flow_controller) {
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static_assert(
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operation == Operation::ANDItoSR || operation == Operation::ANDItoCCR ||
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operation == Operation::EORItoSR || operation == Operation::EORItoCCR ||
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operation == Operation::ORItoSR || operation == Operation::ORItoCCR
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);
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auto sr = status.status();
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switch(operation) {
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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sr &= source;
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break;
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case Operation::EORItoSR: case Operation::EORItoCCR:
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sr ^= source;
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break;
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case Operation::ORItoSR: case Operation::ORItoCCR:
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sr |= source;
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break;
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}
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switch(operation) {
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case Operation::ANDItoSR:
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case Operation::EORItoSR:
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case Operation::ORItoSR:
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status.set_status(sr);
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flow_controller.did_update_status();
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break;
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case Operation::ANDItoCCR:
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case Operation::EORItoCCR:
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case Operation::ORItoCCR:
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status.set_ccr(sr);
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break;
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}
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}
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template <bool is_mulu, typename FlowController>
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void multiply(uint16_t source, uint32_t &destination, Status &status, FlowController &flow_controller) {
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if constexpr (is_mulu) {
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destination = source * uint16_t(destination);
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} else {
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destination = u_extend16(source) * u_extend16(uint16_t(destination));
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}
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status.carry_flag = status.overflow_flag = 0;
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status.zero_result = destination;
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status.negative_flag = status.zero_result & top_bit<uint32_t>();
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if constexpr (is_mulu) {
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flow_controller.did_mulu(source);
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} else {
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flow_controller.did_muls(source);
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}
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}
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template <bool is_divu, bool did_overflow, typename IntT, typename FlowController>
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void did_divide(IntT dividend, IntT divisor, FlowController &flow_controller) {
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if constexpr (is_divu) {
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flow_controller.template did_divu<did_overflow>(dividend, divisor);
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} else {
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flow_controller.template did_divs<did_overflow>(dividend, divisor);
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}
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}
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template <bool is_divu, typename Int16, typename Int32, typename FlowController>
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void divide(uint16_t source, uint32_t &destination, Status &status, FlowController &flow_controller) {
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status.carry_flag = 0;
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const auto dividend = Int32(destination);
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const auto divisor = Int32(Int16(source));
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if(!divisor) {
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status.negative_flag = status.overflow_flag = 0;
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status.zero_result = 1;
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flow_controller.raise_exception(Exception::IntegerDivideByZero);
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did_divide<is_divu, false>(dividend, divisor, flow_controller);
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return;
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}
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const auto quotient = int64_t(dividend) / int64_t(divisor);
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if(quotient != Int32(Int16(quotient))) {
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status.overflow_flag = 1;
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did_divide<is_divu, true>(dividend, divisor, flow_controller);
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return;
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}
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const auto remainder = Int16(dividend % divisor);
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destination = uint32_t((uint32_t(remainder) << 16) | uint16_t(quotient));
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status.overflow_flag = 0;
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status.zero_result = Status::FlagT(quotient);
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status.negative_flag = status.zero_result & 0x8000;
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did_divide<is_divu, false>(dividend, divisor, flow_controller);
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}
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template <typename IntT> void move(IntT source, IntT &destination, Status &status) {
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destination = source;
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status.zero_result = Status::FlagT(source);
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status.negative_flag = status.zero_result & top_bit<IntT>();
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status.overflow_flag = status.carry_flag = 0;
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}
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template <bool is_extend, typename IntT> void negative(IntT &source, Status &status) {
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const IntT result = -source - (is_extend && status.extend_flag ? 1 : 0);
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if constexpr (is_extend) {
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status.zero_result |= result;
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} else {
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status.zero_result = result;
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}
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status.extend_flag = status.carry_flag = result; // i.e. any value other than 0 will result in carry.
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status.negative_flag = result & top_bit<IntT>();
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status.overflow_flag = Primitive::overflow<false>(source, IntT(0), result);
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source = result;
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}
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template <typename IntT> void test(IntT source, Status &status) {
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status.carry_flag = status.overflow_flag = 0;
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status.zero_result = Status::FlagT(source);
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status.negative_flag = status.zero_result & top_bit<IntT>();
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}
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template <typename IntT, typename FlowController> int shift_count(uint8_t source, FlowController &flow_controller) {
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const int count = source & 63;
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flow_controller.template did_shift<IntT>(count);
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return count;
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}
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/// @returns The number of bits in @c IntT.
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template <typename IntT> constexpr int bit_size() {
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return sizeof(IntT) * 8;
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}
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template <typename IntT> void set_neg_zero(IntT result, Status &status) {
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status.zero_result = Status::FlagT(result);
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status.negative_flag = result & top_bit<IntT>();
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}
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/// Perform a rotate without extend, i.e. any of RO[L/R].[b/w/l].
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template <Operation operation, typename IntT, typename FlowController> void rotate(uint32_t source, IntT &destination, Status &status, FlowController &flow_controller) {
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static_assert(
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operation == Operation::ROLb || operation == Operation::ROLw || operation == Operation::ROLl ||
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operation == Operation::RORb || operation == Operation::RORw || operation == Operation::RORl
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);
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const auto size = bit_size<IntT>();
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const auto shift = shift_count<IntT>(uint8_t(source), flow_controller) & (size - 1);
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if(!shift) {
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status.carry_flag = 0;
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} else {
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switch(operation) {
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case Operation::ROLb: case Operation::ROLw: case Operation::ROLl:
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destination = IntT(
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(destination << shift) |
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(destination >> (size - shift))
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);
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status.carry_flag = Status::FlagT(destination & 1);
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break;
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case Operation::RORb: case Operation::RORw: case Operation::RORl:
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destination = IntT(
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(destination >> shift) |
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(destination << (size - shift))
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);
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status.carry_flag = Status::FlagT(destination & top_bit<IntT>());
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break;
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}
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}
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set_neg_zero(destination, status);
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status.overflow_flag = 0;
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}
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/// Perform a rotate-through-extend, i.e. any of ROX[L/R].[b/w/l].
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template <Operation operation, typename IntT, typename FlowController> void rox(uint32_t source, IntT &destination, Status &status, FlowController &flow_controller) {
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static_assert(
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operation == Operation::ROXLb || operation == Operation::ROXLw || operation == Operation::ROXLl ||
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operation == Operation::ROXRb || operation == Operation::ROXRw || operation == Operation::ROXRl
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);
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const auto size = bit_size<IntT>();
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auto shift = shift_count<IntT>(uint8_t(source), flow_controller) % (size + 1);
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if(!shift) {
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// When shift is zero, extend is unaffected but is copied to carry.
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status.carry_flag = status.extend_flag;
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} else {
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switch(operation) {
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case Operation::ROXLb: case Operation::ROXLw: case Operation::ROXLl:
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status.carry_flag = status.extend_flag = Status::FlagT((destination >> (size - shift)) & 1);
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destination = IntT(
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(destination << shift) |
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(IntT(status.extend_flag ? 1 : 0) << (shift - 1)) |
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(destination >> (size + 1 - shift))
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);
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break;
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case Operation::ROXRb: case Operation::ROXRw: case Operation::ROXRl:
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status.carry_flag = status.extend_flag = Status::FlagT(destination & (1 << (shift - 1)));
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destination = IntT(
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(destination >> shift) |
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((status.extend_flag ? top_bit<IntT>() : 0) >> (shift - 1)) |
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(destination << (size + 1 - shift))
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);
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break;
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}
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}
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set_neg_zero(destination, status);
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status.overflow_flag = 0;
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}
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}
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template <
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Model model,
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typename FlowController,
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Operation operation = Operation::Undefined
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> void perform(Preinstruction instruction, CPU::SlicedInt32 &src, CPU::SlicedInt32 &dest, Status &status, FlowController &flow_controller) {
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switch((operation != Operation::Undefined) ? operation : instruction.operation) {
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/*
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ABCD adds the lowest bytes from the source and destination using BCD arithmetic,
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obeying the extend flag.
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*/
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case Operation::ABCD: {
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// Pull out the two halves, for simplicity.
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const uint8_t source = src.b;
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const uint8_t destination = dest.b;
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const int extend = (status.extend_flag ? 1 : 0);
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// Perform the BCD add by evaluating the two nibbles separately.
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const int unadjusted_result = destination + source + extend;
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int result = (destination & 0xf) + (source & 0xf) + extend;
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result +=
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(destination & 0xf0) +
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(source & 0xf0) +
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(((9 - result) >> 4) & 0x06); // i.e. ((result > 0x09) ? 0x06 : 0x00)
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result += ((0x9f - result) >> 4) & 0x60; // i.e. ((result > 0x9f) ? 0x60 : 0x00)
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// Set all flags essentially as if this were normal addition.
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status.zero_result |= result & 0xff;
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status.extend_flag = status.carry_flag = uint_fast32_t(result & ~0xff);
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status.negative_flag = result & 0x80;
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status.overflow_flag = ~unadjusted_result & result & 0x80;
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// Store the result.
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dest.b = uint8_t(result);
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} break;
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// ADD and ADDA add two quantities, the latter sign extending and without setting any flags;
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// ADDQ and SUBQ act as ADD and SUB, but taking the second argument from the instruction code.
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case Operation::ADDb: Primitive::add_sub<true, false>(src.b, dest.b, status); break;
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case Operation::SUBb: Primitive::add_sub<false, false>(src.b, dest.b, status); break;
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case Operation::ADDXb: Primitive::add_sub<true, true>(src.b, dest.b, status); break;
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case Operation::SUBXb: Primitive::add_sub<false, true>(src.b, dest.b, status); break;
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case Operation::ADDw: Primitive::add_sub<true, false>(src.w, dest.w, status); break;
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case Operation::SUBw: Primitive::add_sub<false, false>(src.w, dest.w, status); break;
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case Operation::ADDXw: Primitive::add_sub<true, true>(src.w, dest.w, status); break;
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case Operation::SUBXw: Primitive::add_sub<false, true>(src.w, dest.w, status); break;
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case Operation::ADDl: Primitive::add_sub<true, false>(src.l, dest.l, status); break;
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case Operation::SUBl: Primitive::add_sub<false, false>(src.l, dest.l, status); break;
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case Operation::ADDXl: Primitive::add_sub<true, true>(src.l, dest.l, status); break;
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case Operation::SUBXl: Primitive::add_sub<false, true>(src.l, dest.l, status); break;
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case Operation::ADDAw: dest.l += u_extend16(src.w); break;
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case Operation::ADDAl: dest.l += src.l; break;
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case Operation::SUBAw: dest.l -= u_extend16(src.w); break;
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case Operation::SUBAl: dest.l -= src.l; break;
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// BTST/BCLR/etc: modulo for the mask depends on whether memory or a data register is the target.
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case Operation::BTST:
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status.zero_result = dest.l & (1 << Primitive::mask_bit(instruction, src.l));
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break;
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case Operation::BCLR: Primitive::bit_manipulate<Operation::BCLR>(instruction, src.l, dest.l, status, flow_controller); break;
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case Operation::BCHG: Primitive::bit_manipulate<Operation::BCHG>(instruction, src.l, dest.l, status, flow_controller); break;
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case Operation::BSET: Primitive::bit_manipulate<Operation::BSET>(instruction, src.l, dest.l, status, flow_controller); break;
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case Operation::Bccb:
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flow_controller.template complete_bcc<int8_t>(
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status.evaluate_condition(instruction.condition()),
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int8_t(src.b));
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break;
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case Operation::Bccw:
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flow_controller.template complete_bcc<int16_t>(
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status.evaluate_condition(instruction.condition()),
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int16_t(src.w));
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break;
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case Operation::Bccl:
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flow_controller.template complete_bcc<int32_t>(
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status.evaluate_condition(instruction.condition()),
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int32_t(src.l));
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break;
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case Operation::BSRb:
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flow_controller.bsr(uint32_t(int8_t(src.b)));
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break;
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case Operation::BSRw:
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flow_controller.bsr(uint32_t(int16_t(src.w)));
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break;
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case Operation::BSRl:
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flow_controller.bsr(src.l);
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break;
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case Operation::DBcc: {
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const bool matched_condition = status.evaluate_condition(instruction.condition());
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bool overflowed = false;
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// Classify the dbcc.
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if(!matched_condition) {
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-- src.w;
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overflowed = src.w == 0xffff;
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}
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// Take the branch.
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flow_controller.complete_dbcc(
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matched_condition,
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overflowed,
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int16_t(dest.w));
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} break;
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case Operation::Scc: {
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const bool condition = status.evaluate_condition(instruction.condition());
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src.b = condition ? 0xff : 0x00;
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flow_controller.did_scc(condition);
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} break;
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/*
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CLRs: store 0 to the destination, set the zero flag, and clear
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negative, overflow and carry.
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*/
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case Operation::CLRb: Primitive::clear(src.b, status); break;
|
|
case Operation::CLRw: Primitive::clear(src.w, status); break;
|
|
case Operation::CLRl: Primitive::clear(src.l, status); break;
|
|
|
|
/*
|
|
CMP.b, CMP.l and CMP.w: sets the condition flags (other than extend) based on a subtraction
|
|
of the source from the destination; the result of the subtraction is not stored.
|
|
*/
|
|
case Operation::CMPb: Primitive::compare(src.b, dest.b, status); break;
|
|
case Operation::CMPw: Primitive::compare(src.w, dest.w, status); break;
|
|
case Operation::CMPAw: Primitive::compare(u_extend16(src.w), dest.l, status); break;
|
|
case Operation::CMPAl:
|
|
case Operation::CMPl: Primitive::compare(src.l, dest.l, status); break;
|
|
|
|
// JMP: copies EA(0) to the program counter.
|
|
case Operation::JMP:
|
|
flow_controller.jmp(src.l);
|
|
break;
|
|
|
|
// JSR: jump to EA(0), pushing the current PC to the stack.
|
|
case Operation::JSR:
|
|
flow_controller.jsr(src.l);
|
|
break;
|
|
|
|
/*
|
|
MOVE.b, MOVE.l and MOVE.w: move the least significant byte or word, or the entire long word,
|
|
and set negative, zero, overflow and carry as appropriate.
|
|
*/
|
|
case Operation::MOVEb: Primitive::move(src.b, dest.b, status); break;
|
|
case Operation::MOVEw: Primitive::move(src.w, dest.w, status); break;
|
|
case Operation::MOVEl: Primitive::move(src.l, dest.l, status); break;
|
|
|
|
/*
|
|
MOVEA.l: move the entire long word;
|
|
MOVEA.w: move the least significant word and sign extend it.
|
|
Neither sets any flags.
|
|
*/
|
|
case Operation::MOVEAw:
|
|
dest.l = u_extend16(src.w);
|
|
break;
|
|
|
|
case Operation::MOVEAl:
|
|
dest.l = src.l;
|
|
break;
|
|
|
|
case Operation::LEA:
|
|
dest.l = src.l;
|
|
break;
|
|
|
|
case Operation::PEA:
|
|
flow_controller.pea(src.l);
|
|
break;
|
|
|
|
/*
|
|
Status word moves and manipulations.
|
|
*/
|
|
|
|
case Operation::MOVEtoSR:
|
|
status.set_status(src.w);
|
|
flow_controller.did_update_status();
|
|
break;
|
|
|
|
case Operation::MOVEfromSR:
|
|
src.w = status.status();
|
|
break;
|
|
|
|
case Operation::MOVEtoCCR:
|
|
status.set_ccr(src.w);
|
|
break;
|
|
|
|
case Operation::MOVEtoUSP:
|
|
flow_controller.move_to_usp(src.l);
|
|
break;
|
|
|
|
case Operation::MOVEfromUSP:
|
|
flow_controller.move_from_usp(src.l);
|
|
break;
|
|
|
|
case Operation::EXTbtow:
|
|
src.w = uint16_t(int8_t(src.b));
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
status.zero_result = src.w;
|
|
status.negative_flag = status.zero_result & 0x8000;
|
|
break;
|
|
|
|
case Operation::EXTwtol:
|
|
src.l = u_extend16(src.w);
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
status.zero_result = src.l;
|
|
status.negative_flag = status.zero_result & 0x80000000;
|
|
break;
|
|
|
|
case Operation::ANDItoSR: Primitive::apply_sr_ccr<Operation::ANDItoSR>(src.w, status, flow_controller); break;
|
|
case Operation::EORItoSR: Primitive::apply_sr_ccr<Operation::EORItoSR>(src.w, status, flow_controller); break;
|
|
case Operation::ORItoSR: Primitive::apply_sr_ccr<Operation::ORItoSR>(src.w, status, flow_controller); break;
|
|
case Operation::ANDItoCCR: Primitive::apply_sr_ccr<Operation::ANDItoCCR>(src.w, status, flow_controller); break;
|
|
case Operation::EORItoCCR: Primitive::apply_sr_ccr<Operation::EORItoCCR>(src.w, status, flow_controller); break;
|
|
case Operation::ORItoCCR: Primitive::apply_sr_ccr<Operation::ORItoCCR>(src.w, status, flow_controller); break;
|
|
|
|
/*
|
|
Multiplications.
|
|
*/
|
|
|
|
case Operation::MULU: Primitive::multiply<true>(src.w, dest.l, status, flow_controller); break;
|
|
case Operation::MULS: Primitive::multiply<false>(src.w, dest.l, status, flow_controller); break;
|
|
|
|
/*
|
|
Divisions.
|
|
*/
|
|
|
|
case Operation::DIVU: Primitive::divide<true, uint16_t, uint32_t>(src.w, dest.l, status, flow_controller); break;
|
|
case Operation::DIVS: Primitive::divide<false, int16_t, int32_t>(src.w, dest.l, status, flow_controller); break;
|
|
|
|
// TRAP, which is a nicer form of ILLEGAL.
|
|
case Operation::TRAP:
|
|
flow_controller.template raise_exception<false>(int(src.l + Exception::TrapBase));
|
|
break;
|
|
|
|
case Operation::TRAPV: {
|
|
if(status.overflow_flag) {
|
|
flow_controller.template raise_exception<false>(Exception::TRAPV);
|
|
}
|
|
} break;
|
|
|
|
case Operation::CHK: {
|
|
const bool is_under = s_extend16(dest.w) < 0;
|
|
const bool is_over = s_extend16(dest.w) > s_extend16(src.w);
|
|
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
status.zero_result = dest.w;
|
|
|
|
// Test applied for N:
|
|
//
|
|
// if Dn < 0, set negative flag;
|
|
// otherwise, if Dn > <ea>, reset negative flag.
|
|
if(is_over) status.negative_flag = 0;
|
|
if(is_under) status.negative_flag = 1;
|
|
|
|
// No exception is the default course of action; deviate only if an
|
|
// exception is necessary.
|
|
flow_controller.did_chk(is_under, is_over);
|
|
if(is_under || is_over) {
|
|
flow_controller.template raise_exception<false>(Exception::CHK);
|
|
}
|
|
} break;
|
|
|
|
/*
|
|
NEGs: negatives the destination, setting the zero,
|
|
negative, overflow and carry flags appropriate, and extend.
|
|
|
|
NB: since the same logic as SUB is used to calculate overflow,
|
|
and SUB calculates `destination - source`, the NEGs deliberately
|
|
label 'source' and 'destination' differently from Motorola.
|
|
*/
|
|
case Operation::NEGb: Primitive::negative<false>(src.b, status); break;
|
|
case Operation::NEGw: Primitive::negative<false>(src.w, status); break;
|
|
case Operation::NEGl: Primitive::negative<false>(src.l, status); break;
|
|
|
|
/*
|
|
NEGXs: NEG, with extend.
|
|
*/
|
|
case Operation::NEGXb: Primitive::negative<true>(src.b, status); break;
|
|
case Operation::NEGXw: Primitive::negative<true>(src.w, status); break;
|
|
case Operation::NEGXl: Primitive::negative<true>(src.l, status); break;
|
|
|
|
/*
|
|
The no-op.
|
|
*/
|
|
case Operation::NOP: break;
|
|
|
|
/*
|
|
LINK and UNLINK help with stack frames, allowing a certain
|
|
amount of stack space to be allocated or deallocated.
|
|
*/
|
|
|
|
case Operation::LINKw:
|
|
flow_controller.link(instruction, uint32_t(int16_t(dest.w)));
|
|
break;
|
|
|
|
case Operation::UNLINK:
|
|
flow_controller.unlink(src.l);
|
|
break;
|
|
|
|
/*
|
|
TAS: sets zero and negative depending on the current value of the destination,
|
|
and sets the high bit, using a specialised atomic bus cycle.
|
|
*/
|
|
|
|
case Operation::TAS:
|
|
flow_controller.tas(instruction, src.l);
|
|
break;
|
|
|
|
/*
|
|
Bitwise operators: AND, OR and EOR. All three clear the overflow and carry flags,
|
|
and set zero and negative appropriately.
|
|
*/
|
|
#define op_and(x, y) x &= y
|
|
#define op_or(x, y) x |= y
|
|
#define op_eor(x, y) x ^= y
|
|
|
|
#define bitwise(source, dest, sign_mask, operator) \
|
|
operator(dest, source); \
|
|
status.overflow_flag = status.carry_flag = 0; \
|
|
status.zero_result = dest; \
|
|
status.negative_flag = dest & sign_mask;
|
|
|
|
#define andx(source, dest, sign_mask) bitwise(source, dest, sign_mask, op_and)
|
|
#define eorx(source, dest, sign_mask) bitwise(source, dest, sign_mask, op_eor)
|
|
#define orx(source, dest, sign_mask) bitwise(source, dest, sign_mask, op_or)
|
|
|
|
#define op_bwl(name, op) \
|
|
case Operation::name##b: op(src.b, dest.b, 0x80); break; \
|
|
case Operation::name##w: op(src.w, dest.w, 0x8000); break; \
|
|
case Operation::name##l: op(src.l, dest.l, 0x80000000); break;
|
|
|
|
op_bwl(AND, andx);
|
|
op_bwl(EOR, eorx);
|
|
op_bwl(OR, orx);
|
|
|
|
#undef op_bwl
|
|
#undef orx
|
|
#undef eorx
|
|
#undef andx
|
|
#undef bitwise
|
|
#undef op_eor
|
|
#undef op_or
|
|
#undef op_and
|
|
|
|
// NOTs: take the logical inverse, affecting the negative and zero flags.
|
|
case Operation::NOTb:
|
|
src.b ^= 0xff;
|
|
status.zero_result = src.b;
|
|
status.negative_flag = status.zero_result & 0x80;
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
break;
|
|
|
|
case Operation::NOTw:
|
|
src.w ^= 0xffff;
|
|
status.zero_result = src.w;
|
|
status.negative_flag = status.zero_result & 0x8000;
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
break;
|
|
|
|
case Operation::NOTl:
|
|
src.l ^= 0xffffffff;
|
|
status.zero_result = src.l;
|
|
status.negative_flag = status.zero_result & 0x80000000;
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
break;
|
|
|
|
#define sbcd(d) \
|
|
const int extend = (status.extend_flag ? 1 : 0); \
|
|
const int unadjusted_result = destination - source - extend; \
|
|
\
|
|
const int top = (destination & 0xf0) - (source & 0xf0) - (0x60 & (unadjusted_result >> 4)); \
|
|
\
|
|
int result = (destination & 0xf) - (source & 0xf) - extend; \
|
|
const int low_adjustment = 0x06 & (result >> 4); \
|
|
status.extend_flag = status.carry_flag = Status::FlagT( \
|
|
(unadjusted_result - low_adjustment) & 0x300 \
|
|
); \
|
|
result = result + top - low_adjustment; \
|
|
\
|
|
/* Store the result. */ \
|
|
d = uint8_t(result); \
|
|
\
|
|
/* Set all remaining flags essentially as if this were normal subtraction. */ \
|
|
status.zero_result |= d; \
|
|
status.negative_flag = result & 0x80; \
|
|
status.overflow_flag = unadjusted_result & ~result & 0x80; \
|
|
|
|
/*
|
|
SBCD subtracts the lowest byte of the source from that of the destination using
|
|
BCD arithmetic, obeying the extend flag.
|
|
*/
|
|
case Operation::SBCD: {
|
|
const uint8_t source = src.b;
|
|
const uint8_t destination = dest.b;
|
|
sbcd(dest.b);
|
|
} break;
|
|
|
|
/*
|
|
NBCD is like SBCD except that the result is 0 - source rather than
|
|
destination - source.
|
|
*/
|
|
case Operation::NBCD: {
|
|
const uint8_t source = src.b;
|
|
const uint8_t destination = 0;
|
|
sbcd(src.b);
|
|
} break;
|
|
|
|
#undef sbcd
|
|
|
|
// EXG and SWAP exchange/swap words or long words.
|
|
|
|
case Operation::EXG: {
|
|
const auto temporary = src.l;
|
|
src.l = dest.l;
|
|
dest.l = temporary;
|
|
} break;
|
|
|
|
case Operation::SWAP: {
|
|
uint16_t *const words = reinterpret_cast<uint16_t *>(&src.l);
|
|
const auto temporary = words[0];
|
|
words[0] = words[1];
|
|
words[1] = temporary;
|
|
|
|
status.zero_result = src.l;
|
|
status.negative_flag = temporary & 0x8000;
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
} break;
|
|
|
|
/*
|
|
Shifts and rotates.
|
|
*/
|
|
#define set_neg_zero(v, m) \
|
|
status.zero_result = Status::FlagT(v); \
|
|
status.negative_flag = status.zero_result & Status::FlagT(m);
|
|
|
|
#define set_neg_zero_overflow(v, m) \
|
|
set_neg_zero(v, m); \
|
|
status.overflow_flag = (Status::FlagT(value) ^ status.zero_result) & Status::FlagT(m);
|
|
|
|
#define decode_shift_count(type) \
|
|
int shift_count = src.l & 63; \
|
|
flow_controller.template did_shift<type>(shift_count);
|
|
|
|
#define set_flags_w(t) set_flags(src.w, 0x8000, t)
|
|
|
|
#define asl(destination, size) {\
|
|
decode_shift_count(decltype(destination)); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = status.overflow_flag = 0; \
|
|
} else { \
|
|
destination = (shift_count < size) ? decltype(destination)(value << shift_count) : 0; \
|
|
status.extend_flag = status.carry_flag = Status::FlagT(value) & Status::FlagT( (1u << (size - 1)) >> (shift_count - 1) ); \
|
|
\
|
|
if(shift_count >= size) status.overflow_flag = value && (value != decltype(value)(-1)); \
|
|
else { \
|
|
const auto mask = decltype(destination)(0xffffffff << (size - shift_count)); \
|
|
status.overflow_flag = mask & value && ((mask & value) != mask); \
|
|
} \
|
|
} \
|
|
\
|
|
set_neg_zero(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::ASLm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t(value << 1);
|
|
status.extend_flag = status.carry_flag = value & 0x8000;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::ASLb: asl(dest.b, 8); break;
|
|
case Operation::ASLw: asl(dest.w, 16); break;
|
|
case Operation::ASLl: asl(dest.l, 32); break;
|
|
|
|
#define asr(destination, size) {\
|
|
decode_shift_count(decltype(destination)); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = 0; \
|
|
} else { \
|
|
destination = (shift_count < size) ? \
|
|
decltype(destination)(\
|
|
(value >> shift_count) | \
|
|
((value & decltype(value)(1 << (size - 1)) ? 0xffffffff : 0x000000000) << (size - shift_count)) \
|
|
) : \
|
|
decltype(destination)( \
|
|
(value & decltype(value)(1 << (size - 1))) ? 0xffffffff : 0x000000000 \
|
|
); \
|
|
status.extend_flag = status.carry_flag = Status::FlagT(value) & Status::FlagT(1 << (shift_count - 1)); \
|
|
} \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::ASRm: {
|
|
const auto value = src.w;
|
|
src.w = (value&0x8000) | (value >> 1);
|
|
status.extend_flag = status.carry_flag = value & 1;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::ASRb: asr(dest.b, 8); break;
|
|
case Operation::ASRw: asr(dest.w, 16); break;
|
|
case Operation::ASRl: asr(dest.l, 32); break;
|
|
|
|
|
|
#undef set_neg_zero_overflow
|
|
#define set_neg_zero_overflow(v, m) \
|
|
set_neg_zero(v, m); \
|
|
status.overflow_flag = 0;
|
|
|
|
#undef set_flags
|
|
#define set_flags(v, m, t) \
|
|
status.zero_result = v; \
|
|
status.negative_flag = status.zero_result & (m); \
|
|
status.overflow_flag = 0; \
|
|
status.carry_flag = value & (t);
|
|
|
|
#define lsl(destination, size) {\
|
|
decode_shift_count(decltype(destination)); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = 0; \
|
|
} else { \
|
|
destination = (shift_count < size) ? decltype(destination)(value << shift_count) : 0; \
|
|
status.extend_flag = status.carry_flag = Status::FlagT(value) & Status::FlagT( (1u << (size - 1)) >> (shift_count - 1) ); \
|
|
} \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::LSLm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t(value << 1);
|
|
status.extend_flag = status.carry_flag = value & 0x8000;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::LSLb: lsl(dest.b, 8); break;
|
|
case Operation::LSLw: lsl(dest.w, 16); break;
|
|
case Operation::LSLl: lsl(dest.l, 32); break;
|
|
|
|
#define lsr(destination, size) {\
|
|
decode_shift_count(decltype(destination)); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = 0; \
|
|
} else { \
|
|
destination = (shift_count < size) ? (value >> shift_count) : 0; \
|
|
status.extend_flag = status.carry_flag = value & Status::FlagT(1 << (shift_count - 1)); \
|
|
} \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::LSRm: {
|
|
const auto value = src.w;
|
|
src.w = value >> 1;
|
|
status.extend_flag = status.carry_flag = value & 1;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::LSRb: lsr(dest.b, 8); break;
|
|
case Operation::LSRw: lsr(dest.w, 16); break;
|
|
case Operation::LSRl: lsr(dest.l, 32); break;
|
|
|
|
// ---
|
|
|
|
case Operation::ROLm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t((value << 1) | (value >> 15));
|
|
status.carry_flag = src.w & 0x0001;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::ROLb: Primitive::rotate<Operation::ROLb>(src.l, dest.b, status, flow_controller); break;
|
|
case Operation::ROLw: Primitive::rotate<Operation::ROLw>(src.l, dest.w, status, flow_controller); break;
|
|
case Operation::ROLl: Primitive::rotate<Operation::ROLl>(src.l, dest.l, status, flow_controller); break;
|
|
|
|
case Operation::RORm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t((value >> 1) | (value << 15));
|
|
status.carry_flag = src.w & 0x8000;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::RORb: Primitive::rotate<Operation::RORb>(src.l, dest.b, status, flow_controller); break;
|
|
case Operation::RORw: Primitive::rotate<Operation::RORw>(src.l, dest.w, status, flow_controller); break;
|
|
case Operation::RORl: Primitive::rotate<Operation::RORl>(src.l, dest.l, status, flow_controller); break;
|
|
|
|
case Operation::ROXLm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t((value << 1) | (status.extend_flag ? 0x0001 : 0x0000));
|
|
status.extend_flag = value & 0x8000;
|
|
set_flags_w(0x8000);
|
|
} break;
|
|
case Operation::ROXLb: Primitive::rox<Operation::ROXLb>(src.l, dest.b, status, flow_controller); break;
|
|
case Operation::ROXLw: Primitive::rox<Operation::ROXLw>(src.l, dest.w, status, flow_controller); break;
|
|
case Operation::ROXLl: Primitive::rox<Operation::ROXLl>(src.l, dest.l, status, flow_controller); break;
|
|
|
|
case Operation::ROXRm: {
|
|
const auto value = src.w;
|
|
src.w = (value >> 1) | (status.extend_flag ? 0x8000 : 0x0000);
|
|
status.extend_flag = value & 0x0001;
|
|
set_flags_w(0x0001);
|
|
} break;
|
|
case Operation::ROXRb: Primitive::rox<Operation::ROXRb>(src.l, dest.b, status, flow_controller); break;
|
|
case Operation::ROXRw: Primitive::rox<Operation::ROXRw>(src.l, dest.w, status, flow_controller); break;
|
|
case Operation::ROXRl: Primitive::rox<Operation::ROXRl>(src.l, dest.l, status, flow_controller); break;
|
|
|
|
#undef ror
|
|
#undef rol
|
|
#undef asr
|
|
#undef lsr
|
|
#undef lsl
|
|
#undef asl
|
|
|
|
#undef set_flags
|
|
#undef decode_shift_count
|
|
#undef set_flags_w
|
|
#undef set_neg_zero_overflow
|
|
#undef set_neg_zero
|
|
|
|
case Operation::MOVEPl:
|
|
flow_controller.template movep<uint32_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEPw:
|
|
flow_controller.template movep<uint16_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEMtoRl:
|
|
flow_controller.template movem_toR<uint32_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEMtoMl:
|
|
flow_controller.template movem_toM<uint32_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEMtoRw:
|
|
flow_controller.template movem_toR<uint16_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEMtoMw:
|
|
flow_controller.template movem_toM<uint16_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
/*
|
|
RTE and RTR share an implementation.
|
|
*/
|
|
case Operation::RTR:
|
|
flow_controller.rtr();
|
|
break;
|
|
|
|
case Operation::RTE:
|
|
flow_controller.rte();
|
|
break;
|
|
|
|
case Operation::RTS:
|
|
flow_controller.rts();
|
|
break;
|
|
|
|
/*
|
|
TSTs: compare to zero.
|
|
*/
|
|
|
|
case Operation::TSTb: Primitive::test(src.b, status); break;
|
|
case Operation::TSTw: Primitive::test(src.w, status); break;
|
|
case Operation::TSTl: Primitive::test(src.l, status); break;
|
|
|
|
case Operation::STOP:
|
|
status.set_status(src.w);
|
|
flow_controller.did_update_status();
|
|
flow_controller.stop();
|
|
break;
|
|
|
|
case Operation::RESET:
|
|
flow_controller.reset();
|
|
break;
|
|
|
|
/*
|
|
Development period debugging.
|
|
*/
|
|
default:
|
|
assert(false);
|
|
break;
|
|
}
|
|
|
|
#undef u_extend16
|
|
#undef s_extend16
|
|
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
#endif /* InstructionSets_M68k_PerformImplementation_h */
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