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1925 lines
66 KiB
C++
1925 lines
66 KiB
C++
//
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//
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// PerformImplementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 05/10/2023.
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// Copyright © 2023 Thomas Harte. All rights reserved.
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//
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#ifndef PerformImplementation_h
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#define PerformImplementation_h
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#include "../../../Numeric/Carry.hpp"
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#include "../../../Numeric/RegisterSizes.hpp"
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#include "../Interrupts.hpp"
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#include <utility>
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namespace InstructionSet::x86 {
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template <Model model, typename IntT, AccessType access, typename InstructionT, typename RegistersT, typename MemoryT>
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IntT *resolve(
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InstructionT &instruction,
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Source source,
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DataPointer pointer,
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RegistersT ®isters,
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MemoryT &memory,
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IntT *none = nullptr,
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IntT *immediate = nullptr
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);
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template <Model model, Source source, typename IntT, AccessType access, typename InstructionT, typename RegistersT, typename MemoryT>
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uint32_t address(
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InstructionT &instruction,
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DataPointer pointer,
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RegistersT ®isters,
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MemoryT &memory
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) {
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// TODO: non-word indexes and bases.
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if constexpr (source == Source::DirectAddress) {
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return instruction.offset();
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}
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uint32_t address;
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uint16_t zero = 0;
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address = *resolve<model, uint16_t, access>(instruction, pointer.index(), pointer, registers, memory, &zero);
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if constexpr (is_32bit(model)) {
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address <<= pointer.scale();
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}
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address += instruction.offset();
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if constexpr (source == Source::IndirectNoBase) {
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return address;
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}
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return address + *resolve<model, uint16_t, access>(instruction, pointer.base(), pointer, registers, memory);
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}
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template <Model model, typename IntT, AccessType access, Source source, typename RegistersT>
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IntT *register_(RegistersT ®isters) {
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switch(source) {
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case Source::eAX:
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// Slightly contorted if chain here and below:
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//
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// (i) does the `constexpr` version of a `switch`; and
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// (i) ensures .eax() etc aren't called on @c registers for 16-bit processors, so they need not implement 32-bit storage.
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if constexpr (is_32bit(model) && std::is_same_v<IntT, uint32_t>) { return ®isters.eax(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return ®isters.ax(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return ®isters.al(); }
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else { return nullptr; }
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case Source::eCX:
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if constexpr (is_32bit(model) && std::is_same_v<IntT, uint32_t>) { return ®isters.ecx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return ®isters.cx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return ®isters.cl(); }
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else { return nullptr; }
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case Source::eDX:
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if constexpr (is_32bit(model) && std::is_same_v<IntT, uint32_t>) { return ®isters.edx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return ®isters.dx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return ®isters.dl(); }
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else if constexpr (std::is_same_v<IntT, uint32_t>) { return nullptr; }
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case Source::eBX:
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if constexpr (is_32bit(model) && std::is_same_v<IntT, uint32_t>) { return ®isters.ebx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return ®isters.bx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return ®isters.bl(); }
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else if constexpr (std::is_same_v<IntT, uint32_t>) { return nullptr; }
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case Source::eSPorAH:
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if constexpr (is_32bit(model) && std::is_same_v<IntT, uint32_t>) { return ®isters.esp(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return ®isters.sp(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return ®isters.ah(); }
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else { return nullptr; }
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case Source::eBPorCH:
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if constexpr (is_32bit(model) && std::is_same_v<IntT, uint32_t>) { return ®isters.ebp(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return ®isters.bp(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return ®isters.ch(); }
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else { return nullptr; }
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case Source::eSIorDH:
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if constexpr (is_32bit(model) && std::is_same_v<IntT, uint32_t>) { return ®isters.esi(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return ®isters.si(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return ®isters.dh(); }
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else { return nullptr; }
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case Source::eDIorBH:
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if constexpr (is_32bit(model) && std::is_same_v<IntT, uint32_t>) { return ®isters.edi(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return ®isters.di(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return ®isters.bh(); }
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else { return nullptr; }
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default: return nullptr;
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}
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}
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template <Model model, typename IntT, AccessType access, typename InstructionT, typename RegistersT, typename MemoryT>
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uint32_t address(
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InstructionT &instruction,
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DataPointer pointer,
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RegistersT ®isters,
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MemoryT &memory
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) {
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// TODO: at least on the 8086 this isn't how register 'addresses' are resolved; instead whatever was the last computed address
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// remains in the address register and is returned. Find out what other x86s do and make a decision.
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switch(pointer.source()) {
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default: return 0;
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case Source::eAX: return *register_<model, IntT, access, Source::eAX>(registers);
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case Source::eCX: return *register_<model, IntT, access, Source::eCX>(registers);
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case Source::eDX: return *register_<model, IntT, access, Source::eDX>(registers);
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case Source::eBX: return *register_<model, IntT, access, Source::eBX>(registers);
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case Source::eSPorAH: return *register_<model, IntT, access, Source::eSPorAH>(registers);
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case Source::eBPorCH: return *register_<model, IntT, access, Source::eBPorCH>(registers);
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case Source::eSIorDH: return *register_<model, IntT, access, Source::eSIorDH>(registers);
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case Source::eDIorBH: return *register_<model, IntT, access, Source::eDIorBH>(registers);
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case Source::Indirect: return address<model, Source::Indirect, IntT, access>(instruction, pointer, registers, memory);
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case Source::IndirectNoBase: return address<model, Source::IndirectNoBase, IntT, access>(instruction, pointer, registers, memory);
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case Source::DirectAddress: return address<model, Source::DirectAddress, IntT, access>(instruction, pointer, registers, memory);
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}
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}
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template <Model model, typename IntT, AccessType access, typename InstructionT, typename RegistersT, typename MemoryT>
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IntT *resolve(
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InstructionT &instruction,
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Source source,
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DataPointer pointer,
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RegistersT ®isters,
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MemoryT &memory,
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IntT *none,
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IntT *immediate
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) {
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// Rules:
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//
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// * if this is a memory access, set target_address and break;
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// * otherwise return the appropriate value.
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uint32_t target_address;
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switch(source) {
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case Source::eAX: return register_<model, IntT, access, Source::eAX>(registers);
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case Source::eCX: return register_<model, IntT, access, Source::eCX>(registers);
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case Source::eDX: return register_<model, IntT, access, Source::eDX>(registers);
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case Source::eBX: return register_<model, IntT, access, Source::eBX>(registers);
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case Source::eSPorAH: return register_<model, IntT, access, Source::eSPorAH>(registers);
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case Source::eBPorCH: return register_<model, IntT, access, Source::eBPorCH>(registers);
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case Source::eSIorDH: return register_<model, IntT, access, Source::eSIorDH>(registers);
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case Source::eDIorBH: return register_<model, IntT, access, Source::eDIorBH>(registers);
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// Segment registers are always 16-bit.
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case Source::ES: if constexpr (std::is_same_v<IntT, uint16_t>) return ®isters.es(); else return nullptr;
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case Source::CS: if constexpr (std::is_same_v<IntT, uint16_t>) return ®isters.cs(); else return nullptr;
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case Source::SS: if constexpr (std::is_same_v<IntT, uint16_t>) return ®isters.ss(); else return nullptr;
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case Source::DS: if constexpr (std::is_same_v<IntT, uint16_t>) return ®isters.ds(); else return nullptr;
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// 16-bit models don't have FS and GS.
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case Source::FS: if constexpr (is_32bit(model) && std::is_same_v<IntT, uint16_t>) return ®isters.fs(); else return nullptr;
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case Source::GS: if constexpr (is_32bit(model) && std::is_same_v<IntT, uint16_t>) return ®isters.gs(); else return nullptr;
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case Source::Immediate:
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*immediate = instruction.operand();
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return immediate;
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case Source::None: return none;
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case Source::Indirect:
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target_address = address<model, Source::Indirect, IntT, access>(instruction, pointer, registers, memory);
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break;
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case Source::IndirectNoBase:
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target_address = address<model, Source::IndirectNoBase, IntT, access>(instruction, pointer, registers, memory);
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break;
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case Source::DirectAddress:
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target_address = address<model, Source::DirectAddress, IntT, access>(instruction, pointer, registers, memory);
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break;
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}
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// If execution has reached here then a memory fetch is required.
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// Do it and exit.
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return &memory.template access<IntT, access>(instruction.data_segment(), target_address);
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};
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namespace Primitive {
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// The below takes a reference in order properly to handle PUSH SP, which should place the value of SP after the
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// push onto the stack.
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template <typename IntT, bool preauthorised, typename MemoryT, typename RegistersT>
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void push(IntT &value, MemoryT &memory, RegistersT ®isters) {
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registers.sp_ -= sizeof(IntT);
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memory.template access<IntT, preauthorised ? AccessType::PreAuthorised : AccessType::Write>(
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InstructionSet::x86::Source::SS,
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registers.sp_) = value;
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memory.template write_back<IntT>();
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}
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template <typename IntT, bool preauthorised, typename MemoryT, typename RegistersT>
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IntT pop(MemoryT &memory, RegistersT ®isters) {
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const auto value = memory.template access<IntT, preauthorised ? AccessType::PreAuthorised : AccessType::Read>(
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InstructionSet::x86::Source::SS,
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registers.sp_);
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registers.sp_ += sizeof(IntT);
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return value;
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}
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//
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// Comments below on intended functioning of each operation come from the 1997 edition of the
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// Intel Architecture Software Developer’s Manual; that year all such definitions still fitted within a
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// single volume, Volume 2.
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//
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// Order Number 243191; e.g. https://www.ardent-tool.com/CPU/docs/Intel/IA/243191-002.pdf
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//
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inline void aaa(CPU::RegisterPair16 &ax, Status &status) { // P. 313
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/*
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IF ((AL AND 0FH) > 9) OR (AF = 1)
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THEN
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AL ← (AL + 6);
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AH ← AH + 1;
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AF ← 1;
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CF ← 1;
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ELSE
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AF ← 0;
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CF ← 0;
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FI;
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AL ← AL AND 0FH;
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*/
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/*
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The AF and CF flags are set to 1 if the adjustment results in a decimal carry;
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otherwise they are cleared to 0. The OF, SF, ZF, and PF flags are undefined.
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*/
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if((ax.halves.low & 0x0f) > 9 || status.flag<Flag::AuxiliaryCarry>()) {
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ax.halves.low += 6;
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++ax.halves.high;
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status.set_from<Flag::Carry, Flag::AuxiliaryCarry>(1);
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} else {
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status.set_from<Flag::Carry, Flag::AuxiliaryCarry>(0);
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}
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ax.halves.low &= 0x0f;
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}
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inline void aad(CPU::RegisterPair16 &ax, uint8_t imm, Status &status) {
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/*
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tempAL ← AL;
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tempAH ← AH;
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AL ← (tempAL + (tempAH * imm8)) AND FFH; (* imm8 is set to 0AH for the AAD mnemonic *)
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AH ← 0
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*/
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/*
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The SF, ZF, and PF flags are set according to the result;
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the OF, AF, and CF flags are undefined.
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*/
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ax.halves.low = ax.halves.low + (ax.halves.high * imm);
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ax.halves.high = 0;
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status.set_from<uint8_t, Flag::Zero, Flag::Sign, Flag::ParityOdd>(ax.halves.low);
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}
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template <typename FlowControllerT>
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void aam(CPU::RegisterPair16 &ax, uint8_t imm, Status &status, FlowControllerT &flow_controller) {
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/*
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tempAL ← AL;
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AH ← tempAL / imm8; (* imm8 is set to 0AH for the AAD mnemonic *)
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AL ← tempAL MOD imm8;
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*/
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/*
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The SF, ZF, and PF flags are set according to the result.
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The OF, AF, and CF flags are undefined.
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*/
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/*
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If ... an immediate value of 0 is used, it will cause a #DE (divide error) exception.
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*/
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if(!imm) {
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flow_controller.interrupt(Interrupt::DivideError);
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return;
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}
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ax.halves.high = ax.halves.low / imm;
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ax.halves.low = ax.halves.low % imm;
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status.set_from<uint8_t, Flag::Zero, Flag::Sign, Flag::ParityOdd>(ax.halves.low);
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}
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inline void aas(CPU::RegisterPair16 &ax, Status &status) {
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/*
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IF ((AL AND 0FH) > 9) OR (AF = 1)
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THEN
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AL ← AL – 6;
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AH ← AH – 1;
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AF ← 1;
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CF ← 1;
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ELSE
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CF ← 0;
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AF ← 0;
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FI;
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AL ← AL AND 0FH;
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*/
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/*
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The AF and CF flags are set to 1 if there is a decimal borrow;
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otherwise, they are cleared to 0. The OF, SF, ZF, and PF flags are undefined.
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*/
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if((ax.halves.low & 0x0f) > 9 || status.flag<Flag::AuxiliaryCarry>()) {
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ax.halves.low -= 6;
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--ax.halves.high;
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status.set_from<Flag::Carry, Flag::AuxiliaryCarry>(1);
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} else {
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status.set_from<Flag::Carry, Flag::AuxiliaryCarry>(0);
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}
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ax.halves.low &= 0x0f;
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}
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inline void daa(uint8_t &al, Status &status) {
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/*
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(as modified by https://www.felixcloutier.com/x86/daa ...)
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old_AL ← AL;
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old_CF ← CF;
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CF ← 0;
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IF (((AL AND 0FH) > 9) or AF = 1)
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THEN
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AL ← AL + 6;
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CF ← old_CF OR CarryFromLastAddition; (* CF OR carry from AL ← AL + 6 *)
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AF ← 1;
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ELSE
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AF ← 0;
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FI;
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IF ((old_AL > 99H) or old_CF = 1)
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THEN
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AL ← AL + 60H;
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CF ← 1;
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ELSE
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CF ← 0;
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FI;
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*/
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/*
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The CF and AF flags are set if the adjustment of the value results in a
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decimal carry in either digit of the result (see the “Operation” section above).
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The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
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*/
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const uint8_t old_al = al;
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const auto old_carry = status.flag<Flag::Carry>();
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status.set_from<Flag::Carry>(0);
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if((al & 0x0f) > 0x09 || status.flag<Flag::AuxiliaryCarry>()) {
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status.set_from<Flag::Carry>(old_carry | (al > 0xf9));
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al += 0x06;
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status.set_from<Flag::AuxiliaryCarry>(1);
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} else {
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status.set_from<Flag::AuxiliaryCarry>(0);
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}
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if(old_al > 0x99 || old_carry) {
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al += 0x60;
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status.set_from<Flag::Carry>(1);
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} else {
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status.set_from<Flag::Carry>(0);
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}
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status.set_from<uint8_t, Flag::Zero, Flag::Sign, Flag::ParityOdd>(al);
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}
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inline void das(uint8_t &al, Status &status) {
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/*
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(as modified by https://www.felixcloutier.com/x86/daa ...)
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old_AL ← AL;
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old_CF ← CF;
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CF ← 0;
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IF (((AL AND 0FH) > 9) or AF = 1)
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THEN
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AL ← AL - 6;
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CF ← old_CF OR CarryFromLastAddition; (* CF OR borrow from AL ← AL - 6 *)
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AF ← 1;
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ELSE
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AF ← 0;
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FI;
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IF ((old_AL > 99H) or old_CF = 1)
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THEN
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AL ← AL - 60H;
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CF ← 1;
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ELSE
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CF ← 0;
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FI;
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*/
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/*
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The CF and AF flags are set if the adjustment of the value results in a
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decimal carry in either digit of the result (see the “Operation” section above).
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The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
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*/
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const uint8_t old_al = al;
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const auto old_carry = status.flag<Flag::Carry>();
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status.set_from<Flag::Carry>(0);
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if((al & 0x0f) > 0x09 || status.flag<Flag::AuxiliaryCarry>()) {
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status.set_from<Flag::Carry>(old_carry | (al < 0x06));
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al -= 0x06;
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status.set_from<Flag::AuxiliaryCarry>(1);
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} else {
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status.set_from<Flag::AuxiliaryCarry>(0);
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}
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if(old_al > 0x99 || old_carry) {
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al -= 0x60;
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status.set_from<Flag::Carry>(1);
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} else {
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status.set_from<Flag::Carry>(0);
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}
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status.set_from<uint8_t, Flag::Zero, Flag::Sign, Flag::ParityOdd>(al);
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}
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template <bool with_carry, typename IntT>
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void add(IntT &destination, IntT source, Status &status) {
|
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/*
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DEST ← DEST + SRC [+ CF];
|
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*/
|
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/*
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The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
|
||
*/
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const IntT result = destination + source + (with_carry ? status.carry_bit<IntT>() : 0);
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||
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status.set_from<Flag::Carry>(
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Numeric::carried_out<true, Numeric::bit_size<IntT>() - 1>(destination, source, result));
|
||
status.set_from<Flag::AuxiliaryCarry>(
|
||
Numeric::carried_in<4>(destination, source, result));
|
||
status.set_from<Flag::Overflow>(
|
||
Numeric::overflow<true, IntT>(destination, source, result));
|
||
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(result);
|
||
|
||
destination = result;
|
||
}
|
||
|
||
template <bool with_borrow, bool write_back, typename IntT>
|
||
void sub(IntT &destination, IntT source, Status &status) {
|
||
/*
|
||
DEST ← DEST - (SRC [+ CF]);
|
||
*/
|
||
/*
|
||
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
|
||
*/
|
||
const IntT result = destination - source - (with_borrow ? status.carry_bit<IntT>() : 0);
|
||
|
||
status.set_from<Flag::Carry>(
|
||
Numeric::carried_out<false, Numeric::bit_size<IntT>() - 1>(destination, source, result));
|
||
status.set_from<Flag::AuxiliaryCarry>(
|
||
Numeric::carried_in<4>(destination, source, result));
|
||
status.set_from<Flag::Overflow>(
|
||
Numeric::overflow<false, IntT>(destination, source, result));
|
||
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(result);
|
||
|
||
if constexpr (write_back) {
|
||
destination = result;
|
||
}
|
||
}
|
||
|
||
template <typename IntT>
|
||
void test(IntT &destination, IntT source, Status &status) {
|
||
/*
|
||
TEMP ← SRC1 AND SRC2;
|
||
SF ← MSB(TEMP);
|
||
IF TEMP = 0
|
||
THEN ZF ← 0;
|
||
ELSE ZF ← 1;
|
||
FI:
|
||
PF ← BitwiseXNOR(TEMP[0:7]);
|
||
CF ← 0;
|
||
OF ← 0;
|
||
*/
|
||
/*
|
||
The OF and CF flags are cleared to 0.
|
||
The SF, ZF, and PF flags are set according to the result (see the “Operation” section above).
|
||
The state of the AF flag is undefined.
|
||
*/
|
||
const IntT result = destination & source;
|
||
|
||
status.set_from<Flag::Carry, Flag::Overflow>(0);
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(result);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void xchg(IntT &destination, IntT &source) {
|
||
/*
|
||
TEMP ← DEST
|
||
DEST ← SRC
|
||
SRC ← TEMP
|
||
*/
|
||
std::swap(destination, source);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void mul(IntT &destination_high, IntT &destination_low, IntT source, Status &status) {
|
||
/*
|
||
IF byte operation
|
||
THEN
|
||
AX ← AL * SRC
|
||
ELSE (* word or doubleword operation *)
|
||
IF OperandSize = 16 THEN
|
||
DX:AX ← AX * SRC
|
||
ELSE (* OperandSize = 32 *)
|
||
EDX:EAX ← EAX * SRC
|
||
FI;
|
||
*/
|
||
/*
|
||
The OF and CF flags are cleared to 0 if the upper half of the result is 0;
|
||
otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined.
|
||
*/
|
||
destination_high = (destination_low * source) >> (8 * sizeof(IntT));
|
||
destination_low *= source;
|
||
status.set_from<Flag::Overflow, Flag::Carry>(destination_high);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void imul(IntT &destination_high, IntT &destination_low, IntT source, Status &status) {
|
||
/*
|
||
(as modified by https://www.felixcloutier.com/x86/daa ...)
|
||
|
||
IF (OperandSize = 8)
|
||
THEN
|
||
AX ← AL ∗ SRC (* signed multiplication *)
|
||
IF (AX = SignExtend(AL))
|
||
THEN CF = 0; OF = 0;
|
||
ELSE CF = 1; OF = 1;
|
||
FI;
|
||
ELSE IF OperandSize = 16
|
||
THEN
|
||
DX:AX ← AX ∗ SRC (* signed multiplication *)
|
||
IF (DX:AX = SignExtend(AX))
|
||
THEN CF = 0; OF = 0;
|
||
ELSE CF = 1; OF = 1;
|
||
FI;
|
||
ELSE (* OperandSize = 32 *)
|
||
EDX:EAX ← EAX ∗ SRC (* signed multiplication *)
|
||
IF (EDX:EAX = SignExtend(EAX))
|
||
THEN CF = 0; OF = 0;
|
||
ELSE CF = 1; OF = 1;
|
||
FI;
|
||
FI;
|
||
*/
|
||
using sIntT = typename std::make_signed<IntT>::type;
|
||
destination_high = (sIntT(destination_low) * sIntT(source)) >> (8 * sizeof(IntT));
|
||
destination_low = IntT(sIntT(destination_low) * sIntT(source));
|
||
|
||
const auto sign_extension = (destination_low & Numeric::top_bit<IntT>()) ? IntT(~0) : 0;
|
||
status.set_from<Flag::Overflow, Flag::Carry>(destination_high != sign_extension);
|
||
}
|
||
|
||
template <typename IntT, typename FlowControllerT>
|
||
void div(IntT &destination_high, IntT &destination_low, IntT source, FlowControllerT &flow_controller) {
|
||
/*
|
||
IF SRC = 0
|
||
THEN #DE; (* divide error *)
|
||
FI;
|
||
IF OperandSize = 8 (* word/byte operation *)
|
||
THEN
|
||
temp ← AX / SRC;
|
||
IF temp > FFH
|
||
THEN #DE; (* divide error *) ;
|
||
ELSE
|
||
AL ← temp;
|
||
AH ← AX MOD SRC;
|
||
FI;
|
||
ELSE
|
||
IF OperandSize = 16 (* doubleword/word operation *)
|
||
THEN
|
||
temp ← DX:AX / SRC;
|
||
IF temp > FFFFH
|
||
THEN #DE; (* divide error *) ;
|
||
ELSE
|
||
AX ← temp;
|
||
DX ← DX:AX MOD SRC;
|
||
FI;
|
||
ELSE (* quadword/doubleword operation *)
|
||
temp ← EDX:EAX / SRC;
|
||
IF temp > FFFFFFFFH
|
||
THEN #DE; (* divide error *) ;
|
||
ELSE
|
||
EAX ← temp;
|
||
EDX ← EDX:EAX MOD SRC;
|
||
FI;
|
||
FI;
|
||
FI;
|
||
*/
|
||
/*
|
||
The CF, OF, SF, ZF, AF, and PF flags are undefined.
|
||
*/
|
||
if(!source) {
|
||
flow_controller.interrupt(Interrupt::DivideError);
|
||
return;
|
||
}
|
||
|
||
// TEMPORARY HACK. Will not work with DWords.
|
||
const uint32_t dividend = (destination_high << (8 * sizeof(IntT))) + destination_low;
|
||
const auto result = dividend / source;
|
||
if(IntT(result) != result) {
|
||
flow_controller.interrupt(Interrupt::DivideError);
|
||
return;
|
||
}
|
||
|
||
destination_low = IntT(result);
|
||
destination_high = dividend % source;
|
||
}
|
||
|
||
template <typename IntT, typename FlowControllerT>
|
||
void idiv(IntT &destination_high, IntT &destination_low, IntT source, FlowControllerT &flow_controller) {
|
||
/*
|
||
IF SRC = 0
|
||
THEN #DE; (* divide error *)
|
||
FI;
|
||
IF OperandSize = 8 (* word/byte operation *)
|
||
THEN
|
||
temp ← AX / SRC; (* signed division *)
|
||
IF (temp > 7FH) OR (temp < 80H) (* if a positive result is greater than 7FH or a negative result is less than 80H *)
|
||
THEN #DE; (* divide error *) ;
|
||
ELSE
|
||
AL ← temp;
|
||
AH ← AX MOD SRC;
|
||
FI;
|
||
ELSE
|
||
IF OperandSize = 16 (* doubleword/word operation *)
|
||
THEN
|
||
temp ← DX:AX / SRC; (* signed division *)
|
||
IF (temp > 7FFFH) OR (temp < 8000H) (* if a positive result is greater than 7FFFH or a negative result is less than 8000H *)
|
||
THEN #DE; (* divide error *) ;
|
||
ELSE
|
||
AX ← temp;
|
||
DX ← DX:AX MOD SRC;
|
||
FI;
|
||
ELSE (* quadword/doubleword operation *)
|
||
temp ← EDX:EAX / SRC; (* signed division *)
|
||
IF (temp > 7FFFFFFFH) OR (temp < 80000000H) (* if a positive result is greater than 7FFFFFFFH or a negative result is less than 80000000H *)
|
||
THEN #DE; (* divide error *) ;
|
||
ELSE
|
||
EAX ← temp;
|
||
EDX ← EDX:EAX MOD SRC;
|
||
FI;
|
||
FI;
|
||
FI;
|
||
*/
|
||
/*
|
||
The CF, OF, SF, ZF, AF, and PF flags are undefined.
|
||
*/
|
||
if(!source) {
|
||
flow_controller.interrupt(Interrupt::DivideError);
|
||
return;
|
||
}
|
||
|
||
// TEMPORARY HACK. Will not work with DWords.
|
||
using sIntT = typename std::make_signed<IntT>::type;
|
||
const int32_t dividend = (sIntT(destination_high) << (8 * sizeof(IntT))) + destination_low;
|
||
const auto result = dividend / sIntT(source);
|
||
if(sIntT(result) != result) {
|
||
flow_controller.interrupt(Interrupt::DivideError);
|
||
return;
|
||
}
|
||
|
||
destination_low = IntT(result);
|
||
destination_high = dividend % sIntT(source);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void inc(IntT &destination, Status &status) {
|
||
/*
|
||
DEST ← DEST + 1;
|
||
*/
|
||
/*
|
||
The CF flag is not affected.
|
||
The OF, SF, ZF, AF, and PF flags are set according to the result.
|
||
*/
|
||
++destination;
|
||
|
||
status.set_from<Flag::Overflow>(destination == Numeric::top_bit<IntT>());
|
||
status.set_from<Flag::AuxiliaryCarry>(((destination - 1) ^ destination) & 0x10);
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename IntT, typename RegistersT, typename FlowControllerT>
|
||
void jump(bool condition, IntT displacement, RegistersT ®isters, FlowControllerT &flow_controller) {
|
||
/*
|
||
IF condition
|
||
THEN
|
||
EIP ← EIP + SignExtend(DEST);
|
||
IF OperandSize = 16
|
||
THEN
|
||
EIP ← EIP AND 0000FFFFH;
|
||
FI;
|
||
FI;
|
||
*/
|
||
|
||
// TODO: proper behaviour in 32-bit.
|
||
if(condition) {
|
||
flow_controller.jump(registers.ip() + displacement);
|
||
}
|
||
}
|
||
|
||
template <typename IntT, typename OffsetT, typename RegistersT, typename FlowControllerT>
|
||
void loop(IntT &counter, OffsetT displacement, RegistersT ®isters, FlowControllerT &flow_controller) {
|
||
--counter;
|
||
if(counter) {
|
||
flow_controller.jump(registers.ip() + displacement);
|
||
}
|
||
}
|
||
|
||
template <typename IntT, typename OffsetT, typename RegistersT, typename FlowControllerT>
|
||
void loope(IntT &counter, OffsetT displacement, RegistersT ®isters, Status &status, FlowControllerT &flow_controller) {
|
||
--counter;
|
||
if(counter && status.flag<Flag::Zero>()) {
|
||
flow_controller.jump(registers.ip() + displacement);
|
||
}
|
||
}
|
||
|
||
template <typename IntT, typename OffsetT, typename RegistersT, typename FlowControllerT>
|
||
void loopne(IntT &counter, OffsetT displacement, RegistersT ®isters, Status &status, FlowControllerT &flow_controller) {
|
||
--counter;
|
||
if(counter && !status.flag<Flag::Zero>()) {
|
||
flow_controller.jump(registers.ip() + displacement);
|
||
}
|
||
}
|
||
|
||
template <typename IntT>
|
||
void dec(IntT &destination, Status &status) {
|
||
/*
|
||
DEST ← DEST - 1;
|
||
*/
|
||
/*
|
||
The CF flag is not affected.
|
||
The OF, SF, ZF, AF, and PF flags are set according to the result.
|
||
*/
|
||
status.set_from<Flag::Overflow>(destination == Numeric::top_bit<IntT>());
|
||
|
||
--destination;
|
||
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(destination);
|
||
status.set_from<Flag::AuxiliaryCarry>(((destination + 1) ^ destination) & 0x10);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void and_(IntT &destination, IntT source, Status &status) {
|
||
/*
|
||
DEST ← DEST AND SRC;
|
||
*/
|
||
/*
|
||
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result.
|
||
The state of the AF flag is undefined.
|
||
*/
|
||
destination &= source;
|
||
|
||
status.set_from<Flag::Overflow, Flag::Carry>(0);
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void or_(IntT &destination, IntT source, Status &status) {
|
||
/*
|
||
DEST ← DEST OR SRC;
|
||
*/
|
||
/*
|
||
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result.
|
||
The state of the AF flag is undefined.
|
||
*/
|
||
destination |= source;
|
||
|
||
status.set_from<Flag::Overflow, Flag::Carry>(0);
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void xor_(IntT &destination, IntT source, Status &status) {
|
||
/*
|
||
DEST ← DEST XOR SRC;
|
||
*/
|
||
/*
|
||
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result.
|
||
The state of the AF flag is undefined.
|
||
*/
|
||
destination ^= source;
|
||
|
||
status.set_from<Flag::Overflow, Flag::Carry>(0);
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void neg(IntT &destination, Status &status) {
|
||
/*
|
||
IF DEST = 0
|
||
THEN CF ← 0
|
||
ELSE CF ← 1;
|
||
FI;
|
||
DEST ← –(DEST)
|
||
*/
|
||
/*
|
||
The CF flag cleared to 0 if the source operand is 0; otherwise it is set to 1.
|
||
The OF, SF, ZF, AF, and PF flags are set according to the result.
|
||
*/
|
||
status.set_from<Flag::AuxiliaryCarry>(Numeric::carried_in<4>(IntT(0), destination, IntT(-destination)));
|
||
|
||
destination = -destination;
|
||
|
||
status.set_from<Flag::Carry>(destination);
|
||
status.set_from<Flag::Overflow>(destination == Numeric::top_bit<IntT>());
|
||
status.set_from<IntT, Flag::Zero, Flag::Sign, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void not_(IntT &destination) {
|
||
/*
|
||
DEST ← NOT DEST;
|
||
*/
|
||
/*
|
||
Flags affected: none.
|
||
*/
|
||
destination = ~destination;
|
||
}
|
||
|
||
template <typename IntT, typename RegistersT, typename FlowControllerT>
|
||
void call_relative(IntT offset, RegistersT ®isters, FlowControllerT &flow_controller) {
|
||
flow_controller.call(registers.ip() + offset);
|
||
}
|
||
|
||
template <typename IntT, typename FlowControllerT>
|
||
void call_absolute(IntT target, FlowControllerT &flow_controller) {
|
||
flow_controller.call(target);
|
||
}
|
||
|
||
template <typename IntT, typename FlowControllerT>
|
||
void jump_absolute(IntT target, FlowControllerT &flow_controller) {
|
||
flow_controller.jump(target);
|
||
}
|
||
|
||
template <Model model, typename InstructionT, typename FlowControllerT, typename RegistersT, typename MemoryT>
|
||
void call_far(InstructionT &instruction,
|
||
FlowControllerT &flow_controller,
|
||
RegistersT ®isters,
|
||
MemoryT &memory
|
||
) {
|
||
// TODO: eliminate 16-bit assumption below.
|
||
uint16_t source_address = 0;
|
||
const auto pointer = instruction.destination();
|
||
switch(pointer.source()) {
|
||
default:
|
||
case Source::Immediate: flow_controller.call(instruction.segment(), instruction.offset()); return;
|
||
|
||
case Source::Indirect:
|
||
source_address = address<model, Source::Indirect, uint16_t, AccessType::PreAuthorised>(instruction, pointer, registers, memory);
|
||
break;
|
||
case Source::IndirectNoBase:
|
||
source_address = address<model, Source::IndirectNoBase, uint16_t, AccessType::PreAuthorised>(instruction, pointer, registers, memory);
|
||
break;
|
||
case Source::DirectAddress:
|
||
source_address = address<model, Source::DirectAddress, uint16_t, AccessType::PreAuthorised>(instruction, pointer, registers, memory);
|
||
break;
|
||
}
|
||
|
||
const Source source_segment = instruction.data_segment();
|
||
|
||
const uint16_t offset = memory.template access<uint16_t, AccessType::Read>(source_segment, source_address);
|
||
source_address += 2;
|
||
const uint16_t segment = memory.template access<uint16_t, AccessType::Read>(source_segment, source_address);
|
||
flow_controller.call(segment, offset);
|
||
}
|
||
|
||
template <Model model, typename InstructionT, typename FlowControllerT, typename RegistersT, typename MemoryT>
|
||
void jump_far(InstructionT &instruction,
|
||
FlowControllerT &flow_controller,
|
||
RegistersT ®isters,
|
||
MemoryT &memory
|
||
) {
|
||
// TODO: eliminate 16-bit assumption below.
|
||
uint16_t source_address = 0;
|
||
const auto pointer = instruction.destination();
|
||
switch(pointer.source()) {
|
||
default:
|
||
case Source::Immediate: flow_controller.jump(instruction.segment(), instruction.offset()); return;
|
||
|
||
case Source::Indirect:
|
||
source_address = address<model, Source::Indirect, uint16_t, AccessType::Read>(instruction, pointer, registers, memory);
|
||
break;
|
||
case Source::IndirectNoBase:
|
||
source_address = address<model, Source::IndirectNoBase, uint16_t, AccessType::Read>(instruction, pointer, registers, memory);
|
||
break;
|
||
case Source::DirectAddress:
|
||
source_address = address<model, Source::DirectAddress, uint16_t, AccessType::Read>(instruction, pointer, registers, memory);
|
||
break;
|
||
}
|
||
|
||
const Source source_segment = instruction.data_segment();
|
||
|
||
const uint16_t offset = memory.template access<uint16_t, AccessType::Read>(source_segment, source_address);
|
||
source_address += 2;
|
||
const uint16_t segment = memory.template access<uint16_t, AccessType::Read>(source_segment, source_address);
|
||
flow_controller.jump(segment, offset);
|
||
}
|
||
|
||
template <typename FlowControllerT, typename RegistersT, typename MemoryT>
|
||
void iret(RegistersT ®isters, FlowControllerT &flow_controller, MemoryT &memory, Status &status) {
|
||
// TODO: all modes other than 16-bit real mode.
|
||
memory.preauthorise_stack(sizeof(uint16_t) * 3);
|
||
registers.ip() = pop<uint16_t, true>(memory, registers);
|
||
registers.cs() = pop<uint16_t, true>(memory, registers);
|
||
status.set(pop<uint16_t, true>(memory, registers));
|
||
flow_controller.did_iret();
|
||
}
|
||
|
||
template <typename InstructionT, typename FlowControllerT, typename RegistersT, typename MemoryT>
|
||
void ret_near(InstructionT instruction, RegistersT ®isters, FlowControllerT &flow_controller, MemoryT &memory) {
|
||
registers.ip() = pop<uint16_t, false>(memory, registers);
|
||
registers.sp() += instruction.operand();
|
||
flow_controller.did_near_ret();
|
||
}
|
||
|
||
template <typename InstructionT, typename FlowControllerT, typename RegistersT, typename MemoryT>
|
||
void ret_far(InstructionT instruction, RegistersT ®isters, FlowControllerT &flow_controller, MemoryT &memory) {
|
||
memory.preauthorise_stack(sizeof(uint16_t) * 2);
|
||
registers.ip() = pop<uint16_t, true>(memory, registers);
|
||
registers.cs() = pop<uint16_t, true>(memory, registers);
|
||
registers.sp() += instruction.operand();
|
||
flow_controller.did_far_ret();
|
||
}
|
||
|
||
template <Model model, Source selector, typename InstructionT, typename MemoryT, typename RegistersT>
|
||
void ld(
|
||
InstructionT &instruction,
|
||
uint16_t &destination,
|
||
MemoryT &memory,
|
||
RegistersT ®isters
|
||
) {
|
||
const auto pointer = instruction.source();
|
||
auto source_address = address<model, uint16_t, AccessType::Read>(instruction, pointer, registers, memory);
|
||
const Source source_segment = instruction.data_segment();
|
||
|
||
destination = memory.template access<uint16_t, AccessType::Read>(source_segment, source_address);
|
||
source_address += 2;
|
||
switch(selector) {
|
||
case Source::DS: registers.ds() = memory.template access<uint16_t, AccessType::Read>(source_segment, source_address); break;
|
||
case Source::ES: registers.es() = memory.template access<uint16_t, AccessType::Read>(source_segment, source_address); break;
|
||
}
|
||
}
|
||
|
||
template <Model model, typename IntT, typename InstructionT, typename MemoryT, typename RegistersT>
|
||
void lea(
|
||
const InstructionT &instruction,
|
||
IntT &destination,
|
||
MemoryT &memory,
|
||
RegistersT ®isters
|
||
) {
|
||
// TODO: address size.
|
||
destination = IntT(address<model, uint16_t, AccessType::PreAuthorised>(instruction, instruction.source(), registers, memory));
|
||
}
|
||
|
||
template <typename AddressT, typename InstructionT, typename MemoryT, typename RegistersT>
|
||
void xlat(
|
||
const InstructionT &instruction,
|
||
MemoryT &memory,
|
||
RegistersT ®isters
|
||
) {
|
||
AddressT address;
|
||
if constexpr (std::is_same_v<AddressT, uint16_t>) {
|
||
address = registers.bx() + registers.al();
|
||
}
|
||
|
||
registers.al() = memory.template access<uint8_t, AccessType::Read>(instruction.data_segment(), address);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void mov(IntT &destination, IntT source) {
|
||
destination = source;
|
||
}
|
||
|
||
template <typename FlowControllerT>
|
||
void int_(uint8_t vector, FlowControllerT &flow_controller) {
|
||
flow_controller.interrupt(vector);
|
||
}
|
||
|
||
template <typename FlowControllerT>
|
||
void into(Status &status, FlowControllerT &flow_controller) {
|
||
if(status.flag<Flag::Overflow>()) {
|
||
flow_controller.interrupt(Interrupt::OnOverflow);
|
||
}
|
||
}
|
||
|
||
inline void sahf(uint8_t &ah, Status &status) {
|
||
/*
|
||
EFLAGS(SF:ZF:0:AF:0:PF:1:CF) ← AH;
|
||
*/
|
||
status.set_from<uint8_t, Flag::Sign>(ah);
|
||
status.set_from<Flag::Zero>(!(ah & 0x40));
|
||
status.set_from<Flag::AuxiliaryCarry>(ah & 0x10);
|
||
status.set_from<Flag::ParityOdd>(!(ah & 0x04));
|
||
status.set_from<Flag::Carry>(ah & 0x01);
|
||
}
|
||
|
||
inline void lahf(uint8_t &ah, Status &status) {
|
||
/*
|
||
AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF);
|
||
*/
|
||
ah =
|
||
(status.flag<Flag::Sign>() ? 0x80 : 0x00) |
|
||
(status.flag<Flag::Zero>() ? 0x40 : 0x00) |
|
||
(status.flag<Flag::AuxiliaryCarry>() ? 0x10 : 0x00) |
|
||
(status.flag<Flag::ParityOdd>() ? 0x00 : 0x04) |
|
||
0x02 |
|
||
(status.flag<Flag::Carry>() ? 0x01 : 0x00);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void cbw(IntT &ax) {
|
||
constexpr IntT test_bit = 1 << (sizeof(IntT) * 4 - 1);
|
||
constexpr IntT low_half = (1 << (sizeof(IntT) * 4)) - 1;
|
||
|
||
if(ax & test_bit) {
|
||
ax |= ~low_half;
|
||
} else {
|
||
ax &= low_half;
|
||
}
|
||
}
|
||
|
||
template <typename IntT>
|
||
void cwd(IntT &dx, IntT ax) {
|
||
dx = ax & Numeric::top_bit<IntT>() ? IntT(~0) : IntT(0);
|
||
}
|
||
|
||
// TODO: changes to the interrupt flag do quite a lot more in protected mode.
|
||
inline void clc(Status &status) { status.set_from<Flag::Carry>(0); }
|
||
inline void cld(Status &status) { status.set_from<Flag::Direction>(0); }
|
||
inline void cli(Status &status) { status.set_from<Flag::Interrupt>(0); }
|
||
inline void stc(Status &status) { status.set_from<Flag::Carry>(1); }
|
||
inline void std(Status &status) { status.set_from<Flag::Direction>(1); }
|
||
inline void sti(Status &status) { status.set_from<Flag::Interrupt>(1); }
|
||
inline void cmc(Status &status) { status.set_from<Flag::Carry>(!status.flag<Flag::Carry>()); }
|
||
|
||
inline void salc(uint8_t &al, const Status &status) {
|
||
al = status.flag<Flag::Carry>() ? 0xff : 0x00;
|
||
}
|
||
|
||
template <typename IntT>
|
||
void setmo(IntT &destination, Status &status) {
|
||
destination = ~0;
|
||
status.set_from<Flag::Carry, Flag::AuxiliaryCarry, Flag::Overflow>(0);
|
||
status.set_from<IntT, Flag::Sign, Flag::Zero, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename IntT>
|
||
void setmoc(IntT &destination, uint8_t cl, Status &status) {
|
||
if(cl) setmo(destination, status);
|
||
}
|
||
|
||
template <typename IntT>
|
||
inline void rcl(IntT &destination, uint8_t count, Status &status) {
|
||
/*
|
||
(* RCL and RCR instructions *)
|
||
SIZE ← OperandSize
|
||
CASE (determine count) OF
|
||
SIZE = 8: tempCOUNT ← (COUNT AND 1FH) MOD 9;
|
||
SIZE = 16: tempCOUNT ← (COUNT AND 1FH) MOD 17;
|
||
SIZE = 32: tempCOUNT ← COUNT AND 1FH;
|
||
ESAC;
|
||
*/
|
||
/*
|
||
(* RCL instruction operation *)
|
||
WHILE (tempCOUNT ≠ 0)
|
||
DO
|
||
tempCF ← MSB(DEST);
|
||
DEST ← (DEST * 2) + CF;
|
||
CF ← tempCF;
|
||
tempCOUNT ← tempCOUNT – 1;
|
||
OD;
|
||
ELIHW;
|
||
IF COUNT = 1
|
||
THEN OF ← MSB(DEST) XOR CF;
|
||
ELSE OF is undefined;
|
||
FI;
|
||
*/
|
||
/*
|
||
The CF flag contains the value of the bit shifted into it.
|
||
The OF flag is affected only for single- bit rotates (see “Description” above);
|
||
it is undefined for multi-bit rotates. The SF, ZF, AF, and PF flags are not affected.
|
||
*/
|
||
const auto temp_count = count % (Numeric::bit_size<IntT>() + 1);
|
||
auto carry = status.carry_bit<IntT>();
|
||
switch(temp_count) {
|
||
case 0: break;
|
||
case Numeric::bit_size<IntT>(): {
|
||
const IntT temp_carry = destination & 1;
|
||
destination = (destination >> 1) | (carry << (Numeric::bit_size<IntT>() - 1));
|
||
carry = temp_carry;
|
||
} break;
|
||
default: {
|
||
const IntT temp_carry = destination & (Numeric::top_bit<IntT>() >> (temp_count - 1));
|
||
destination =
|
||
(destination << temp_count) |
|
||
(destination >> (Numeric::bit_size<IntT>() + 1 - temp_count)) |
|
||
(carry << (temp_count - 1));
|
||
carry = temp_carry ? 1 : 0;
|
||
} break;
|
||
}
|
||
|
||
status.set_from<Flag::Carry>(carry);
|
||
status.set_from<Flag::Overflow>(
|
||
((destination >> (Numeric::bit_size<IntT>() - 1)) & 1) ^ carry
|
||
);
|
||
}
|
||
|
||
template <typename IntT>
|
||
inline void rcr(IntT &destination, uint8_t count, Status &status) {
|
||
/*
|
||
(* RCR instruction operation *)
|
||
IF COUNT = 1
|
||
THEN OF ← MSB(DEST) XOR CF;
|
||
ELSE OF is undefined;
|
||
FI;
|
||
WHILE (tempCOUNT ≠ 0)
|
||
DO
|
||
tempCF ← LSB(SRC);
|
||
DEST ← (DEST / 2) + (CF * 2SIZE);
|
||
CF ← tempCF;
|
||
tempCOUNT ← tempCOUNT – 1;
|
||
OD;
|
||
*/
|
||
auto carry = status.carry_bit<IntT>();
|
||
status.set_from<Flag::Overflow>(
|
||
((destination >> (Numeric::bit_size<IntT>() - 1)) & 1) ^ carry
|
||
);
|
||
|
||
const auto temp_count = count % (Numeric::bit_size<IntT>() + 1);
|
||
switch(temp_count) {
|
||
case 0: break;
|
||
case Numeric::bit_size<IntT>(): {
|
||
const IntT temp_carry = destination & Numeric::top_bit<IntT>();
|
||
destination = (destination << 1) | carry;
|
||
carry = temp_carry;
|
||
} break;
|
||
default: {
|
||
const IntT temp_carry = destination & (1 << (temp_count - 1));
|
||
destination =
|
||
(destination >> temp_count) |
|
||
(destination << (Numeric::bit_size<IntT>() + 1 - temp_count)) |
|
||
(carry << (Numeric::bit_size<IntT>() - temp_count));
|
||
carry = temp_carry;
|
||
} break;
|
||
}
|
||
|
||
status.set_from<Flag::Carry>(carry);
|
||
}
|
||
|
||
template <typename IntT>
|
||
inline void rol(IntT &destination, uint8_t count, Status &status) {
|
||
/*
|
||
(* ROL and ROR instructions *)
|
||
SIZE ← OperandSize
|
||
CASE (determine count) OF
|
||
SIZE = 8: tempCOUNT ← COUNT MOD 8;
|
||
SIZE = 16: tempCOUNT ← COUNT MOD 16;
|
||
SIZE = 32: tempCOUNT ← COUNT MOD 32;
|
||
ESAC;
|
||
*/
|
||
/*
|
||
(* ROL instruction operation *)
|
||
WHILE (tempCOUNT ≠ 0)
|
||
DO
|
||
tempCF ← MSB(DEST);
|
||
DEST ← (DEST * 2) + tempCF;
|
||
tempCOUNT ← tempCOUNT – 1;
|
||
OD;
|
||
ELIHW;
|
||
IF COUNT = 1
|
||
THEN OF ← MSB(DEST) XOR CF;
|
||
ELSE OF is undefined;
|
||
FI;
|
||
*/
|
||
/*
|
||
The CF flag contains the value of the bit shifted into it.
|
||
The OF flag is affected only for single- bit rotates (see “Description” above);
|
||
it is undefined for multi-bit rotates. The SF, ZF, AF, and PF flags are not affected.
|
||
*/
|
||
const auto temp_count = count & (Numeric::bit_size<IntT>() - 1);
|
||
if(!count) {
|
||
// TODO: is this 8086-specific? i.e. do the other x86s also exit without affecting flags when temp_count = 0?
|
||
return;
|
||
}
|
||
if(temp_count) {
|
||
destination =
|
||
(destination << temp_count) |
|
||
(destination >> (Numeric::bit_size<IntT>() - temp_count));
|
||
}
|
||
|
||
status.set_from<Flag::Carry>(destination & 1);
|
||
status.set_from<Flag::Overflow>(
|
||
((destination >> (Numeric::bit_size<IntT>() - 1)) ^ destination) & 1
|
||
);
|
||
}
|
||
|
||
template <typename IntT>
|
||
inline void ror(IntT &destination, uint8_t count, Status &status) {
|
||
/*
|
||
(* ROL and ROR instructions *)
|
||
SIZE ← OperandSize
|
||
CASE (determine count) OF
|
||
SIZE = 8: tempCOUNT ← COUNT MOD 8;
|
||
SIZE = 16: tempCOUNT ← COUNT MOD 16;
|
||
SIZE = 32: tempCOUNT ← COUNT MOD 32;
|
||
ESAC;
|
||
*/
|
||
/*
|
||
(* ROR instruction operation *)
|
||
WHILE (tempCOUNT ≠ 0)
|
||
DO
|
||
tempCF ← LSB(DEST);
|
||
DEST ← (DEST / 2) + (tempCF * 2^SIZE);
|
||
tempCOUNT ← tempCOUNT – 1;
|
||
OD;
|
||
ELIHW;
|
||
IF COUNT = 1
|
||
THEN OF ← MSB(DEST) XOR MSB - 1 (DEST);
|
||
ELSE OF is undefined;
|
||
FI;
|
||
*/
|
||
/*
|
||
The CF flag contains the value of the bit shifted into it.
|
||
The OF flag is affected only for single- bit rotates (see “Description” above);
|
||
it is undefined for multi-bit rotates. The SF, ZF, AF, and PF flags are not affected.
|
||
*/
|
||
const auto temp_count = count & (Numeric::bit_size<IntT>() - 1);
|
||
if(!count) {
|
||
// TODO: is this 8086-specific? i.e. do the other x86s also exit without affecting flags when temp_count = 0?
|
||
return;
|
||
}
|
||
if(temp_count) {
|
||
destination =
|
||
(destination >> temp_count) |
|
||
(destination << (Numeric::bit_size<IntT>() - temp_count));
|
||
}
|
||
|
||
status.set_from<Flag::Carry>(destination & Numeric::top_bit<IntT>());
|
||
status.set_from<Flag::Overflow>(
|
||
(destination ^ (destination << 1)) & Numeric::top_bit<IntT>()
|
||
);
|
||
}
|
||
|
||
/*
|
||
tempCOUNT ← (COUNT AND 1FH);
|
||
tempDEST ← DEST;
|
||
WHILE (tempCOUNT ≠ 0)
|
||
DO
|
||
IF instruction is SAL or SHL
|
||
THEN
|
||
CF ← MSB(DEST);
|
||
ELSE (* instruction is SAR or SHR *)
|
||
CF ← LSB(DEST);
|
||
FI;
|
||
IF instruction is SAL or SHL
|
||
THEN
|
||
DEST ← DEST ∗ 2;
|
||
ELSE
|
||
IF instruction is SAR
|
||
THEN
|
||
DEST ← DEST / 2 (*Signed divide, rounding toward negative infinity*);
|
||
ELSE (* instruction is SHR *)
|
||
DEST ← DEST / 2 ; (* Unsigned divide *);
|
||
FI;
|
||
FI;
|
||
tempCOUNT ← tempCOUNT – 1;
|
||
OD;
|
||
(* Determine overflow for the various instructions *)
|
||
IF COUNT = 1
|
||
THEN
|
||
IF instruction is SAL or SHL
|
||
THEN
|
||
OF ← MSB(DEST) XOR CF;
|
||
ELSE
|
||
IF instruction is SAR
|
||
THEN
|
||
OF ← 0;
|
||
ELSE (* instruction is SHR *)
|
||
OF ← MSB(tempDEST);
|
||
FI;
|
||
FI;
|
||
ELSE
|
||
IF COUNT = 0
|
||
THEN
|
||
All flags remain unchanged;
|
||
ELSE (* COUNT neither 1 or 0 *)
|
||
OF ← undefined;
|
||
FI;
|
||
FI;
|
||
*/
|
||
/*
|
||
The CF flag contains the value of the last bit shifted out of the destination operand;
|
||
it is undefined for SHL and SHR instructions where the count is greater than or equal to
|
||
the size (in bits) of the destination operand. The OF flag is affected only for 1-bit shifts
|
||
(see “Description” above); otherwise, it is undefined.
|
||
|
||
The SF, ZF, and PF flags are set according to the result. If the count is 0, the flags are not affected.
|
||
For a non-zero count, the AF flag is undefined.
|
||
*/
|
||
template <typename IntT>
|
||
inline void sal(IntT &destination, uint8_t count, Status &status) {
|
||
switch(count) {
|
||
case 0: return;
|
||
case Numeric::bit_size<IntT>():
|
||
status.set_from<Flag::Carry, Flag::Overflow>(destination & 1);
|
||
destination = 0;
|
||
break;
|
||
default:
|
||
if(count > Numeric::bit_size<IntT>()) {
|
||
status.set_from<Flag::Carry, Flag::Overflow>(0);
|
||
destination = 0;
|
||
} else {
|
||
const auto mask = (Numeric::top_bit<IntT>() >> (count - 1));
|
||
status.set_from<Flag::Carry>(
|
||
destination & mask
|
||
);
|
||
status.set_from<Flag::Overflow>(
|
||
(destination ^ (destination << 1)) & mask
|
||
);
|
||
destination <<= count;
|
||
}
|
||
break;
|
||
}
|
||
status.set_from<IntT, Flag::Sign, Flag::Zero, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename IntT>
|
||
inline void sar(IntT &destination, uint8_t count, Status &status) {
|
||
if(!count) {
|
||
return;
|
||
}
|
||
|
||
const IntT sign = Numeric::top_bit<IntT>() & destination;
|
||
if(count >= Numeric::bit_size<IntT>()) {
|
||
destination = sign ? IntT(~0) : IntT(0);
|
||
status.set_from<Flag::Carry>(sign);
|
||
} else {
|
||
const IntT mask = 1 << (count - 1);
|
||
status.set_from<Flag::Carry>(destination & mask);
|
||
destination = (destination >> count) | (sign ? ~(IntT(~0) >> count) : 0);
|
||
}
|
||
status.set_from<Flag::Overflow>(0);
|
||
status.set_from<IntT, Flag::Sign, Flag::Zero, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename IntT>
|
||
inline void shr(IntT &destination, uint8_t count, Status &status) {
|
||
if(!count) {
|
||
return;
|
||
}
|
||
|
||
status.set_from<Flag::Overflow>(Numeric::top_bit<IntT>() & destination);
|
||
if(count == Numeric::bit_size<IntT>()) {
|
||
status.set_from<Flag::Carry>(Numeric::top_bit<IntT>() & destination);
|
||
destination = 0;
|
||
} else if(count > Numeric::bit_size<IntT>()) {
|
||
status.set_from<Flag::Carry>(0);
|
||
destination = 0;
|
||
} else {
|
||
const IntT mask = 1 << (count - 1);
|
||
status.set_from<Flag::Carry>(destination & mask);
|
||
destination >>= count;
|
||
}
|
||
status.set_from<IntT, Flag::Sign, Flag::Zero, Flag::ParityOdd>(destination);
|
||
}
|
||
|
||
template <typename MemoryT, typename RegistersT>
|
||
void popf(MemoryT &memory, RegistersT ®isters, Status &status) {
|
||
status.set(pop<uint16_t, false>(memory, registers));
|
||
}
|
||
|
||
template <typename MemoryT, typename RegistersT>
|
||
void pushf(MemoryT &memory, RegistersT ®isters, Status &status) {
|
||
uint16_t value = status.get();
|
||
push<uint16_t, false>(value, memory, registers);
|
||
}
|
||
|
||
template <typename AddressT, Repetition repetition>
|
||
bool repetition_over(const AddressT &eCX) {
|
||
return repetition != Repetition::None && !eCX;
|
||
}
|
||
|
||
template <typename AddressT, Repetition repetition, typename FlowControllerT>
|
||
void repeat([[maybe_unused]] Status &status, AddressT &eCX, FlowControllerT &flow_controller) {
|
||
if(
|
||
repetition == Repetition::None || // No repetition => stop.
|
||
!(--eCX) // [e]cx is zero after being decremented => stop.
|
||
) {
|
||
return;
|
||
}
|
||
if constexpr (repetition != Repetition::Rep) {
|
||
// If this is RepE or RepNE, also test the zero flag.
|
||
if((repetition == Repetition::RepNE) == status.flag<Flag::Zero>()) {
|
||
return;
|
||
}
|
||
}
|
||
flow_controller.repeat_last();
|
||
}
|
||
|
||
template <typename IntT, typename AddressT, Repetition repetition, typename InstructionT, typename MemoryT, typename FlowControllerT>
|
||
void cmps(const InstructionT &instruction, AddressT &eCX, AddressT &eSI, AddressT &eDI, MemoryT &memory, Status &status, FlowControllerT &flow_controller) {
|
||
if(repetition_over<AddressT, repetition>(eCX)) {
|
||
return;
|
||
}
|
||
|
||
IntT lhs = memory.template access<IntT, AccessType::Read>(instruction.data_segment(), eSI);
|
||
const IntT rhs = memory.template access<IntT, AccessType::Read>(Source::ES, eDI);
|
||
eSI += status.direction<AddressT>() * sizeof(IntT);
|
||
eDI += status.direction<AddressT>() * sizeof(IntT);
|
||
|
||
Primitive::sub<false, false>(lhs, rhs, status);
|
||
|
||
repeat<AddressT, repetition>(status, eCX, flow_controller);
|
||
}
|
||
|
||
template <typename IntT, typename AddressT, Repetition repetition, typename MemoryT, typename FlowControllerT>
|
||
void scas(AddressT &eCX, AddressT &eDI, IntT &eAX, MemoryT &memory, Status &status, FlowControllerT &flow_controller) {
|
||
if(repetition_over<AddressT, repetition>(eCX)) {
|
||
return;
|
||
}
|
||
|
||
const IntT rhs = memory.template access<IntT, AccessType::Read>(Source::ES, eDI);
|
||
eDI += status.direction<AddressT>() * sizeof(IntT);
|
||
|
||
Primitive::sub<false, false>(eAX, rhs, status);
|
||
|
||
repeat<AddressT, repetition>(status, eCX, flow_controller);
|
||
}
|
||
|
||
template <typename IntT, typename AddressT, Repetition repetition, typename InstructionT, typename MemoryT, typename FlowControllerT>
|
||
void lods(const InstructionT &instruction, AddressT &eCX, AddressT &eSI, IntT &eAX, MemoryT &memory, Status &status, FlowControllerT &flow_controller) {
|
||
if(repetition_over<AddressT, repetition>(eCX)) {
|
||
return;
|
||
}
|
||
|
||
eAX = memory.template access<IntT, AccessType::Read>(instruction.data_segment(), eSI);
|
||
eSI += status.direction<AddressT>() * sizeof(IntT);
|
||
|
||
repeat<AddressT, repetition>(status, eCX, flow_controller);
|
||
}
|
||
|
||
template <typename IntT, typename AddressT, Repetition repetition, typename InstructionT, typename MemoryT, typename FlowControllerT>
|
||
void movs(const InstructionT &instruction, AddressT &eCX, AddressT &eSI, AddressT &eDI, MemoryT &memory, Status &status, FlowControllerT &flow_controller) {
|
||
if(repetition_over<AddressT, repetition>(eCX)) {
|
||
return;
|
||
}
|
||
|
||
memory.template access<IntT, AccessType::Write>(Source::ES, eDI) = memory.template access<IntT, AccessType::Read>(instruction.data_segment(), eSI);
|
||
|
||
eSI += status.direction<AddressT>() * sizeof(IntT);
|
||
eDI += status.direction<AddressT>() * sizeof(IntT);
|
||
|
||
repeat<AddressT, repetition>(status, eCX, flow_controller);
|
||
}
|
||
|
||
template <typename IntT, typename AddressT, Repetition repetition, typename MemoryT, typename FlowControllerT>
|
||
void stos(AddressT &eCX, AddressT &eDI, IntT &eAX, MemoryT &memory, Status &status, FlowControllerT &flow_controller) {
|
||
if(repetition_over<AddressT, repetition>(eCX)) {
|
||
return;
|
||
}
|
||
|
||
memory.template access<IntT, AccessType::Write>(Source::ES, eDI) = eAX;
|
||
eDI += status.direction<AddressT>() * sizeof(IntT);
|
||
|
||
repeat<AddressT, repetition>(status, eCX, flow_controller);
|
||
}
|
||
|
||
template <typename IntT, typename AddressT, Repetition repetition, typename InstructionT, typename MemoryT, typename IOT, typename FlowControllerT>
|
||
void outs(const InstructionT &instruction, AddressT &eCX, uint16_t port, AddressT &eSI, MemoryT &memory, IOT &io, Status &status, FlowControllerT &flow_controller) {
|
||
if(repetition_over<AddressT, repetition>(eCX)) {
|
||
return;
|
||
}
|
||
|
||
io.template out<IntT>(port, memory.template access<IntT, AccessType::Read>(instruction.data_segment(), eSI));
|
||
eSI += status.direction<AddressT>() * sizeof(IntT);
|
||
|
||
repeat<AddressT, repetition>(status, eCX, flow_controller);
|
||
}
|
||
|
||
template <typename IntT, typename AddressT, Repetition repetition, typename MemoryT, typename IOT, typename FlowControllerT>
|
||
void ins(AddressT &eCX, uint16_t port, AddressT &eDI, MemoryT &memory, IOT &io, Status &status, FlowControllerT &flow_controller) {
|
||
if(repetition_over<AddressT, repetition>(eCX)) {
|
||
return;
|
||
}
|
||
|
||
memory.template access<IntT, AccessType::Write>(Source::ES, eDI) = io.template in<IntT>(port);
|
||
eDI += status.direction<AddressT>() * sizeof(IntT);
|
||
|
||
repeat<AddressT, repetition>(status, eCX, flow_controller);
|
||
}
|
||
|
||
template <typename IntT, typename IOT>
|
||
void out(uint16_t port, IntT value, IOT &io) {
|
||
io.template out<IntT>(port, value);
|
||
}
|
||
|
||
template <typename IntT, typename IOT>
|
||
void in(uint16_t port, IntT &value, IOT &io) {
|
||
value = io.template in<IntT>(port);
|
||
}
|
||
|
||
}
|
||
|
||
template <
|
||
Model model,
|
||
DataSize data_size,
|
||
AddressSize address_size,
|
||
typename InstructionT,
|
||
typename FlowControllerT,
|
||
typename RegistersT,
|
||
typename MemoryT,
|
||
typename IOT
|
||
> void perform(
|
||
const InstructionT &instruction,
|
||
Status &status,
|
||
FlowControllerT &flow_controller,
|
||
RegistersT ®isters,
|
||
MemoryT &memory,
|
||
IOT &io
|
||
) {
|
||
using IntT = typename DataSizeType<data_size>::type;
|
||
using AddressT = typename AddressSizeType<address_size>::type;
|
||
|
||
// Establish source() and destination() shorthands to fetch data if necessary.
|
||
//
|
||
// C++17, which this project targets at the time of writing, does not provide templatised lambdas.
|
||
// So the following division is in part a necessity.
|
||
//
|
||
// (though GCC offers C++20 syntax as an extension, and Clang seems to follow along, so maybe I'm overthinking)
|
||
IntT immediate;
|
||
const auto source_r = [&]() -> IntT& {
|
||
return *resolve<model, IntT, AccessType::Read>(
|
||
instruction,
|
||
instruction.source().source(),
|
||
instruction.source(),
|
||
registers,
|
||
memory,
|
||
nullptr,
|
||
&immediate);
|
||
};
|
||
const auto source_rmw = [&]() -> IntT& {
|
||
return *resolve<model, IntT, AccessType::ReadModifyWrite>(
|
||
instruction,
|
||
instruction.source().source(),
|
||
instruction.source(),
|
||
registers,
|
||
memory,
|
||
nullptr,
|
||
&immediate);
|
||
};
|
||
const auto destination_r = [&]() -> IntT& {
|
||
return *resolve<model, IntT, AccessType::Read>(
|
||
instruction,
|
||
instruction.destination().source(),
|
||
instruction.destination(),
|
||
registers,
|
||
memory,
|
||
nullptr,
|
||
&immediate);
|
||
};
|
||
const auto destination_w = [&]() -> IntT& {
|
||
return *resolve<model, IntT, AccessType::Write>(
|
||
instruction,
|
||
instruction.destination().source(),
|
||
instruction.destination(),
|
||
registers,
|
||
memory,
|
||
nullptr,
|
||
&immediate);
|
||
};
|
||
const auto destination_rmw = [&]() -> IntT& {
|
||
return *resolve<model, IntT, AccessType::ReadModifyWrite>(
|
||
instruction,
|
||
instruction.destination().source(),
|
||
instruction.destination(),
|
||
registers,
|
||
memory,
|
||
nullptr,
|
||
&immediate);
|
||
};
|
||
|
||
// Performs a displacement jump only if @c condition is true.
|
||
const auto jcc = [&](bool condition) {
|
||
Primitive::jump(
|
||
condition,
|
||
instruction.displacement(),
|
||
registers,
|
||
flow_controller);
|
||
};
|
||
|
||
const auto shift_count = [&]() -> uint8_t {
|
||
static constexpr uint8_t mask = (model != Model::i8086) ? 0x1f : 0xff;
|
||
switch(instruction.source().source()) {
|
||
case Source::None: return 1;
|
||
case Source::Immediate: return uint8_t(instruction.operand()) & mask;
|
||
default: return registers.cl() & mask;
|
||
}
|
||
};
|
||
|
||
// Some instructions use a pair of registers as an extended accumulator — DX:AX or EDX:EAX.
|
||
// The two following return the high and low parts of that pair; they also work in Byte mode to return AH:AL,
|
||
// i.e. AX split into high and low parts.
|
||
const auto pair_high = [&]() -> IntT& {
|
||
if constexpr (data_size == DataSize::Byte) return registers.ah();
|
||
else if constexpr (data_size == DataSize::Word) return registers.dx();
|
||
else if constexpr (data_size == DataSize::DWord) return registers.edx();
|
||
};
|
||
const auto pair_low = [&]() -> IntT& {
|
||
if constexpr (data_size == DataSize::Byte) return registers.al();
|
||
else if constexpr (data_size == DataSize::Word) return registers.ax();
|
||
else if constexpr (data_size == DataSize::DWord) return registers.eax();
|
||
};
|
||
|
||
// For the string operations, evaluate to either SI and DI or ESI and EDI, depending on the address size.
|
||
const auto eSI = [&]() -> AddressT& {
|
||
if constexpr (std::is_same_v<AddressT, uint16_t>) {
|
||
return registers.si();
|
||
} else {
|
||
return registers.esi();
|
||
}
|
||
};
|
||
const auto eDI = [&]() -> AddressT& {
|
||
if constexpr (std::is_same_v<AddressT, uint16_t>) {
|
||
return registers.di();
|
||
} else {
|
||
return registers.edi();
|
||
}
|
||
};
|
||
|
||
// For counts, provide either eCX or CX depending on address size.
|
||
const auto eCX = [&]() -> AddressT& {
|
||
if constexpr (std::is_same_v<AddressT, uint16_t>) {
|
||
return registers.cx();
|
||
} else {
|
||
return registers.ecx();
|
||
}
|
||
};
|
||
|
||
// Gets the port for an IN or OUT; these are always 16-bit.
|
||
const auto port = [&](Source source) -> uint16_t {
|
||
switch(source) {
|
||
case Source::DirectAddress: return instruction.offset();
|
||
default: return registers.dx();
|
||
}
|
||
};
|
||
|
||
// Guide to the below:
|
||
//
|
||
// * use hard-coded register names where appropriate;
|
||
// * return directly if there is definitely no possible write back to RAM;
|
||
// * otherwise use the source() and destination() lambdas, and break in order to allow a writeback if necessary.
|
||
switch(instruction.operation()) {
|
||
default:
|
||
assert(false);
|
||
|
||
case Operation::AAA: Primitive::aaa(registers.axp(), status); return;
|
||
case Operation::AAD: Primitive::aad(registers.axp(), instruction.operand(), status); return;
|
||
case Operation::AAM: Primitive::aam(registers.axp(), instruction.operand(), status, flow_controller); return;
|
||
case Operation::AAS: Primitive::aas(registers.axp(), status); return;
|
||
case Operation::DAA: Primitive::daa(registers.al(), status); return;
|
||
case Operation::DAS: Primitive::das(registers.al(), status); return;
|
||
|
||
case Operation::CBW: Primitive::cbw(pair_low()); return;
|
||
case Operation::CWD: Primitive::cwd(pair_high(), pair_low()); return;
|
||
|
||
case Operation::ESC:
|
||
case Operation::NOP: return;
|
||
|
||
case Operation::HLT: flow_controller.halt(); return;
|
||
case Operation::WAIT: flow_controller.wait(); return;
|
||
|
||
case Operation::ADC: Primitive::add<true>(destination_rmw(), source_r(), status); break;
|
||
case Operation::ADD: Primitive::add<false>(destination_rmw(), source_r(), status); break;
|
||
case Operation::SBB: Primitive::sub<true, true>(destination_rmw(), source_r(), status); break;
|
||
case Operation::SUB: Primitive::sub<false, true>(destination_rmw(), source_r(), status); break;
|
||
case Operation::CMP: Primitive::sub<false, false>(destination_rmw(), source_r(), status); return;
|
||
case Operation::TEST: Primitive::test(destination_r(), source_r(), status); return;
|
||
|
||
case Operation::MUL: Primitive::mul(pair_high(), pair_low(), source_r(), status); return;
|
||
case Operation::IMUL_1: Primitive::imul(pair_high(), pair_low(), source_r(), status); return;
|
||
case Operation::DIV: Primitive::div(pair_high(), pair_low(), source_r(), flow_controller); return;
|
||
case Operation::IDIV: Primitive::idiv(pair_high(), pair_low(), source_r(), flow_controller); return;
|
||
|
||
case Operation::INC: Primitive::inc(destination_rmw(), status); break;
|
||
case Operation::DEC: Primitive::dec(destination_rmw(), status); break;
|
||
|
||
case Operation::AND: Primitive::and_(destination_rmw(), source_r(), status); break;
|
||
case Operation::OR: Primitive::or_(destination_rmw(), source_r(), status); break;
|
||
case Operation::XOR: Primitive::xor_(destination_rmw(), source_r(), status); break;
|
||
case Operation::NEG: Primitive::neg(source_rmw(), status); break; // TODO: should be a destination.
|
||
case Operation::NOT: Primitive::not_(source_rmw()); break; // TODO: should be a destination.
|
||
|
||
case Operation::CALLrel:
|
||
Primitive::call_relative(instruction.displacement(), registers, flow_controller);
|
||
return;
|
||
case Operation::CALLabs:
|
||
Primitive::call_absolute(destination_r(), flow_controller);
|
||
return;
|
||
case Operation::CALLfar:
|
||
Primitive::call_far<model>(instruction, flow_controller, registers, memory);
|
||
return;
|
||
|
||
case Operation::JMPrel: jcc(true); return;
|
||
case Operation::JMPabs: Primitive::jump_absolute(destination_r(), flow_controller); return;
|
||
case Operation::JMPfar: Primitive::jump_far<model>(instruction, flow_controller, registers, memory); return;
|
||
|
||
case Operation::JCXZ: jcc(!eCX()); return;
|
||
case Operation::LOOP: Primitive::loop(eCX(), instruction.offset(), registers, flow_controller); return;
|
||
case Operation::LOOPE: Primitive::loope(eCX(), instruction.offset(), registers, status, flow_controller); return;
|
||
case Operation::LOOPNE: Primitive::loopne(eCX(), instruction.offset(), registers, status, flow_controller); return;
|
||
|
||
case Operation::IRET: Primitive::iret(registers, flow_controller, memory, status); return;
|
||
case Operation::RETnear: Primitive::ret_near(instruction, registers, flow_controller, memory); return;
|
||
case Operation::RETfar: Primitive::ret_far(instruction, registers, flow_controller, memory); return;
|
||
|
||
case Operation::INT: Primitive::int_(instruction.operand(), flow_controller); return;
|
||
case Operation::INTO: Primitive::into(status, flow_controller); return;
|
||
|
||
case Operation::SAHF: Primitive::sahf(registers.ah(), status); return;
|
||
case Operation::LAHF: Primitive::lahf(registers.ah(), status); return;
|
||
|
||
case Operation::LDS: if constexpr (data_size == DataSize::Word) Primitive::ld<model, Source::DS>(instruction, destination_w(), memory, registers); return;
|
||
case Operation::LES: if constexpr (data_size == DataSize::Word) Primitive::ld<model, Source::ES>(instruction, destination_w(), memory, registers); return;
|
||
|
||
case Operation::LEA: Primitive::lea<model>(instruction, destination_w(), memory, registers); return;
|
||
case Operation::MOV: Primitive::mov(destination_w(), source_r()); break;
|
||
|
||
case Operation::JO: jcc(status.condition<Condition::Overflow>()); return;
|
||
case Operation::JNO: jcc(!status.condition<Condition::Overflow>()); return;
|
||
case Operation::JB: jcc(status.condition<Condition::Below>()); return;
|
||
case Operation::JNB: jcc(!status.condition<Condition::Below>()); return;
|
||
case Operation::JZ: jcc(status.condition<Condition::Zero>()); return;
|
||
case Operation::JNZ: jcc(!status.condition<Condition::Zero>()); return;
|
||
case Operation::JBE: jcc(status.condition<Condition::BelowOrEqual>()); return;
|
||
case Operation::JNBE: jcc(!status.condition<Condition::BelowOrEqual>()); return;
|
||
case Operation::JS: jcc(status.condition<Condition::Sign>()); return;
|
||
case Operation::JNS: jcc(!status.condition<Condition::Sign>()); return;
|
||
case Operation::JP: jcc(!status.condition<Condition::ParityOdd>()); return;
|
||
case Operation::JNP: jcc(status.condition<Condition::ParityOdd>()); return;
|
||
case Operation::JL: jcc(status.condition<Condition::Less>()); return;
|
||
case Operation::JNL: jcc(!status.condition<Condition::Less>()); return;
|
||
case Operation::JLE: jcc(status.condition<Condition::LessOrEqual>()); return;
|
||
case Operation::JNLE: jcc(!status.condition<Condition::LessOrEqual>()); return;
|
||
|
||
case Operation::RCL: Primitive::rcl(destination_rmw(), shift_count(), status); break;
|
||
case Operation::RCR: Primitive::rcr(destination_rmw(), shift_count(), status); break;
|
||
case Operation::ROL: Primitive::rol(destination_rmw(), shift_count(), status); break;
|
||
case Operation::ROR: Primitive::ror(destination_rmw(), shift_count(), status); break;
|
||
case Operation::SAL: Primitive::sal(destination_rmw(), shift_count(), status); break;
|
||
case Operation::SAR: Primitive::sar(destination_rmw(), shift_count(), status); break;
|
||
case Operation::SHR: Primitive::shr(destination_rmw(), shift_count(), status); break;
|
||
|
||
case Operation::CLC: Primitive::clc(status); return;
|
||
case Operation::CLD: Primitive::cld(status); return;
|
||
case Operation::CLI: Primitive::cli(status); return;
|
||
case Operation::STC: Primitive::stc(status); return;
|
||
case Operation::STD: Primitive::std(status); return;
|
||
case Operation::STI: Primitive::sti(status); return;
|
||
case Operation::CMC: Primitive::cmc(status); return;
|
||
|
||
case Operation::XCHG: Primitive::xchg(destination_rmw(), source_rmw()); break;
|
||
|
||
case Operation::SALC: Primitive::salc(registers.al(), status); return;
|
||
case Operation::SETMO:
|
||
if constexpr (model == Model::i8086) {
|
||
Primitive::setmo(destination_w(), status);
|
||
break;
|
||
} else {
|
||
// TODO.
|
||
}
|
||
return;
|
||
case Operation::SETMOC:
|
||
if constexpr (model == Model::i8086) {
|
||
Primitive::setmoc(destination_w(), registers.cl(), status);
|
||
break;
|
||
} else {
|
||
// TODO.
|
||
}
|
||
return;
|
||
|
||
case Operation::OUT: Primitive::out(port(instruction.destination().source()), pair_low(), io); return;
|
||
case Operation::IN: Primitive::in(port(instruction.source().source()), pair_low(), io); return;
|
||
|
||
case Operation::XLAT: Primitive::xlat<AddressT>(instruction, memory, registers); return;
|
||
|
||
case Operation::POP: destination_w() = Primitive::pop<IntT, false>(memory, registers); break;
|
||
case Operation::PUSH: Primitive::push<IntT, false>(source_r(), memory, registers); break;
|
||
case Operation::POPF: Primitive::popf(memory, registers, status); break;
|
||
case Operation::PUSHF: Primitive::pushf(memory, registers, status); break;
|
||
|
||
case Operation::CMPS:
|
||
Primitive::cmps<IntT, AddressT, Repetition::None>(instruction, eCX(), eSI(), eDI(), memory, status, flow_controller);
|
||
break;
|
||
case Operation::CMPS_REPE:
|
||
Primitive::cmps<IntT, AddressT, Repetition::RepE>(instruction, eCX(), eSI(), eDI(), memory, status, flow_controller);
|
||
break;
|
||
case Operation::CMPS_REPNE:
|
||
Primitive::cmps<IntT, AddressT, Repetition::RepNE>(instruction, eCX(), eSI(), eDI(), memory, status, flow_controller);
|
||
break;
|
||
|
||
case Operation::SCAS:
|
||
Primitive::scas<IntT, AddressT, Repetition::None>(eCX(), eDI(), pair_low(), memory, status, flow_controller);
|
||
break;
|
||
case Operation::SCAS_REPE:
|
||
Primitive::scas<IntT, AddressT, Repetition::RepE>(eCX(), eDI(), pair_low(), memory, status, flow_controller);
|
||
break;
|
||
case Operation::SCAS_REPNE:
|
||
Primitive::scas<IntT, AddressT, Repetition::RepNE>(eCX(), eDI(), pair_low(), memory, status, flow_controller);
|
||
break;
|
||
|
||
case Operation::LODS:
|
||
Primitive::lods<IntT, AddressT, Repetition::None>(instruction, eCX(), eSI(), pair_low(), memory, status, flow_controller);
|
||
break;
|
||
case Operation::LODS_REP:
|
||
Primitive::lods<IntT, AddressT, Repetition::Rep>(instruction, eCX(), eSI(), pair_low(), memory, status, flow_controller);
|
||
break;
|
||
|
||
case Operation::MOVS:
|
||
Primitive::movs<IntT, AddressT, Repetition::None>(instruction, eCX(), eSI(), eDI(), memory, status, flow_controller);
|
||
break;
|
||
case Operation::MOVS_REP:
|
||
Primitive::movs<IntT, AddressT, Repetition::Rep>(instruction, eCX(), eSI(), eDI(), memory, status, flow_controller);
|
||
break;
|
||
|
||
case Operation::STOS:
|
||
Primitive::stos<IntT, AddressT, Repetition::None>(eCX(), eDI(), pair_low(), memory, status, flow_controller);
|
||
break;
|
||
case Operation::STOS_REP:
|
||
Primitive::stos<IntT, AddressT, Repetition::Rep>(eCX(), eDI(), pair_low(), memory, status, flow_controller);
|
||
break;
|
||
|
||
case Operation::OUTS:
|
||
Primitive::outs<IntT, AddressT, Repetition::None>(instruction, eCX(), registers.dx(), eSI(), memory, io, status, flow_controller);
|
||
break;
|
||
case Operation::OUTS_REP:
|
||
Primitive::outs<IntT, AddressT, Repetition::Rep>(instruction, eCX(), registers.dx(), eSI(), memory, io, status, flow_controller);
|
||
break;
|
||
|
||
case Operation::INS:
|
||
Primitive::ins<IntT, AddressT, Repetition::None>(eCX(), registers.dx(), eDI(), memory, io, status, flow_controller);
|
||
break;
|
||
case Operation::INS_REP:
|
||
Primitive::ins<IntT, AddressT, Repetition::Rep>(eCX(), registers.dx(), eDI(), memory, io, status, flow_controller);
|
||
break;
|
||
}
|
||
|
||
// Write to memory if required to complete this operation.
|
||
memory.template write_back<IntT>();
|
||
}
|
||
|
||
template <
|
||
Model model,
|
||
typename InstructionT,
|
||
typename FlowControllerT,
|
||
typename RegistersT,
|
||
typename MemoryT,
|
||
typename IOT
|
||
> void perform(
|
||
const InstructionT &instruction,
|
||
Status &status,
|
||
FlowControllerT &flow_controller,
|
||
RegistersT ®isters,
|
||
MemoryT &memory,
|
||
IOT &io
|
||
) {
|
||
auto size = [](DataSize operation_size, AddressSize address_size) constexpr -> int {
|
||
return int(operation_size) + (int(address_size) << 2);
|
||
};
|
||
|
||
// Dispatch to a function specialised on data and address size.
|
||
switch(size(instruction.operation_size(), instruction.address_size())) {
|
||
// 16-bit combinations.
|
||
case size(DataSize::Byte, AddressSize::b16):
|
||
perform<model, DataSize::Byte, AddressSize::b16>(instruction, status, flow_controller, registers, memory, io);
|
||
return;
|
||
case size(DataSize::Word, AddressSize::b16):
|
||
perform<model, DataSize::Word, AddressSize::b16>(instruction, status, flow_controller, registers, memory, io);
|
||
return;
|
||
|
||
// 32-bit combinations.
|
||
//
|
||
// The if constexprs below ensure that `perform` isn't compiled for incompatible data or address size and
|
||
// model combinations. So if a caller nominates a 16-bit model it can supply registers and memory objects
|
||
// that don't implement 32-bit registers or accesses.
|
||
case size(DataSize::Byte, AddressSize::b32):
|
||
if constexpr (is_32bit(model)) {
|
||
perform<model, DataSize::Byte, AddressSize::b32>(instruction, status, flow_controller, registers, memory, io);
|
||
return;
|
||
}
|
||
break;
|
||
case size(DataSize::Word, AddressSize::b32):
|
||
if constexpr (is_32bit(model)) {
|
||
perform<model, DataSize::Word, AddressSize::b32>(instruction, status, flow_controller, registers, memory, io);
|
||
return;
|
||
}
|
||
break;
|
||
case size(DataSize::DWord, AddressSize::b16):
|
||
if constexpr (is_32bit(model)) {
|
||
perform<model, DataSize::DWord, AddressSize::b16>(instruction, status, flow_controller, registers, memory, io);
|
||
return;
|
||
}
|
||
break;
|
||
case size(DataSize::DWord, AddressSize::b32):
|
||
if constexpr (is_32bit(model)) {
|
||
perform<model, DataSize::DWord, AddressSize::b32>(instruction, status, flow_controller, registers, memory, io);
|
||
return;
|
||
}
|
||
break;
|
||
|
||
default: break;
|
||
}
|
||
|
||
// This is reachable only if the data and address size combination in use isn't available
|
||
// on the processor model nominated.
|
||
assert(false);
|
||
}
|
||
|
||
}
|
||
|
||
#endif /* PerformImplementation_h */
|