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125 lines
4.6 KiB
C++
125 lines
4.6 KiB
C++
//
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// PowerPC.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 12/30/20.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#include "PowerPC.hpp"
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using namespace CPU::Decoder::PowerPC;
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Decoder::Decoder(Model model) : model_(model) {}
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Instruction Decoder::decode(uint32_t opcode) {
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// Quick bluffer's guide to PowerPC instruction encoding:
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//
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// There is a six-bit field at the very top of the instruction.
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// Sometimes that fully identifies an instruction, but usually
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// it doesn't.
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//
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// There is an addition 9- or 10-bit field starting one bit above
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// least significant that disambiguates the rest. Strictly speaking
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// it's a 10-bit field, but the mnemonics for many instructions treat
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// it as a 9-bit field with a flag at the top.
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//
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// I've decided to hew directly to the mnemonics.
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#define Bind(mask, operation) case mask: return Instruction(Operation::operation, opcode);
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#define BindConditional(condition, mask, operation) \
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case mask: \
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if(condition()) return Instruction(Operation::operation, opcode); \
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return Instruction(opcode);
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#define Six(x) (unsigned(x) << 26)
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#define SixTen(x, y) (Six(x) | (y << 1))
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// First pass: weed out all those instructions identified entirely by the
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// top six bits.
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switch(opcode & Six(0b111111)) {
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default: break;
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BindConditional(is64bit, Six(0b000010), tdi);
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Bind(Six(0b000011), twi);
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Bind(Six(0b000111), mulli);
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Bind(Six(0b001000), subfic);
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Bind(Six(0b001100), addic); Bind(Six(0b001101), addic_);
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Bind(Six(0b001110), addi); Bind(Six(0b001111), addis);
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Bind(Six(0b010000), bcx);
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Bind(Six(0b010010), bx);
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Bind(Six(0b010100), rlwimix);
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Bind(Six(0b010101), rlwinmx);
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Bind(Six(0b010111), rlwnmx);
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Bind(Six(0b011000), ori); Bind(Six(0b011001), oris);
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Bind(Six(0b011010), xori); Bind(Six(0b011011), xoris);
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Bind(Six(0b011100), andi_); Bind(Six(0b011101), andis_);
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Bind(Six(0b100000), lwz); Bind(Six(0b100001), lwzu);
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Bind(Six(0b100010), lbz); Bind(Six(0b100011), lbzu);
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Bind(Six(0b100100), stw); Bind(Six(0b100101), stwu);
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Bind(Six(0b100110), stb); Bind(Six(0b100111), stbu);
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Bind(Six(0b101000), lhz); Bind(Six(0b101001), lhzu);
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Bind(Six(0b101010), lha); Bind(Six(0b101011), lhau);
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Bind(Six(0b101100), sth); Bind(Six(0b101101), sthu);
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Bind(Six(0b101110), lmw); Bind(Six(0b101111), stmw);
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Bind(Six(0b110000), lfs); Bind(Six(0b110001), lfsu);
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Bind(Six(0b110010), lfd); Bind(Six(0b110011), lfdu);
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Bind(Six(0b110100), stfs); Bind(Six(0b110101), stfsu);
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Bind(Six(0b110110), stfd); Bind(Six(0b110111), stfdu);
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// Assumed below here: reserved bits can be ignored.
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// This might need to be a function of CPU model.
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Bind(Six(0b001010), cmpli); Bind(Six(0b001011), cmpi);
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}
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// Second pass: all those with a top six bits and a bottom nine or ten.
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switch(opcode & SixTen(0b111111, 0b1111111111)) {
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default: break;
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BindConditional(is64bit, SixTen(0b011111, 0b0000001001), mulhdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0000010101), ldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0000011011), sldx);
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Bind(SixTen(0b010011, 0b0000000000), mcrf);
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Bind(SixTen(0b010011, 0b0000010000), bclrx);
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Bind(SixTen(0b010011, 0b0000100001), crnor);
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Bind(SixTen(0b010011, 0b0000110010), rfi);
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Bind(SixTen(0b010011, 0b0010000001), crandc);
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Bind(SixTen(0b010011, 0b0010010110), isync);
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Bind(SixTen(0b010011, 0b0011000001), crxor);
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Bind(SixTen(0b010011, 0b0011100001), crnand);
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Bind(SixTen(0b010011, 0b0100000001), crand);
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Bind(SixTen(0b010011, 0b0100100001), creqv);
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Bind(SixTen(0b010011, 0b0110100001), crorc);
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Bind(SixTen(0b010011, 0b0111000001), cror);
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Bind(SixTen(0b010011, 0b1000010000), bcctrx);
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Bind(SixTen(0b011111, 0b0000000000), cmp);
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Bind(SixTen(0b011111, 0b0000000100), tw);
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Bind(SixTen(0b011111, 0b0000001000), subfcx); Bind(SixTen(0b011111, 0b1000001000), subfcx);
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Bind(SixTen(0b011111, 0b0000001010), addcx); Bind(SixTen(0b011111, 0b1000001010), addcx);
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Bind(SixTen(0b011111, 0b0000001011), mulhwux);
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Bind(SixTen(0b011111, 0b0000010011), mfcr);
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Bind(SixTen(0b011111, 0b0000010100), lwarx);
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Bind(SixTen(0b011111, 0b0000010111), lwzx);
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Bind(SixTen(0b011111, 0b0000011000), slwx);
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Bind(SixTen(0b011111, 0b0000011010), cntlzwx);
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Bind(SixTen(0b011111, 0b0000011100), andx);
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Bind(SixTen(0b011111, 0b0000100000), cmpl);
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Bind(SixTen(0b011111, 0b0000101000), subfx); Bind(SixTen(0b011111, 0b1000101000), subfx);
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}
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// Check for sc.
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if((opcode & 0b010001'00000'00000'00000000000000'1'0) == 0b010001'00000'00000'00000000000000'1'0) {
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return Instruction(Operation::sc, opcode);
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}
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#undef Six
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#undef Bind
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#undef BindConditional
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return Instruction(opcode);
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}
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