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CLK
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CLK
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OSBindings
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Mac
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Clock SignalTests
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Bridges
History
Thomas Harte
05b95ea2e0
Corrects Xcode tests.
2018-01-01 16:04:13 -05:00
..
C1540Bridge.h
Corrects Xcode tests.
2018-01-01 16:04:13 -05:00
C1540Bridge.mm
Corrects Xcode tests.
2018-01-01 16:04:13 -05:00
Clock SignalTests-Bridging-Header.h
Adjusted slightly to adapt to latest Swift warnings.
2017-05-17 07:49:48 -04:00
DigitalPhaseLockedLoopBridge.h
Fixed the
DigitalPhaseLockedLoopBridge
bridge, once again fixing tests.
2017-07-16 20:55:57 -04:00
DigitalPhaseLockedLoopBridge.mm
Converted the DPLL and disk controller classes to be
ClockReceiver
s.
2017-07-24 21:04:47 -04:00
MOS6522Bridge.h
…
MOS6522Bridge.mm
Corrects 6522 bridge per has-a-not-is-a template switch.
2017-09-04 21:56:21 -04:00
MOS6532Bridge.h
…
MOS6532Bridge.mm
The 6532 is now a
ClockReceiver
.
2017-07-24 21:57:24 -04:00
TestMachine6502.h
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
TestMachine6502.mm
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
TestMachine.h
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
TestMachine.mm
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
TestMachine+ForSubclassEyesOnly.h
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
TestMachineZ80.h
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
TestMachineZ80.mm
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00