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286 lines
8.7 KiB
C++
286 lines
8.7 KiB
C++
//
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// AppleIIgs.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 20/10/2020.
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// Copyright 2020 Thomas Harte. All rights reserved.
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//
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#include "AppleIIgs.hpp"
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#include "../../MachineTypes.hpp"
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#include "../../../Processors/65816/65816.hpp"
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#include "../../../Analyser/Static/AppleIIgs/Target.hpp"
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#include "MemoryMap.hpp"
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#include "../../../Components/8530/z8530.hpp"
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#include "../../../Components/AppleClock/AppleClock.hpp"
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#include "../../../Components/DiskII/IWM.hpp"
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#include <cassert>
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#include <array>
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namespace Apple {
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namespace IIgs {
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class ConcreteMachine:
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public Apple::IIgs::Machine,
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public MachineTypes::TimedMachine,
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public MachineTypes::ScanProducer,
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public CPU::MOS6502Esque::BusHandler<uint32_t> {
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public:
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ConcreteMachine(const Analyser::Static::AppleIIgs::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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m65816_(*this) {
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set_clock_rate(14318180.0);
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using Target = Analyser::Static::AppleIIgs::Target;
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std::vector<ROMMachine::ROM> rom_descriptions;
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const std::string machine_name = "AppleIIgs";
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switch(target.model) {
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case Target::Model::ROM00:
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/* TODO */
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case Target::Model::ROM01:
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rom_descriptions.emplace_back(machine_name, "the Apple IIgs ROM01", "apple2gs.rom", 128*1024, 0x42f124b0);
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break;
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case Target::Model::ROM03:
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rom_descriptions.emplace_back(machine_name, "the Apple IIgs ROM03", "apple2gs.rom2", 256*1024, 0xde7ddf29);
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break;
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}
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const auto roms = rom_fetcher(rom_descriptions);
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if(!roms[0]) {
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throw ROMMachine::Error::MissingROMs;
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}
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rom_ = *roms[0];
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size_t ram_size = 0;
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switch(target.memory_model) {
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case Target::MemoryModel::TwoHundredAndFiftySixKB:
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ram_size = 256;
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break;
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case Target::MemoryModel::OneMB:
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ram_size = 128 + 1024;
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break;
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case Target::MemoryModel::EightMB:
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ram_size = 128 + 8 * 1024;
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break;
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}
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ram_.resize(ram_size * 1024);
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memory_.set_storage(ram_, rom_);
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// Sync up initial values.
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memory_.set_speed_register(speed_register_);
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}
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void run_for(const Cycles cycles) override {
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m65816_.run_for(cycles);
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}
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void set_scan_target(Outputs::Display::ScanTarget *) override {
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const override {
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return Outputs::Display::ScanStatus();
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}
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forceinline Cycles perform_bus_operation(const CPU::WDC65816::BusOperation operation, const uint32_t address, uint8_t *const value) {
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const auto ®ion = MemoryMapRegion(memory_, address);
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// TODO: potentially push time to clock_.
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if(region.flags & MemoryMap::Region::IsIO) {
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// Ensure classic auxiliary and language card accesses have effect.
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const bool is_read = isReadOperation(operation);
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memory_.access(uint16_t(address), is_read);
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switch(address & 0xffff) {
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// New video register.
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case 0xc029:
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if(is_read) {
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*value = 0;
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} else {
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printf("New video: %02x\n", *value);
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// TODO: this bit should affect memory bank selection, somehow?
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// Cf. Page 90.
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}
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break;
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// Shadow register.
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case 0xc035:
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if(is_read) {
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*value = memory_.get_shadow_register();
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} else {
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memory_.set_shadow_register(*value);
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}
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break;
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// Clock data.
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case 0xc033:
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if(is_read) {
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*value = clock_.get_data();
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} else {
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clock_.set_data(*value);
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}
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break;
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// Clock and border control.
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case 0xc034:
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if(is_read) {
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*value = clock_.get_control();
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} else {
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clock_.set_control(*value);
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// TODO: also set border colour.
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}
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break;
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// Speed register.
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case 0xc036:
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if(is_read) {
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*value = speed_register_;
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} else {
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memory_.set_speed_register(*value);
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speed_register_ = *value;
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printf("[Unimplemented] most of speed register: %02x\n", *value);
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}
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break;
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// [Memory] State register.
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case 0xc068:
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if(is_read) {
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*value = memory_.get_state_register();
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} else {
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memory_.set_state_register(*value);
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}
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break;
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// Various independent memory switch reads [TODO: does the IIe-style keyboard the low seven?].
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#define SwitchRead(s) *value = memory_.s ? 0x80 : 0x00
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#define LanguageRead(s) SwitchRead(language_card_switches().state().s)
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#define AuxiliaryRead(s) SwitchRead(auxiliary_switches().switches().s)
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case 0xc011: LanguageRead(bank1); break;
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case 0xc012: LanguageRead(read); break;
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case 0xc013: AuxiliaryRead(read_auxiliary_memory); break;
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case 0xc014: AuxiliaryRead(write_auxiliary_memory); break;
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case 0xc015: AuxiliaryRead(internal_CX_rom); break;
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case 0xc016: AuxiliaryRead(alternative_zero_page); break;
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case 0xc017: AuxiliaryRead(slot_C3_rom); break;
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#undef AuxiliaryRead
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#undef LanguageRead
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#undef SwitchRead
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// The SCC.
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case 0xc038: case 0xc039: case 0xc03a: case 0xc03b:
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if(isReadOperation(operation)) {
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*value = scc_.read(int(address));
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} else {
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scc_.write(int(address), *value);
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}
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break;
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// These were all dealt with by the call to memory_.access.
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// TODO: subject to read data? Does vapour lock apply?
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case 0xc000: case 0xc001: case 0xc002: case 0xc003: case 0xc004: case 0xc005:
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case 0xc006: case 0xc007: case 0xc008: case 0xc009: case 0xc00a: case 0xc00b:
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case 0xc054: case 0xc055: case 0xc056: case 0xc057:
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break;
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// Interrupt ROM addresses; Cf. P25 of the Hardware Reference.
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case 0xc071: case 0xc072: case 0xc073: case 0xc074: case 0xc075: case 0xc076: case 0xc077:
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case 0xc078: case 0xc079: case 0xc07a: case 0xc07b: case 0xc07c: case 0xc07d: case 0xc07e: case 0xc07f:
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if(isReadOperation(operation)) {
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*value = rom_[rom_.size() - 65536 + (address & 0xffff)];
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}
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break;
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default:
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if((address & 0xffff) < 0xc100) {
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// TODO: all other IO accesses.
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printf("Unhandled IO: %04x\n", address & 0xffff);
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assert(false);
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} else {
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// Card IO. Not implemented!
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if(isReadOperation(operation)) {
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*value = 0xff;
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}
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}
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}
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} else {
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// For debugging purposes; if execution heads off into an unmapped page then
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// it's pretty certain that my 65816 still has issues.
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assert(operation != CPU::WDC65816::BusOperation::ReadOpcode || region.read);
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if(isReadOperation(operation)) {
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MemoryMapRead(region, address, value);
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} else {
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MemoryMapWrite(memory_, region, address, value);
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}
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}
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printf("%06x %s %02x", address, isReadOperation(operation) ? "->" : "<-", *value);
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if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
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printf(" a:%04x x:%04x y:%04x s:%04x e:%d p:%02x db:%02x pb:%02x d:%04x\n",
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m65816_.get_value_of_register(CPU::WDC65816::Register::A),
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m65816_.get_value_of_register(CPU::WDC65816::Register::X),
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m65816_.get_value_of_register(CPU::WDC65816::Register::Y),
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m65816_.get_value_of_register(CPU::WDC65816::Register::StackPointer),
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m65816_.get_value_of_register(CPU::WDC65816::Register::EmulationFlag),
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m65816_.get_value_of_register(CPU::WDC65816::Register::Flags),
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m65816_.get_value_of_register(CPU::WDC65816::Register::DataBank),
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m65816_.get_value_of_register(CPU::WDC65816::Register::ProgramBank),
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m65816_.get_value_of_register(CPU::WDC65816::Register::Direct)
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);
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} else printf("\n");
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Cycles duration = Cycles(5);
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// TODO: determine the cost of this access.
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// if((mapping.flags & BankMapping::Is1Mhz) || ((mapping.flags & BankMapping::IsShadowed) && !isReadOperation(operation))) {
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// // TODO: (i) get into phase; (ii) allow for the 1Mhz bus length being sporadically 16 rather than 14.
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// duration = Cycles(14);
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// } else {
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// // TODO: (i) get into phase; (ii) allow for collisions with the refresh cycle.
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// duration = Cycles(5);
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// }
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fast_access_phase_ = (fast_access_phase_ + duration.as<int>()) % 5; // TODO: modulo something else, to allow for refresh.
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slow_access_phase_ = (slow_access_phase_ + duration.as<int>()) % 14; // TODO: modulo something else, to allow for stretched cycles.
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return duration;
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}
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private:
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CPU::WDC65816::Processor<ConcreteMachine, false> m65816_;
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MemoryMap memory_;
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Apple::Clock::ParallelClock clock_;
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int fast_access_phase_ = 0;
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int slow_access_phase_ = 0;
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uint8_t speed_register_ = 0x40; // i.e. Power-on status. (TODO: only if ROM03?)
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// MARK: - Memory storage.
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std::vector<uint8_t> ram_;
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std::vector<uint8_t> rom_;
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// MARK: - Other components.
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Zilog::SCC::z8530 scc_;
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};
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}
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}
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using namespace Apple::IIgs;
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Machine *Machine::AppleIIgs(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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return new ConcreteMachine(*dynamic_cast<const Analyser::Static::AppleIIgs::Target *>(target), rom_fetcher);
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}
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Machine::~Machine() {}
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