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381 lines
12 KiB
C++
381 lines
12 KiB
C++
//
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// 65816Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 23/09/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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enum MicroOp: uint8_t {
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/// Fetches a byte from the program counter to the instruction buffer and increments the program counter.
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CycleFetchIncrementPC,
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/// Fetches a byte from the program counter without incrementing it.
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CycleFetchPC,
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/// Fetches a byte from the program counter without incrementing it, and throws it away.
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CycleFetchPCThrowaway,
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/// The same as CycleFetchIncrementPC but indicates valid program address rather than valid data address.
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CycleFetchOpcode,
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/// Fetches a byte from the data address to the data buffer.
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CycleFetchData,
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/// Fetches a byte from the data address to the data buffer and increments the data address.
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CycleFetchIncrementData,
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/// Fetches from the address formed by the low byte of the data address and the high byte
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/// of the instruction buffer, throwing the result away.
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CycleFetchIncorrectDataAddress,
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/// Fetches a byte from the data address and throws it away.
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CycleFetchDataThrowaway,
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/// Fetches a byte from the data address to the data buffer, signalling VPB .
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CycleFetchVector,
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/// Fetches a byte from the data address to the data buffer and increments the data address, signalling VPB.
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CycleFetchIncrementVector,
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// Dedicated block-move cycles; these use the data buffer as an intermediary.
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CycleFetchBlockX,
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CycleFetchBlockY,
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CycleStoreBlockY,
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/// Stores a byte from the data buffer.
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CycleStoreData,
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/// Stores the most recent byte placed into the data buffer without removing it.
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CycleStoreDataThrowaway,
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/// Stores a byte to the data address from the data buffer and increments the data address.
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CycleStoreIncrementData,
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/// Stores a byte to the data address from the data buffer and decrements the data address.
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CycleStoreDecrementData,
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/// Pushes a single byte from the data buffer to the stack.
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CyclePush,
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/// Fetches from the current stack location and throws the result away.
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CycleAccessStack,
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/// Pulls a single byte to the data buffer from the stack.
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CyclePull,
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/// Performs as CyclePull if the 65816 is not in emulation mode; otherwise skips itself.
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CyclePullIfNotEmulation,
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/// Issues a BusOperation::None and regresses the micro-op counter until an established
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/// STP or WAI condition is satisfied.
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CycleRepeatingNone,
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/// Sets the data address by copying the final two bytes of the instruction buffer and
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/// using the data register as a high byte.
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OperationConstructAbsolute,
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/// Constructs a strictly 16-bit address from the instruction buffer.
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OperationConstructAbsolute16,
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/// Sets the data address by copying the entire instruction buffer.
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OperationConstructAbsoluteLong,
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/// Sets the data address to the 16-bit result of adding x to the value in the instruction buffer.
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OperationConstructAbsoluteIndexedIndirect,
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/// Sets the data address to the 24-bit result of adding x to the low 16-bits of the value in the
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/// instruction buffer and retaining the highest 8-bits as specified.
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OperationConstructAbsoluteLongX,
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/// Calculates an a, x address; if:
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/// there was no carry into the top byte of the address; and
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/// the process or in emulation or 8-bit index mode;
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/// then it also skips the next micro-op.
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OperationConstructAbsoluteXRead,
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/// Calculates an a, x address.
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OperationConstructAbsoluteX,
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// These are analogous to the X versions above.
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OperationConstructAbsoluteY,
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OperationConstructAbsoluteYRead,
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/// Constructs the current direct address using the value in the instruction buffer.
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/// Skips the next micro-op if the low byte of the direct register is 0.
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OperationConstructDirect,
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/// Exactly like OperationConstructDirect, but doesn't retain any single-byte wrapping
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/// behaviour in emulation mode.
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OperationConstructDirectLong,
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/// Constructs the current direct indexed indirect address using the data bank,
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/// direct and x registers plus the value currently in the instruction buffer.
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/// Skips the next micro-op if the low byte of the direct register is 0.
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OperationConstructDirectIndexedIndirect,
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/// Constructs the current direct indexed indirect address using the value
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/// currently in the data buffer.
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OperationConstructDirectIndirect,
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/// Adds y to the low 16-bits currently in the instruction buffer and appends a high 8-bits
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/// also from the instruction buffer.
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OperationConstructDirectIndirectIndexedLong,
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/// Uses the 24-bit address currently in the instruction buffer.
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OperationConstructDirectIndirectLong,
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/// Adds the x register to the direct register to produce a 16-bit address;
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/// skips the next micro-op if the low byte of the direct register is 0.
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OperationConstructDirectX,
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/// Adds the y register to the direct register to produce a 16-bit address;
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/// skips the next micro-op if the low byte of the direct register is 0.
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OperationConstructDirectY,
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/// Adds the instruction buffer to the program counter, making a 16-bit result,
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/// *and stores it into the data buffer*.
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OperationConstructPER,
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/// Adds the stack pointer to the instruction buffer to produce a 16-bit address.
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OperationConstructStackRelative,
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/// Adds y to the value in the instruction buffer to produce a 16-bit result and
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/// prefixes the current data bank.
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OperationConstructStackRelativeIndexedIndirect,
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/// Performs whatever operation goes with this program.
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OperationPerform,
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/// Copies the current program counter to the data buffer.
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OperationCopyPCToData,
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OperationCopyDataToPC,
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OperationCopyInstructionToData,
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OperationCopyDataToInstruction,
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/// Copies the current PBR to the data buffer.
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OperationCopyPBRToData,
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/// Copies A to the data buffer.
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OperationCopyAToData,
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/// Copies the data buffer to A.
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OperationCopyDataToA,
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/// Fills the data buffer with three or four bytes, depending on emulation mode, containing the program
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/// counter, flags and possibly the program bank. Also puts the appropriate vector address into the
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/// address register.
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OperationPrepareException,
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/// Sets the memory lock output for the rest of this instruction.
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OperationSetMemoryLock,
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/// Complete this set of micr-ops.
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OperationMoveToNextProgram,
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/// Inspects the instruction buffer and thereby selects the next set of micro-ops to schedule.
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OperationDecode,
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};
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enum Operation: uint8_t {
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// These perform the named operation using the value in the data buffer;
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// they are implicitly AccessType::Read.
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ADC, AND, BIT, CMP, CPX, CPY, EOR, ORA, SBC, BITimm,
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// These load the respective register from the data buffer;
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// they are implicitly AccessType::Read.
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LDA, LDX, LDY,
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PLB, PLD, PLP, // LDA, LDX and LDY can be used for PLA, PLX, PLY.
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// These move the respective register (or value) to the data buffer;
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// they are implicitly AccessType::Write.
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STA, STX, STY, STZ,
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PHB, PHP, PHD, PHK,
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// These modify the value in the data buffer as part of a read-modify-write.
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INC, DEC, ASL, LSR, ROL, ROR, TRB, TSB,
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// These merely decrement A, increment or decrement X and Y, and regress
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// the program counter only if appropriate.
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MVN, MVP,
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// These use a value straight from the instruction buffer.
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REP, SEP,
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BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC, BVS, BRL,
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// These are all implicit.
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CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI,
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TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX,
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XCE, XBA,
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STP, WAI,
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// These unpack values from the data buffer, which has been filled
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// from the stack.
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RTI,
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/// Loads the PC with the contents of the data buffer.
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JMPind,
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/// Loads the PC with the contents of the instruction bufer.
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JMP,
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/// Loads the PC and PBR with the operand from the instruction buffer.
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JML,
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/// Loads the PC with the operand from the instruction buffer, placing
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/// the current PC into the data buffer.
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JSR,
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/// Loads the PC and the PBR with the operand from the instruction buffer,
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/// placing the old PC into the data buffer (and only the PC; PBR not included).
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JSL,
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/// Loads the PC with the contents of the data buffer + 1.
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RTS,
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/// Loads the PC and program bank with the contents of the data buffer + 1.
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RTL,
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};
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struct ProcessorStorageConstructor;
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struct ProcessorStorage {
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ProcessorStorage();
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// Frustratingly, there is not quite enough space in 16 bits to store both
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// the program offset and the operation as currently defined.
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struct Instruction {
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/// Pointers into micro_ops_ for: [0] = 16-bit operation; [1] = 8-bit operation.
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uint16_t program_offsets[2] = {0xffff, 0xffff};
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/// The operation to perform upon an OperationPerform.
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Operation operation = NOP;
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/// An index into the mx field indicating which of M or X affects whether this is an 8-bit or 16-bit field;
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/// if this is 0 then this instruction picks its size based on the M flag; otherwise it does so based on X.
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/// So the program to perform is that at @c program_offsets[mx_flags[size_field]] .
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uint8_t size_field = 0;
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};
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Instruction instructions[256 + 3]; // Arranged as:
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// 256 entries: instructions;
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// the entry for 'exceptions' (i.e. reset, irq, nmi);
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// a duplicate entry for the final part of exceptions if the selected exception is a reset; and
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// the entry for fetch-decode-execute.
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enum class OperationSlot {
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Exception = 256,
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ResetTail,
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FetchDecodeExecute,
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};
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// A helper for testing.
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uint16_t last_operation_pc_;
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Instruction *active_instruction_;
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Cycles cycles_left_to_run_;
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// All registers are boxed up into a struct so that they can be stored and restored in support of abort.
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struct Registers {
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// Registers.
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RegisterPair16 a;
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RegisterPair16 x, y;
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RegisterPair16 s;
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uint16_t pc;
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// Flags aplenty.
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MOS6502Esque::LazyFlags flags;
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uint8_t mx_flags[2] = {1, 1}; // [0] = m; [1] = x. In both cases either `0` or `1`; `1` => 8-bit.
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uint16_t m_masks[2] = {0xff00, 0x00ff}; // [0] = src mask; [1] = dst mask.
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uint16_t x_masks[2] = {0xff00, 0x00ff}; // [0] = src mask; [1] = dst mask.
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uint16_t e_masks[2] = {0xff00, 0x00ff};
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int m_shift = 0;
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int x_shift = 0;
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bool emulation_flag = true;
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// I.e. the offset for direct addressing (outside of emulation mode).
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uint16_t direct = 0;
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// Banking registers are all stored with the relevant byte
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// shifted up bits 16–23.
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uint32_t data_bank = 0; // i.e. DBR.
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uint32_t program_bank = 0; // i.e. PBR.
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} registers_, abort_registers_copy_;
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// The next bus transaction.
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uint32_t bus_address_ = 0;
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uint8_t *bus_value_ = nullptr;
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static inline uint8_t bus_throwaway_ = 0;
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BusOperation bus_operation_ = BusOperation::None;
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// A bitfield for various exceptions.
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static constexpr int PowerOn = 1 << 0;
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static constexpr int Reset = 1 << 1;
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static constexpr int IRQ = Flag::Interrupt; // This makes masking a lot easier later on; this is 1 << 2.
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static constexpr int NMI = 1 << 3;
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static constexpr int Abort = 1 << 4;
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static constexpr int default_exceptions = PowerOn;
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int pending_exceptions_ = default_exceptions;
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int selected_exceptions_ = default_exceptions;
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bool ready_line_ = false;
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bool memory_lock_ = false;
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// Just to be safe.
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static_assert(PowerOn != IRQ);
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static_assert(Reset != IRQ);
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static_assert(NMI != IRQ);
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static_assert(Abort != IRQ);
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/// Sets the required exception flags necessary to exit a STP or WAI.
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int required_exceptions_ = 0;
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BusOperation stp_wai_bus_operation_ = BusOperation::None;
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/// Defines a four-byte buffer which can be cleared or filled in single-byte increments from least significant byte
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/// to most significant.
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struct Buffer {
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uint32_t value = 0;
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int size = 0;
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int read = 0;
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void clear() {
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value = 0;
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size = 0;
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read = 0;
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}
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uint8_t *next_input() {
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uint8_t *const next = byte(size);
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++size;
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return next;
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}
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uint8_t *next_output() {
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uint8_t *const next = byte(read);
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++read;
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return next;
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}
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uint8_t *preview_output() {
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return byte(read);
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}
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uint8_t *next_output_descending() {
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--size;
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return byte(size);
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}
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uint8_t *any_byte() {
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return reinterpret_cast<uint8_t *>(&value);
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}
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private:
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uint8_t *byte(int pointer) {
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assert(pointer >= 0 && pointer < 4);
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#if TARGET_RT_BIG_ENDIAN
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return reinterpret_cast<uint8_t *>(&value) + (3 ^ pointer);
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#else
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return reinterpret_cast<uint8_t *>(&value) + pointer;
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#endif
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}
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};
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Buffer instruction_buffer_, data_buffer_;
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uint32_t data_address_;
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uint32_t data_address_increment_mask_ = 0xffff;
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uint32_t incorrect_data_address_;
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std::vector<MicroOp> micro_ops_;
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MicroOp *next_op_ = nullptr;
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void set_reset_state();
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void set_emulation_mode(bool);
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void set_m_x_flags(bool m, bool x);
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uint8_t get_flags() const;
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void set_flags(uint8_t);
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};
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