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736 lines
23 KiB
C++
736 lines
23 KiB
C++
//
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// AppleIIgs.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 20/10/2020.
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// Copyright 2020 Thomas Harte. All rights reserved.
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//
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#include "AppleIIgs.hpp"
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#include "../../../Activity/Source.hpp"
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#include "../../MachineTypes.hpp"
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#include "../../../Processors/65816/65816.hpp"
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#include "../../../Analyser/Static/AppleIIgs/Target.hpp"
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#include "ADB.hpp"
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#include "MemoryMap.hpp"
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#include "Video.hpp"
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#include "Sound.hpp"
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#include "../../../Components/8530/z8530.hpp"
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#include "../../../Components/AppleClock/AppleClock.hpp"
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#include "../../../Components/AudioToggle/AudioToggle.hpp"
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#include "../../../Components/DiskII/IWM.hpp"
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#include "../../../Components/DiskII/MacintoshDoubleDensityDrive.hpp"
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#include "../../../Outputs/Speaker/Implementation/LowpassSpeaker.hpp"
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#include "../../Utility/MemoryFuzzer.hpp"
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#include "../../../ClockReceiver/JustInTime.hpp"
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#include <cassert>
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#include <array>
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namespace {
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constexpr int CLOCK_RATE = 14318180;
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}
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namespace Apple {
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namespace IIgs {
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class ConcreteMachine:
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public Activity::Source,
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public Apple::IIgs::Machine,
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public MachineTypes::AudioProducer,
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public MachineTypes::MediaTarget,
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public MachineTypes::ScanProducer,
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public MachineTypes::TimedMachine,
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public CPU::MOS6502Esque::BusHandler<uint32_t> {
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public:
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ConcreteMachine(const Analyser::Static::AppleIIgs::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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m65816_(*this),
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iwm_(CLOCK_RATE / 2),
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drives_{
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{CLOCK_RATE / 2, true},
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{CLOCK_RATE / 2, true}
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},
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audio_toggle_(audio_queue_),
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speaker_(audio_toggle_) {
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set_clock_rate(double(CLOCK_RATE));
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speaker_.set_input_rate(float(CLOCK_RATE) / float(audio_divider));
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using Target = Analyser::Static::AppleIIgs::Target;
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std::vector<ROMMachine::ROM> rom_descriptions;
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const std::string machine_name = "AppleIIgs";
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switch(target.model) {
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case Target::Model::ROM00:
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/* TODO */
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case Target::Model::ROM01:
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rom_descriptions.emplace_back(machine_name, "the Apple IIgs ROM01", "apple2gs.rom", 128*1024, 0x42f124b0);
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break;
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case Target::Model::ROM03:
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rom_descriptions.emplace_back(machine_name, "the Apple IIgs ROM03", "apple2gs.rom2", 256*1024, 0xde7ddf29);
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break;
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}
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rom_descriptions.push_back(video_->rom_description(Video::VideoBase::CharacterROM::EnhancedIIe));
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const auto roms = rom_fetcher(rom_descriptions);
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if(!roms[0] || !roms[1]) {
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throw ROMMachine::Error::MissingROMs;
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}
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rom_ = *roms[0];
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video_->set_character_rom(*roms[1]);
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size_t ram_size = 0;
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switch(target.memory_model) {
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case Target::MemoryModel::TwoHundredAndFiftySixKB:
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ram_size = 256;
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break;
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case Target::MemoryModel::OneMB:
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ram_size = 128 + 1024;
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break;
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case Target::MemoryModel::EightMB:
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ram_size = 128 + 8 * 1024;
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break;
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}
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ram_.resize(ram_size * 1024);
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memory_.set_storage(ram_, rom_);
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video_->set_internal_ram(&ram_[ram_.size() - 128*1024]);
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// Select appropriate ADB behaviour.
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adb_glu_.set_is_rom03(target.model == Target::Model::ROM03);
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// Attach drives to the IWM.
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// TODO: presumably attach more, some of which are 5.25"?
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iwm_->set_drive(0, &drives_[0]);
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iwm_->set_drive(1, &drives_[1]);
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// TODO: enable once machine is otherwise sane.
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// Memory::Fuzz(ram_);
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// Sync up initial values.
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memory_.set_speed_register(speed_register_);
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insert_media(target.media);
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}
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~ConcreteMachine() {
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audio_queue_.flush();
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}
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void run_for(const Cycles cycles) override {
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m65816_.run_for(cycles);
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}
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void flush() {
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video_.flush();
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update_audio();
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iwm_.flush();
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audio_queue_.perform();
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}
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void set_scan_target(Outputs::Display::ScanTarget *target) override {
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video_->set_scan_target(target);
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const override {
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return video_->get_scaled_scan_status() * 2.0f; // TODO: expose multiplier and divider via the JustInTime template?
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}
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void set_display_type(Outputs::Display::DisplayType display_type) final {
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video_->set_display_type(display_type);
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}
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Outputs::Display::DisplayType get_display_type() const final {
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return video_->get_display_type();
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}
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Outputs::Speaker::Speaker *get_speaker() final {
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return &speaker_;
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}
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// MARK: MediaTarget.
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bool insert_media(const Analyser::Static::Media &media) final {
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if(!media.disks.empty()) {
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drives_[0].set_disk(media.disks[0]);
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}
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return true;
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}
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// MARK: Activity::Source
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void set_activity_observer(Activity::Observer *observer) final {
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drives_[0].set_activity_observer(observer, "First 3.5\" Drive", true);
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drives_[1].set_activity_observer(observer, "Second 3.5\" Drive", true);
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}
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// MARK: BusHandler.
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forceinline Cycles perform_bus_operation(const CPU::WDC65816::BusOperation operation, const uint32_t address, uint8_t *const value) {
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const auto ®ion = MemoryMapRegion(memory_, address);
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static bool log = false;
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bool is_1Mhz = (region.flags & MemoryMap::Region::Is1Mhz) || !(speed_register_ & 0x80) || (speed_register_ & motor_flags_);
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if(region.flags & MemoryMap::Region::IsIO) {
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// Ensure classic auxiliary and language card accesses have effect.
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const bool is_read = isReadOperation(operation);
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memory_.access(uint16_t(address), is_read);
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// TODO: which of these are actually 2.8Mhz?
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const auto address_suffix = address & 0xffff;
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#define ReadWrite(x) (x) | (is_read * 0x10000)
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#define Read(x) (x) | 0x10000
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#define Write(x) (x)
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switch(ReadWrite(address_suffix)) {
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// New video register.
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case Read(0xc029):
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*value = video_->get_new_video();;
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break;
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case Write(0xc029):
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video_->set_new_video(*value);
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// TODO: I think bits 7 and 0 might also affect the memory map.
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// The descripton isn't especially clear — P.90 of the Hardware Reference.
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// Revisit if necessary.
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break;
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// Video [and clock] interrupt register.
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case Read(0xc023):
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*value = video_->get_interrupt_register();
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break;
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case Write(0xc023):
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video_->set_interrupt_register(*value);
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break;
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// Video interrupt-clear register.
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case Write(0xc032):
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video_->clear_interrupts(*value);
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break;
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// Shadow register.
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case Read(0xc035):
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*value = memory_.get_shadow_register();
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break;
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case Write(0xc035):
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memory_.set_shadow_register(*value);
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break;
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// Clock data.
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case Read(0xc033):
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*value = clock_.get_data();
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break;
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case Write(0xc033):
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clock_.set_data(*value);
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break;
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// Clock and border control.
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case Read(0xc034):
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*value = clock_.get_control();
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break;
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case Write(0xc034):
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clock_.set_control(*value);
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video_->set_border_colour(*value);
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break;
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// Colour text control.
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case Write(0xc022):
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video_->set_text_colour(*value);
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break;
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// Speed register.
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case Read(0xc036):
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*value = speed_register_;
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break;
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case Write(0xc036):
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// b7: 1 => operate at 2.8Mhz; 0 => 1Mhz.
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// b6: power-on status; 1 => system has been turned on by the power switch (TODO: what clears this?)
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// b5: reserved
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// b4: [bank shadowing bit; cf. the memory map]
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// b0–3: motor on-off speed detectors;
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// 1 => switch to 1Mhz if motor is on; 0 => don't;
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// b0 = slot 4 (i.e. watches addresses c0c9, c0c8)
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// b1 = slot 5 (i.e. c0d9, c0d8)
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// b2 = slot 6 (i.e. c0e9, c0e8)
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// b3 = slot 7 (i.e. c0f9, c0f8)
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memory_.set_speed_register(*value);
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speed_register_ = *value;
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break;
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// [Memory] State register.
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case Read(0xc068):
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*value = memory_.get_state_register();
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break;
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case Write(0xc068):
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memory_.set_state_register(*value);
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break;
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// Various independent memory switch reads [TODO: does the IIe-style keyboard provide the low seven?].
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#define SwitchRead(s) *value = memory_.s ? 0x80 : 0x00
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#define LanguageRead(s) SwitchRead(language_card_switches().state().s)
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#define AuxiliaryRead(s) SwitchRead(auxiliary_switches().switches().s)
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#define VideoRead(s) *value = video_->s ? 0x80 : 0x00
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case Read(0xc011): LanguageRead(bank1); break;
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case Read(0xc012): LanguageRead(read); break;
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case Read(0xc013): AuxiliaryRead(read_auxiliary_memory); break;
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case Read(0xc014): AuxiliaryRead(write_auxiliary_memory); break;
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case Read(0xc015): AuxiliaryRead(internal_CX_rom); break;
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case Read(0xc016): AuxiliaryRead(alternative_zero_page); break;
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case Read(0xc017): AuxiliaryRead(slot_C3_rom); break;
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case Read(0xc018): VideoRead(get_80_store()); break;
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case Read(0xc019): VideoRead(get_is_vertical_blank()); break;
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case Read(0xc01a): VideoRead(get_text()); break;
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case Read(0xc01b): VideoRead(get_mixed()); break;
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case Read(0xc01c): VideoRead(get_page2()); break;
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case Read(0xc01d): VideoRead(get_high_resolution()); break;
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case Read(0xc01e): VideoRead(get_alternative_character_set()); break;
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case Read(0xc01f): VideoRead(get_80_columns()); break;
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case Read(0xc046): VideoRead(get_annunciator_3()); break;
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#undef VideoRead
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#undef AuxiliaryRead
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#undef LanguageRead
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#undef SwitchRead
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// Video switches (and annunciators).
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case Read(0xc050): case Read(0xc051):
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case Write(0xc050): case Write(0xc051):
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video_->set_text(address & 1);
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break;
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case Read(0xc052): case Read(0xc053):
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case Write(0xc052): case Write(0xc053):
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video_->set_mixed(address & 1);
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break;
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case Read(0xc054): case Read(0xc055):
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case Write(0xc054): case Write(0xc055):
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video_->set_page2(address&1);
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break;
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case Read(0xc056): case Read(0xc057):
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case Write(0xc056): case Write(0xc057):
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video_->set_high_resolution(address&1);
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break;
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case Read(0xc058): case Read(0xc059):
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case Write(0xc058): case Write(0xc059):
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case Read(0xc05a): case Read(0xc05b):
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case Write(0xc05a): case Write(0xc05b):
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case Read(0xc05c): case Read(0xc05d):
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case Write(0xc05c): case Write(0xc05d):
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// Annunciators 0, 1 and 2.
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break;
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case Read(0xc05e): case Read(0xc05f):
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case Write(0xc05e): case Write(0xc05f):
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video_->set_annunciator_3(!(address&1));
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break;
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case Write(0xc000): case Write(0xc001):
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video_->set_80_store(address & 1);
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break;
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case Write(0xc00c): case Write(0xc00d):
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video_->set_80_columns(address & 1);
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break;
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case Write(0xc00e): case Write(0xc00f):
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video_->set_alternative_character_set(address & 1);
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break;
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// ADB and keyboard.
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case Read(0xc000):
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*value = adb_glu_.get_keyboard_data();
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break;
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case Read(0xc010):
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*value = adb_glu_.get_any_key_down() ? 0x80 : 0x00;
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[[fallthrough]];
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case Write(0xc010):
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adb_glu_.clear_key_strobe();
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break;
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case Read(0xc024):
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*value = adb_glu_.get_mouse_data();
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break;
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case Read(0xc025):
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*value = adb_glu_.get_modifier_status();
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break;
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case Read(0xc026):
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*value = adb_glu_.get_data();
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break;
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case Write(0xc026):
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adb_glu_.set_command(*value);
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break;
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case Read(0xc027):
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*value = adb_glu_.get_status();
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break;
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case Write(0xc027):
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adb_glu_.set_status(*value);
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break;
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// The SCC.
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case Read(0xc038): case Read(0xc039): case Read(0xc03a): case Read(0xc03b):
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*value = scc_.read(int(address));
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break;
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case Write(0xc038): case Write(0xc039): case Write(0xc03a): case Write(0xc03b):
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scc_.write(int(address), *value);
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break;
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// The audio GLU.
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case Read(0xc03c):
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*value = sound_glu_.get_control();
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break;
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case Write(0xc03c):
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sound_glu_.set_control(*value);
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break;
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case Read(0xc03d):
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*value = sound_glu_.get_data();
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break;
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case Write(0xc03d):
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sound_glu_.set_data(*value);
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break;
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case Read(0xc03e):
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*value = sound_glu_.get_address_low();
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break;
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case Write(0xc03e):
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sound_glu_.set_address_low(*value);
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break;
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case Read(0xc03f):
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*value = sound_glu_.get_address_high();
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break;
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case Write(0xc03f):
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sound_glu_.set_address_high(*value);
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break;
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// These were all dealt with by the call to memory_.access.
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// TODO: subject to read data? Does vapour lock apply?
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case 0xc002: case 0xc003: case 0xc004: case 0xc005:
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case 0xc006: case 0xc007: case 0xc008: case 0xc009: case 0xc00a: case 0xc00b:
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break;
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// Interrupt ROM addresses; Cf. P25 of the Hardware Reference.
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case Read(0xc071): case Read(0xc072): case Read(0xc073):
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case Read(0xc074): case Read(0xc075): case Read(0xc076): case Read(0xc077):
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case Read(0xc078): case Read(0xc079): case Read(0xc07a): case Read(0xc07b):
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case Read(0xc07c): case Read(0xc07d): case Read(0xc07e): case Read(0xc07f):
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*value = rom_[rom_.size() - 65536 + address_suffix];
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break;
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// Analogue inputs. All TODO.
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case Read(0xc060): case Read(0xc061): case Read(0xc062): case Read(0xc063):
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// Joystick buttons (and keyboard modifiers).
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*value = 0x00;
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break;
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case Read(0xc064): case Read(0xc065): case Read(0xc066): case Read(0xc067):
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// Analogue inputs.
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*value = 0x00;
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break;
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case Read(0xc070): case Write(0xc070):
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// TODO: begin analogue channel charge.
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break;
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// Monochome/colour register.
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case Read(0xc021):
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// "Uses bit 7 to determine whether composite output is colour 9) or gray scale (1)."
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*value = video_->get_composite_is_colour() ? 0x00 : 0x80;
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break;
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case Write(0xc021):
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video_->set_composite_is_colour(!(*value & 0x80));
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break;
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// Language select. (?)
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case Read(0xc02b):
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*value = language_;
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break;
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case Write(0xc02b):
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language_ = *value;
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break;
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// Slot select.
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case Read(0xc02d):
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// b7: 0 = internal ROM code for slot 7;
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// b6: 0 = internal ROM code for slot 6;
|
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// b5: 0 = internal ROM code for slot 5;
|
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// b4: 0 = internal ROM code for slot 4;
|
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// b3: reserved;
|
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// b2: internal ROM code for slot 2;
|
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// b1: internal ROM code for slot 1;
|
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// b0: reserved.
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*value = card_mask_;
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break;
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case Write(0xc02d):
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card_mask_ = *value;
|
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break;
|
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case Read(0xc030): case Write(0xc030):
|
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update_audio();
|
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audio_toggle_.set_output(!audio_toggle_.get_output());
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break;
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||
|
||
// Addresses that seemingly map to nothing; provided as a separate break out for now,
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// while I have an assert on unknown accesses.
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||
case 0xc049: case 0xc04a: case 0xc04b: case 0xc04c: case 0xc04d: case 0xc04e: case 0xc04f:
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||
case 0xc069: case 0xc06a: case 0xc06b: case 0xc06c:
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printf("Ignoring %04x\n", address_suffix);
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// log = true;
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||
break;
|
||
|
||
// 'Test Mode', whatever that is (?)
|
||
case Read(0xc06e): case Read(0xc06f):
|
||
case Write(0xc06e): case Write(0xc06f):
|
||
test_mode_ = address & 1;
|
||
break;
|
||
case Read(0xc06d):
|
||
*value = test_mode_ * 0x80;
|
||
break;
|
||
|
||
// Disk drive controls additional to the IWM.
|
||
case Read(0xc031):
|
||
*value = disk_select_;
|
||
break;
|
||
case Write(0xc031):
|
||
// b7: 0 = use head 0; 1 = use head 1.
|
||
// b6: 0 = use 5.25" disks; 1 = use 3.5".
|
||
disk_select_ = *value;
|
||
iwm_->set_select(*value & 0x80);
|
||
|
||
// Presumably bit 6 selects between two 5.25" drives rather than the two 3.5"?
|
||
if(*value & 0x40) {
|
||
iwm_->set_drive(0, &drives_[0]);
|
||
iwm_->set_drive(1, &drives_[1]);
|
||
} else {
|
||
// TODO: add 5.25" drives.
|
||
// (and any Smartport devices?)
|
||
iwm_->set_drive(0, nullptr);
|
||
iwm_->set_drive(1, nullptr);
|
||
}
|
||
break;
|
||
|
||
default:
|
||
// Update motor mask bits.
|
||
switch(address_suffix) {
|
||
case 0xc0c8: motor_flags_ &= ~0x01; break;
|
||
case 0xc0c9: motor_flags_ |= 0x01; break;
|
||
case 0xc0d8: motor_flags_ &= ~0x02; break;
|
||
case 0xc0d9: motor_flags_ |= 0x02; break;
|
||
case 0xc0e8: motor_flags_ &= ~0x04; break;
|
||
case 0xc0e9: motor_flags_ |= 0x04; break;
|
||
case 0xc0f8: motor_flags_ &= ~0x08; break;
|
||
case 0xc0f9: motor_flags_ |= 0x08; break;
|
||
}
|
||
|
||
// Check for a card access.
|
||
if(address_suffix >= 0xc080 && address_suffix < 0xc800) {
|
||
// This is an abridged version of the similar code in AppleII.cpp from
|
||
// line 653; it would be good to factor that out and support cards here.
|
||
// For now just either supply the internal ROM or nothing as per the
|
||
// current card mask.
|
||
|
||
size_t card_number = 0;
|
||
if(address >= 0xc100) {
|
||
/*
|
||
Decode the area conventionally used by cards for ROMs:
|
||
0xCn00 to 0xCnff: card n.
|
||
*/
|
||
card_number = (address - 0xc000) >> 8;
|
||
} else {
|
||
/*
|
||
Decode the area conventionally used by cards for registers:
|
||
C0n0 to C0nF: card n - 8.
|
||
*/
|
||
card_number = (address - 0xc080) >> 4;
|
||
}
|
||
|
||
const uint8_t permitted_card_mask_ = card_mask_ & 0xf6;
|
||
if(permitted_card_mask_ & (1 << card_number)) {
|
||
// TODO: Access an actual card.
|
||
if(is_read) {
|
||
*value = 0xff;
|
||
}
|
||
} else {
|
||
switch(address_suffix) {
|
||
default:
|
||
printf("Internal card-area access: %04x\n", address_suffix);
|
||
if(is_read) {
|
||
*value = rom_[rom_.size() - 65536 + address_suffix];
|
||
}
|
||
break;
|
||
|
||
// IWM.
|
||
case 0xc0e0: case 0xc0e1: case 0xc0e2: case 0xc0e3:
|
||
case 0xc0e4: case 0xc0e5: case 0xc0e6: case 0xc0e7:
|
||
case 0xc0e8: case 0xc0e9: case 0xc0ea: case 0xc0eb:
|
||
case 0xc0ec: case 0xc0ed: case 0xc0ee: case 0xc0ef:
|
||
if(is_read) {
|
||
*value = iwm_->read(int(address_suffix));
|
||
} else {
|
||
iwm_->write(int(address_suffix), *value);
|
||
}
|
||
break;
|
||
}
|
||
// log = true;
|
||
}
|
||
#undef ReadWrite
|
||
#undef Read
|
||
#undef Write
|
||
} else {
|
||
if(address_suffix < 0xc080) {
|
||
// TODO: all other IO accesses.
|
||
printf("Unhandled IO %s: %04x\n", is_read ? "read" : "write", address_suffix);
|
||
assert(false);
|
||
}
|
||
}
|
||
}
|
||
} else {
|
||
// For debugging purposes; if execution heads off into an unmapped page then
|
||
// it's pretty certain that my 65816 still has issues.
|
||
assert(operation != CPU::WDC65816::BusOperation::ReadOpcode || region.read);
|
||
|
||
if(isReadOperation(operation)) {
|
||
MemoryMapRead(region, address, value);
|
||
} else {
|
||
// Shadowed writes also occur "at 1Mhz".
|
||
// TODO: this is probably an approximation. I'm assuming that there's the ability asynchronously to post
|
||
// both a 1Mhz cycle and a 2.8Mhz cycle and since the latter always fits into the former, this is sufficiently
|
||
// descriptive. I suspect this isn't true as it wouldn't explain the speed boost that Wolfenstein and others
|
||
// get by adding periodic NOPs within their copy-to-shadow step.
|
||
//
|
||
// Maybe the interaction with 2.8Mhz refresh isn't as straightforward as I think?
|
||
is_1Mhz |= region.flags & MemoryMap::Region::IsShadowed;
|
||
|
||
// Use a very broad test for flushing video: any write to $e0 or $e1, or any write that is shadowed.
|
||
// TODO: at least restrict the e0/e1 test to possible video buffers!
|
||
if((address >= 0xe00000 && address < 0xe1000000) || region.flags & MemoryMap::Region::IsShadowed) {
|
||
video_.flush();
|
||
}
|
||
|
||
MemoryMapWrite(memory_, region, address, value);
|
||
}
|
||
}
|
||
|
||
if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
|
||
assert(address);
|
||
}
|
||
// log |= (address >= 0xff9b00) && (address < 0xff9b32);
|
||
if(log) {
|
||
printf("%06x %s %02x", address, isReadOperation(operation) ? "->" : "<-", *value);
|
||
if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
|
||
printf(" a:%04x x:%04x y:%04x s:%04x e:%d p:%02x db:%02x pb:%02x d:%04x\n",
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::A),
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::X),
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::Y),
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::StackPointer),
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::EmulationFlag),
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::Flags),
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::DataBank),
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::ProgramBank),
|
||
m65816_.get_value_of_register(CPU::WDC65816::Register::Direct
|
||
)
|
||
);
|
||
} else printf("\n");
|
||
}
|
||
|
||
// TODO: fully determine the cost of this access.
|
||
// Below is very vague on real details. Won't do.
|
||
Cycles duration;
|
||
if(is_1Mhz) {
|
||
// TODO: (i) get into phase; (ii) allow for the 1Mhz bus length being sporadically 16 rather than 14.
|
||
duration = Cycles(14);
|
||
} else {
|
||
// TODO: (i) get into phase; (ii) allow for collisions with the refresh cycle.
|
||
duration = Cycles(5);
|
||
}
|
||
fast_access_phase_ = (fast_access_phase_ + duration.as<int>()) % 5; // TODO: modulo something else, to allow for refresh.
|
||
slow_access_phase_ = (slow_access_phase_ + duration.as<int>()) % 14; // TODO: modulo something else, to allow for stretched cycles.
|
||
|
||
|
||
// Propagate time far and wide.
|
||
cycles_since_clock_tick_ += duration;
|
||
auto ticks = cycles_since_clock_tick_.divide(Cycles(CLOCK_RATE)).as_integral();
|
||
while(ticks--) {
|
||
clock_.update();
|
||
video_.last_valid()->notify_clock_tick(); // The video controller marshalls the one-second interrupt.
|
||
update_interrupts();
|
||
}
|
||
|
||
video_ += duration;
|
||
iwm_ += duration;
|
||
cycles_since_audio_update_ += duration;
|
||
|
||
// Ensure no more than a single line is enqueued for just-in-time video purposes.
|
||
// TODO: as implemented, check_flush_threshold doesn't actually work. Can it be made to, or is it a bad idea?
|
||
if(video_.check_flush_threshold<131>()) {
|
||
update_interrupts();
|
||
}
|
||
|
||
return duration;
|
||
}
|
||
|
||
void update_interrupts() {
|
||
// Update the interrupt line. TODO: should include the sound GLU too.
|
||
m65816_.set_irq_line(video_.last_valid()->get_interrupt_register() & 0x80);
|
||
}
|
||
|
||
private:
|
||
CPU::WDC65816::Processor<ConcreteMachine, false> m65816_;
|
||
MemoryMap memory_;
|
||
|
||
// MARK: - Timing.
|
||
|
||
int fast_access_phase_ = 0;
|
||
int slow_access_phase_ = 0;
|
||
|
||
uint8_t speed_register_ = 0x40; // i.e. Power-on status. (TODO: only if ROM03?)
|
||
uint8_t motor_flags_ = 0x00;
|
||
|
||
// MARK: - Memory storage.
|
||
|
||
std::vector<uint8_t> ram_{};
|
||
std::vector<uint8_t> rom_;
|
||
|
||
// MARK: - Other components.
|
||
|
||
Apple::Clock::ParallelClock clock_;
|
||
JustInTimeActor<Apple::IIgs::Video::Video, 1, 2, Cycles> video_; // i.e. run video at twice the 1Mhz clock.
|
||
Apple::IIgs::ADB::GLU adb_glu_;
|
||
Zilog::SCC::z8530 scc_;
|
||
JustInTimeActor<Apple::IWM, 1, 2, Cycles> iwm_;
|
||
Cycles cycles_since_clock_tick_;
|
||
Apple::Macintosh::DoubleDensityDrive drives_[2];
|
||
|
||
// The audio parts.
|
||
Apple::IIgs::Sound::GLU sound_glu_;
|
||
Concurrency::DeferringAsyncTaskQueue audio_queue_;
|
||
Audio::Toggle audio_toggle_;
|
||
Outputs::Speaker::LowpassSpeaker<Audio::Toggle> speaker_;
|
||
Cycles cycles_since_audio_update_;
|
||
static constexpr int audio_divider = 8;
|
||
void update_audio() {
|
||
speaker_.run_for(audio_queue_, cycles_since_audio_update_.divide(Cycles(audio_divider)));
|
||
}
|
||
|
||
// MARK: - Cards.
|
||
|
||
// TODO: most of cards.
|
||
uint8_t card_mask_ = 0x00;
|
||
|
||
bool test_mode_ = false;
|
||
uint8_t language_ = 0;
|
||
uint8_t disk_select_ = 0;
|
||
};
|
||
|
||
}
|
||
}
|
||
|
||
using namespace Apple::IIgs;
|
||
|
||
Machine *Machine::AppleIIgs(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
|
||
return new ConcreteMachine(*dynamic_cast<const Analyser::Static::AppleIIgs::Target *>(target), rom_fetcher);
|
||
}
|
||
|
||
Machine::~Machine() {}
|