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329 lines
10 KiB
C++
329 lines
10 KiB
C++
//
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// 68000Mk2Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef _8000Mk2Implementation_h
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#define _8000Mk2Implementation_h
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#include <cassert>
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#include <cstdio>
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namespace CPU {
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namespace MC68000Mk2 {
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// MARK: - The state machine.
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template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
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void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::run_for(HalfCycles duration) {
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// Accumulate the newly paid-in cycles. If this instance remains in deficit, exit.
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time_remaining_ += duration;
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if(time_remaining_ <= HalfCycles(0)) return;
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// Check whether all remaining time has been expended; if so then exit, having set this line up as
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// the next resumption point.
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#define ConsiderExit() if(time_remaining_ <= HalfCycles(0)) { state_ = __COUNTER__+1; return; } [[fallthrough]]; case __COUNTER__:
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// Subtracts `n` half-cycles from `time_remaining_`; if permit_overrun is false, also ConsiderExit()
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#define Spend(n) time_remaining_ -= (n); if constexpr (!permit_overrun) ConsiderExit()
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// Performs ConsiderExit() only if permit_overrun is true.
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#define CheckOverrun() if constexpr (permit_overrun) ConsiderExit()
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// Sets `x` as the next state, and exits now if all remaining time has been extended and permit_overrun is true.
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#define MoveToState(x) state_ = (x); if (permit_overrun && time_remaining_ <= HalfCycles(0)) return
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//
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// So basic structure is, in general:
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//
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// case Action:
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// do_something();
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// Spend(20);
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// do_something_else();
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// Spend(10);
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// do_a_third_thing();
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// Spend(30);
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//
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// MoveToState(next_action);
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// break;
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//
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// Additional notes:
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//
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// Action and all equivalents should be negative values, since the
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// switch-for-computed-goto-for-a-coroutine structure uses __COUNTER__* for
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// its invented entry- and exit-points, meaning that negative numbers are
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// the easiest group that is safely definitely never going to collide.
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//
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// (* an extension supported by at least GCC, Clang and MSVC)
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// Some microcycles that will be modified as required and used in the loop below;
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// the semantics of a switch statement make in-place declarations awkward.
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Microcycle idle{0};
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// Read a data word.
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Microcycle read_word_data_announce {
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Microcycle::Read | Microcycle::NewAddress | Microcycle::IsData
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};
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Microcycle read_word_data {
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Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsData
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};
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// Read a program word. All accesses via the program counter are word sized.
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Microcycle read_program_announce {
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Microcycle::Read | Microcycle::NewAddress | Microcycle::IsProgram
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};
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Microcycle read_program {
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Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsProgram
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};
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// Holding spot when awaiting DTACK/etc.
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Microcycle awaiting_dtack;
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// Spare containers:
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uint32_t address = 0; // For an address, where it isn't provideable by reference.
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HalfCycles delay; // To receive any additional time added on by calls to perform_bus_operation.
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// Helper macros for common bus transactions:
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// Performs the bus operation and then applies a `Spend` of its length
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// plus any additional length returned by the bus handler.
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#define PerformBusOperation(x) \
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delay = bus_handler_.perform_bus_operation(x, is_supervisor_); \
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Spend(x.length + delay)
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// Performs no bus activity for the specified number of microcycles.
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#define IdleBus(n) \
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idle.length = HalfCycles(n * 4); \
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PerformBusOperation(idle)
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// Spin until DTACK, VPA or BERR is asserted (unless DTACK is implicit),
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// holding the bus cycle provided.
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#define WaitForDTACK(x) \
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if constexpr (!dtack_is_implicit && !dtack_ && !vpa_ && !berr_) { \
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awaiting_dtack = x; \
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awaiting_dtack.length = HalfCycles(2); \
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post_dtack_state_ = __COUNTER__+1; \
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state_ = State::WaitForDTACK; \
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break; \
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} \
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[[fallthrough]]; case __COUNTER__:
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// Performs the bus operation provided, which will be one with a
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// SelectWord or SelectByte operation, stretching it to match the E
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// bus if VPA is currently asserted.
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//
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// TODO: If BERR is asserted, stop here and perform a bus error exception.
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//
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// TODO: If VPA is asserted, stretch this cycle.
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#define CompleteAccess(x) \
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PerformBusOperation(x)
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// Performs the memory access implied by the announce, perform pair,
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// honouring DTACK, BERR and VPA as necessary.
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#define AccessPair(addr, val, announce, perform) \
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perform.address = announce.address = &addr; \
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perform.value = &val; \
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if constexpr (!dtack_is_implicit) { \
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announce.length = HalfCycles(4); \
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} \
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PerformBusOperation(announce); \
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WaitForDTACK(announce); \
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CompleteAccess(perform);
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// Reads the data (i.e. non-program) word from addr into val.
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#define ReadDataWord(addr, val) AccessPair(addr, val, read_word_data_announce, read_word_data)
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// Reads the program (i.e. non-data) word from addr into val.
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#define ReadProgramWord(val) \
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AccessPair(program_counter_.l, val, read_program_announce, read_program); \
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program_counter_.l += 2;
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// Reads one futher word from the program counter and inserts it into
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// the prefetch queue.
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#define Prefetch() \
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prefetch_.high = prefetch_.low; \
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ReadProgramWord(prefetch_.low)
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using Mode = InstructionSet::M68k::AddressingMode;
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// Otherwise continue for all time, until back in debt.
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// Formatting is slightly obtuse here to make this look more like a coroutine.
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while(true) { switch(state_) {
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// Spin in place, one cycle at a time, until one of DTACK,
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// BERR or VPA is asserted.
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case State::WaitForDTACK:
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PerformBusOperation(awaiting_dtack);
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if(dtack_ || berr_ || vpa_) {
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state_ = post_dtack_state_;
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}
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break;
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// Perform the RESET exception, which seeds the stack pointer and program
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// counter, populates the prefetch queue, and then moves to instruction dispatch.
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case State::Reset:
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IdleBus(7); // (n-)*5 nn
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// Establish general reset state.
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status_.is_supervisor = true;
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status_.interrupt_level = 7;
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status_.trace_flag = 0;
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did_update_status();
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address = 0; ReadDataWord(address, registers_[15].high); // nF
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address += 2; ReadDataWord(address, registers_[15].low); // nf
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address += 2; ReadDataWord(address, program_counter_.high); // nV
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address += 2; ReadDataWord(address, program_counter_.low); // nv
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Prefetch(); // np
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IdleBus(1); // n
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Prefetch(); // np
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MoveToState(State::Decode);
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break;
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// Inspect the prefetch queue in order to decode the next instruction,
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// and segue into the fetching of operands.
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case State::Decode:
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opcode_ = prefetch_.high.w;
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instruction_ = decoder_.decode(opcode_);
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instruction_address_ = program_counter_.l - 4;
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// TODO: check for privilege and unrecognised instructions.
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// Obtain operand flags and pick a perform pattern.
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setup_operation();
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// Signal the bus handler if requested.
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if constexpr (signal_will_perform) {
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bus_handler_.will_perform(instruction_address_, opcode_);
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}
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// Ensure the first parameter is next fetched.
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next_operand_ = 0;
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[[fallthrough]];
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// Check the operand flags to determine whether the operand at index
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// operand_ needs to be fetched, and if so then calculate the EA and
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// do so.
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//
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// Per Yacht, all instructions other than MOVE.[b/w/;] will read all
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// relevant operands — even when that's a useless endeavour, such as
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// for CLR or MOVE SR, <ea>.
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//
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// TODO: add MOVE special case, somewhere.
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case State::FetchOperand:
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switch(instruction_.mode(next_operand_)) {
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case Mode::None:
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state_ = perform_state_;
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continue;
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case Mode::AddressRegisterDirect:
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case Mode::DataRegisterDirect:
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operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
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++next_operand_;
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state_ = next_operand_ == 2 ? perform_state_ : State::FetchOperand;
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continue;
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default:
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assert(false);
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}
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break;
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//
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// Various forms of perform.
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//
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case State::Perform_np:
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InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
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instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
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Prefetch(); // np
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next_operand_ = 0;
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MoveToState(operand_flags_ & 0x0c ? State::StoreOperand : State::Decode);
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break;
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case State::Perform_np_n:
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InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
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instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
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Prefetch(); // np
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IdleBus(1); // n
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next_operand_ = 0;
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MoveToState(operand_flags_ & 0x0c ? State::StoreOperand : State::Decode);
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break;
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default:
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printf("Unhandled state: %d\n", state_);
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assert(false);
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}}
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#undef Prefetch
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#undef ReadProgramWord
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#undef ReadDataWord
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#undef AccessPair
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#undef CompleteAccess
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#undef WaitForDTACK
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#undef IdleBus
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#undef PerformBusOperation
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#undef MoveToState
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#undef CheckOverrun
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#undef Spend
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#undef ConsiderExit
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}
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// MARK: - Operation specifications.
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template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
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void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::setup_operation() {
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#define BIND(x, p) \
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case InstructionSet::M68k::Operation::x: \
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operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>(); \
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perform_state_ = p; \
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break;
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using Mode = InstructionSet::M68k::AddressingMode;
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switch(instruction_.operation) {
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BIND(NBCD, instruction_.mode(0) == Mode::DataRegisterDirect ? State::Perform_np_n : State::Perform_np);
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default:
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assert(false);
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}
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#undef BIND
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}
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// MARK: - Flow Controller.
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void ProcessorBase::did_update_status() {
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// Shuffle the stack pointers.
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stack_pointers_[is_supervisor_] = registers_[7];
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registers_[7] = stack_pointers_[int(status_.is_supervisor)];
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is_supervisor_ = int(status_.is_supervisor);
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}
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// MARK: - External state.
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template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
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CPU::MC68000Mk2::State Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::get_state() {
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return CPU::MC68000Mk2::State();
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}
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template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
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void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::set_state(const CPU::MC68000Mk2::State &) {
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}
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}
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}
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#endif /* _8000Mk2Implementation_h */
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