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139 lines
3.3 KiB
Plaintext
139 lines
3.3 KiB
Plaintext
//
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// 65816ComparativeTests.m
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// Clock SignalTests
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//
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// Created by Thomas Harte on 18/06/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#include "65816.hpp"
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#import <XCTest/XCTest.h>
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#include <array>
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#include <vector>
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#include <unordered_map>
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namespace {
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struct StopException {};
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struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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// Use a map to store RAM contents, in order to preserve initialised state.
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std::unordered_map<uint32_t, uint8_t> ram;
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std::unordered_map<uint32_t, uint8_t> inventions;
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Cycles perform_bus_operation(CPU::MOS6502Esque::BusOperation operation, uint32_t address, uint8_t *value) {
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// Record the basics of the operation.
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auto &cycle = cycles.emplace_back();
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cycle.address = address;
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cycle.operation = operation;
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cycle.value = 0xff;
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// Perform the operation, and fill in the cycle's value.
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using BusOperation = CPU::MOS6502Esque::BusOperation;
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auto ram_value = ram.find(address);
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switch(operation) {
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case BusOperation::ReadOpcode:
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--opcodes_remaining;
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if(!opcodes_remaining) {
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cycles.pop_back();
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throw StopException();
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}
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case BusOperation::Read:
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case BusOperation::ReadProgram:
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case BusOperation::ReadVector:
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if(ram_value != ram.end()) {
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cycle.value = *value = ram_value->second;
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} else {
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cycle.value = *value = uint8_t(rand() >> 8);
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inventions[address] = ram[address] = cycle.value;
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}
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break;
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case BusOperation::Write:
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cycle.value = ram[address] = *value;
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break;
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default: break;
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}
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// Don't occupy any bonus time.
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return Cycles(1);
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}
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template <typename Processor> void setup(Processor &processor, uint8_t opcode) {
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ram.clear();
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inventions.clear();
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cycles.clear();
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using Register = CPU::MOS6502Esque::Register;
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const uint32_t pc =
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processor.get_value_of_register(Register::ProgramCounter) |
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(processor.get_value_of_register(Register::ProgramBank) << 8);
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inventions[pc] = ram[pc] = opcode;
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}
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int opcodes_remaining = 0;
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struct Cycle {
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CPU::MOS6502Esque::BusOperation operation;
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uint32_t address;
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uint8_t value;
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};
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std::vector<Cycle> cycles;
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};
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}
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// MARK: - New test generator.
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@interface TestGenerator : NSObject
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@end
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@implementation TestGenerator
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- (void)generate {
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BusHandler handler;
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CPU::WDC65816::Processor<BusHandler, false> processor(handler);
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// Never run the official reset procedure.
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processor.set_power_on(false);
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for(int operation = 0; operation < 512; operation++) {
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const bool is_emulated = operation & 256;
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const uint8_t opcode = operation & 255;
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// Ensure processor's next action is an opcode fetch.
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processor.restart_operation_fetch();
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// Randomise processor state.
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using Register = CPU::MOS6502Esque::Register;
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processor.set_value_of_register(Register::EmulationFlag, is_emulated);
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// Establish the opcode.
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handler.setup(processor, opcode);
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// Run to the second opcode fetch.
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handler.opcodes_remaining = 2;
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try {
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processor.run_for(Cycles(100));
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} catch (const StopException &) {}
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}
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}
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@end
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// MARK: - Existing test evaluator.
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@interface WDC65816ComparativeTests : XCTestCase
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@end
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@implementation WDC65816ComparativeTests
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// A generator for tests; not intended to be a permanent fixture.
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- (void)testGenerate {
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[[[TestGenerator alloc] init] generate];
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}
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@end
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