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129 lines
3.7 KiB
Plaintext
129 lines
3.7 KiB
Plaintext
//
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// IIgsMemoryMapTests.mm
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// Clock SignalTests
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//
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// Created by Thomas Harte on 25/10/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include "../../../Machines/Apple/AppleIIgs/MemoryMap.hpp"
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namespace {
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using MemoryMap = Apple::IIgs::MemoryMap;
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}
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@interface IIgsMemoryMapTests : XCTestCase
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@end
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@implementation IIgsMemoryMapTests {
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MemoryMap _memoryMap;
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std::vector<uint8_t> _ram;
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std::vector<uint8_t> _rom;
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}
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- (void)setUp {
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_ram.resize((128 + 8 * 1024) * 1024);
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_rom.resize(256 * 1024);
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_memoryMap.set_storage(_ram, _rom);
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// If this isn't the first test run, RAM and ROM may have old values.
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// Initialise to a known state.
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memset(_ram.data(), 0, _ram.size());
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memset(_rom.data(), 0, _rom.size());
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}
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- (void)write:(uint8_t)value address:(uint32_t)address {
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const auto ®ion = MemoryMapRegion(_memoryMap, address);
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XCTAssertFalse(region.flags & MemoryMap::Region::IsIO);
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MemoryMapWrite(_memoryMap, region, address, &value);
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}
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- (uint8_t)readAddress:(uint32_t)address {
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const auto ®ion = MemoryMapRegion(_memoryMap, address);
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uint8_t value;
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MemoryMapRead(region, address, &value);
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return value;
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}
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- (void)testAllRAM {
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// Disable IO/LC 'shadowing', to give linear memory up to bank $80.
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_memoryMap.set_shadow_register(0x5f);
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// Fill memory via the map.
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for(int address = 0x00'0000; address < 0x80'0000; ++address) {
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const uint8_t value = uint8_t(address ^ (address >> 8) ^ (address >> 16));
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[self write:value address:address];
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}
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// Test by direct access.
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for(int address = 0x00'0000; address < 0x80'0000; ++address) {
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const uint8_t value = uint8_t(address ^ (address >> 8) ^ (address >> 16));
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XCTAssertEqual([self readAddress:address], value);
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}
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}
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- (void)testROMIsReadonly {
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_rom[0] = 0xc0;
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// Test that ROM can be read in the correct location.
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XCTAssertEqual([self readAddress:0xfc'0000], 0xc0);
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// Try writing to it, and check that nothing happened.
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[self write:0xfc address:0xfc'0000];
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XCTAssertEqual(_rom[0], 0xc0);
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}
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/// Tests that the same portion of ROM is visible in banks $00, $01, $e0 and $e1.
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- (void)testROMVisibility {
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_rom.back() = 0xa8;
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auto test_bank = [self](uint32_t bank) {
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const uint32_t address = bank | 0xffff;
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XCTAssertEqual([self readAddress:address], 0xa8);
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};
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test_bank(0x00'0000);
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test_bank(0x01'0000);
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test_bank(0xe0'0000);
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test_bank(0xe1'0000);
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}
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/// Tests that writes to $00:$0400 and to $01:$0400 are subsequently visible at $e0:$0400 and $e1:$0400.
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- (void)testShadowing {
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[self write:0xab address:0x00'0400];
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[self write:0xcd address:0x01'0400];
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XCTAssertEqual([self readAddress:0xe0'0400], 0xab);
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XCTAssertEqual([self readAddress:0xe1'0400], 0xcd);
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}
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/// Tests that a write to bank $00 which via the auxiliary switches is redirected to bank $01 is then
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/// mirrored to $e1.
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- (void)testAuxiliaryShadowing {
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// Select the alternate text page 1.
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_memoryMap.access(0xc001, false); // Set 80STORE.
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_memoryMap.access(0xc055, false); // Set PAGE2.
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// These two things together should enable auxiliary memory for text page 1.
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// No, really.
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// Enable shadowing of text page 1.
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_memoryMap.set_shadow_register(0x00);
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// Establish a different value in bank $e1, then write
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// to bank $00 and check banks $01 and $e1.
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[self write: 0xcb address:0xe1'0400];
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[self write: 0xde address:0x00'0400];
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XCTAssertEqual([self readAddress:0xe1'0400], 0xde);
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XCTAssertEqual([self readAddress:0x01'0400], 0xde);
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// Reset the $e1 page version and check all three detinations.
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[self write: 0xcb address:0xe1'0400];
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XCTAssertEqual([self readAddress:0xe1'0400], 0xcb);
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XCTAssertEqual([self readAddress:0x00'0400], 0xde);
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XCTAssertEqual([self readAddress:0x01'0400], 0xde);
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}
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@end
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