Table of Contents
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Relative to the internal counters:
- NTSC: 262 lines, or 262/263 in interlaced mode; lines are alternately 227 and 228 slots long;
- PAL: 312 lines, or 312/313 in interlaced mode; lines are 227 slots long.
Each 'slot' being two processor clock ticks, or one NTSC-rate colour cycle — i.e. one chip RAM access window.
Fixed slot per-line cycle access breakdown:
- 0–3: refresh;
- 4–6: disk;
- 7–10: audio;
- 11–: sprite DMA, two slots per sprite, running for at most 16 slots.
Bitmap data fetch start time is programmable but may not begin earlier than slot 24. It may displace some sprite fetches, and in high-resolution mode will also utilise some of the slots otherwise reserved for the CPU.
"$05 here is the stop position after horizontal blanking on OCS that results in the MOVE, executed 8 pixels later, modifying the background color visibly on the start of that line."
DMA Priority
- Bitplane fetching (or disk/sprite/refresh, per region within a line)
- Copper
- Blitter
- CPU
The Blitter will yield every fourth slot if BLTPRI in DMACON is clear.
The Copper will use odd-numbered slots only; those are the same slots otherwise available to the CPU during bitplane fetching in low-res when using four or fewer bitplanes.
Bitplane Fetches
Requesting seven bitplanes results in fetching as though you'd requested four, followed by output as if you'd requested six. So bit planes 5 and 6 will endlessly repeat whatever value is in their data register.
Low-resolution
An eight-slot fetch pattern is followed:
- [unused]
- bit plane 4
- bit plane 6
- bit plane 2
- [unused]
- bit plane 3
- bit plane 5
- bit plane 1
High-resolution
Four-slot fetch pattern:
- bit plane 4
- bit plane 2
- bit plane 3
- bit plane 1