This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.
This is transcribed from a PDF with the file name as per the title. All text not in italics is present on the original document.
THIS IS OLD INFORMATION BUT MAY BE OF USE.
Introduction
The VDC (ELITE) chip is designed as the video display generator in a paged memory Z80 personal computer. The full addressing range of the computer is 4 megabytes and the top 64K is allocated to the video display (although in a minimal system it may also be used for programs and variables).
A typical system is as follows:
A0–A13 ┌─────────────┐ D0–D7
┌─────────────<───────┤ Z80 ├──────<─>─────────────┐
│ A14', A15' │ │ │
│ ┌─────<──────┤ │ │
│ │ └─────────────┘ │
│ │ │
│ │ ┌───────────────┐ D0–D7 │
│ └───────>───┤ Memory paging ├──<──────────────────┤
│ A0–A1 │ (4 8─bit reg) │ │
├────────────────>───┤ │ │
│ A14–A21 │ │ │
├────────────────<───┤ │ │
│ └───────────────┘ │
│ │
│ ┌───────────────┐ │
│ A0–A15 │ ROM │ D0–D7 │
├────────────────>───┤ ├──────>──────────────┤
│ └───────────────┘ │
│ │
│ │
│ ┌───────────────┐ │
│ A0–A7 │ Sound & IO │ D0–D7 │
├────────────────>───┤ ├────<─>──────────────┤
│ └───────────────┘ │
│ │
│ A0–A21 ┌───────────────┐ D0–D7 │
├──────────────<─>───┤ Expansion Bus ├────<─>──────────────┤
│ └───────────────┘ │
│ │
│ A0–A15 │
┌─┴───────┐ ┌──────┴─┐
│ Buffers │ │ Buffer │
└─┬───────┘ └──────┬─┘
│ UA0–UA15 UD0–UD7 │
│ │
│ ┌─────┐ ┌───────────────┐ │
├─────────┤ Mux ├────┤ Video DRAM ├───<─>───────────────┤
│ └─────┘ └───────────────┘ │
│ │
│ UA0–UA15 ┌───────────────┐ UD0–UD7 │
└──────────────<─>───┤ VDC ├────<─>──────────────┘
│ │
External video ────>──┤ ├───────>──────── 8─bit colour
└───────────────┘
The VDC generates a complex video display from information placed in the Video DRAM by the processor. The Z80 must load a 16-bit pointer to "line parameters" in the VDC.
Whenever the Z80 needs to access the video RAM or the VDC its clock is stretched until a "slot" is available. Note that the video display and the Z80 normally run asynchronously.
Video dynamic RAM is automatically refreshed.
In contrast to the majority of video display devices which allow the user various modes for the whole display the VDC allows many different modes in the same display frame:
- Mixed mode displays
- User definable characters from fonts of 64, 128, and 256
- 8-bit colour output (256 colours)
- 2, 4, 16, and 256 colours per line chosen from 256
- Maximum resolution (using interlace) 672 * 512
- Cell based graphics, bitmaps and characters
- Characters any height from 1 to 256 scanlines
- Choice of 256 border colours
- User defined screen width and height
- External colour input (unlimited sprites or TV camera)
- Efficient use of RAM (can work with < 1K of RAM)
- 4 colour 84 column text mode (uses pixel mode)
- Special uses of bits to increase colour options
- Phaselocked PAL
Block Diagram
-
66 of 68 pins are used leaving 2 for TEST
-
this diagram is intended as a guide to chip layout
-
this pinout (or similar) seems to make internal routing easier
-
presumably it is best to put GND and VCC on opposite sides
-
refer to DPCH/VDC/4 for details
P P P P P P P P V T E E E E E G V T C C C C C C C C C E X C C C C N C E 0 1 2 3 4 5 6 7 1 S T 0 1 2 3 D C S T C T │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌──────┼──┼──┼──┼──┼──┼──┼──┼──┴──┴──┴──┴──┴──┴──┴──┴──┴──┴──────┐ │ └──┴──┴──┴──┴──┴──┴──┘ │ │ │ UA0 ──┼─┐ ┌───────────────────┐ ┌───────────────┐ ┌──────────┐ ├── 4.433M UA1 ──┼─┤ │ │ │ Shift regs │ │ Priority │ ├── 7805 UA2 ──┼─┤ │ Palette registers │ │ & colour mode │ │ │ ├── /BLNK UA3 ──┼─┤ └───────────────────┘ └───────────────┘ └──────────┘ ├── H/2 UA4 ──┼─┤ ────────────────────────┬───────────────────────────── ├── /BURST UA5 ──┼─┤ ┌──────────────────┐ │ ┌───────────────────────┐ ├── /HSYNC UA6 ──┼─┼──│ Char address gen │ │ │ Line data #1 & #2 etc │ ├── /VSYNC UA7 ──┼─┤ ├──────────────────┤ │ ├───────────────────────┴──┐ ├── /VIRQ UA8 ──┼─┼──│ Line data ptr #2 │ │ │ Column counter & margins │ ├── /WR UA9 ──┼─┤ ├──────────────────┤ │ └──────────────────────────┘ ├── /VW UA10 ─┼─┼──│ Line data ptr #1 │ │ ┌──────────────────────┐ ├── /VCAS UA11 ─┼─┤ ├──────────────────┤ │ │ 14m Ring & pixel CLK │ ├── /VRAS UA12 ─┼─┼──│ Refresh addr gen │ │ └──────────────────────┘ ├── /VMUX UA13 ─┼─┤ ├──────────────────┤ │ ┌───────────────────┐ ├── 14M UA14 ─┼─┼──│ Line farm ptr │ │ │ Z80 clock stretch │ ├── /VRAM UA15 ─┼─┘ └──────────────────┘ │ └───────────────────┘ │ │ ┌──┬──┬──┬──┬──┬──┬──┬┘ │ │ │ │ │ │ │ │ │ │ │ └──────┼──┼──┼──┼──┼──┼──┼──┼──┬──┬──┬──┬──┬──┬──┬──┬──┬──┬──────┘ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ U U U U U U U U / 8 D / / / / / P / D D D D D D D D R M 8 M M R I P H A 0 1 2 3 4 5 6 7 E M 1 R F O H I C S E S R I C E Q H Q T
In the above diagram the internal bus (A-BUS), internal data bus (D-BUS) and physical colour bus (PC-BUS) are shown.
Pinout
┌──────────┴──────────┐
──>──┤ 14M VCC PHI ├──>──
──>──┤ D8M /PHI ├──>──
──>──┤ 8M /VRAS ├──>──
──>──┤ /RESET /VMUX ├──>──
──>──┤ /VRAM /VCAS ├──>──
──>──┤ /VID /VW ├──>──
──>──┤ /RFSH /ACCESS ├──>──
──>──┤ /M1 │
──>──┤ /MREQ │
──>──┤ /IOREQ │
──>──┤ /WR /VIRQ ├──>──
│ │
─<─>─┤ UA0 UA8 ├──>──
─<─>─┤ UA1 UA9 ├──>──
─<─>─┤ UA2 UA10 ├──>──
─<─>─┤ UA3 UA11 ├──>──
─<─>─┤ UA4 UA12 ├──>──
─<─>─┤ UA5 UA13 ├──>──
─<─>─┤ UA6 UA14 ├──>──
─<─>─┤ UA7 UA15 ├──>──
│ │
─<─>─┤ UD0 PC0 ├──>──
─<─>─┤ UD1 PC1 ├──>──
─<─>─┤ UD2 PC2 ├──>──
─<─>─┤ UD3 PC3 ├──>──
─<─>─┤ UD4 PC4 ├──>──
─<─>─┤ UD5 PC5 ├──>──
─<─>─┤ UD6 PC6 ├──>──
─<─>─┤ UD7 PC7 ├──>──
│ │
──>──┤ /EXTC VC1 ├──>──
──>──┤ EC0 /BLNK ├──>──
──>──┤ EC1 H/2 ├──>──
──>──┤ EC2 /BURST ├──>──
──>──┤ ED3 /HSYNC ├──>──
│ /VSYNC ├──>──
──>──┤ 4.433M 7805Hz ├──>──
│ GND │
└──────────┬──────────┘
- 2 pins spare for TEST
- 7805Hz might be released if more test pins are required
Signal Description
| 14M | Input. 14.3Mhz master video clock. |
| 8M | Input. 8Mhz (or 12Mhz) master processor clock. |
| D8M | Input. Delayed 8Mhz (or 12Mhz). |
| /RESET | Input. Reset input from sound chip (phased to /M1). |
| /VRAM | Input. Active low if Z80 requesting access to video RAM. |
| /VIO | Input. Active low if Z80 requesting to write to VDC registers (Address 0H80–0H8F gated with /IORQ). |
| /RFSH | Input. Active low if Z80 refreshing memory. |
| /M1 | Input. Active low if Z80 opcode fetch. |
| /MREQ | Input. Active low if Z80 accessing memory. |
| /IORQ | Input. Active low if Z80 accessing IO. |
| /WR | Input. Active low if Z80 writing to RAM or IO. |
| /VRAS | LSTTL output. Active low RAS strobe to video memory. |
| /VMUX | LSTTL output. MUX strobe to video RAM multiplexers. |
| /VCAS | LSTTL output. Active low CAS strobe to video memory. |
| /VW | LSTTL output. Active low write strobe of video memory. |
| /VACCESS | LSTTL output. Active low if Z80 accessing video RAM or video registers. Used to control external buffers. |
| PHI | FAST LSTTL output. Z80 clock. |
| /PHI | FAST LSTTL output. Inverted Z80 clock. |
| /VIRQ | LSTTL output. Active low if video interrupt requested. |
| UA0–UA7 | LSTTL drive tri-state input/output. Low address bus. (8 lines) |
| UA8–UA15 | LSTTL drive tri-state output. High address bus. (8 lines) |
| UD0–UD7 | LSTTL drive tri-state input/output. Data bus. (8 lines) |
| /EXTC | Input. Active low to request external colour input. |
| EC0–EC3 | Input. Active high. External colour input. (4 lines) |
| PC0–PC7 | LSTTL output. 8-bit colour output. (8 lines) |
| /HSYNC | LSTTL output. Active low horizontal sync. |
| /VSYNC | LSTTL output. Active low vertical sync. |
| /BURST | LSTTL output. Active low colour burst strobe. |
| /VC1 | LSTTL output. General purpose output. (Used for colour kill.) |
| /BLNK | LSTTL output. Active low for video blanking. |
| H/2 | LSTTL output. Used by PAL modulator. |
| VCC | Power input at 5V. |
| GND | Ground connection. |
| 4.433M | LSTTL output. Divided by 4722 to give 7805Hz. |
| 7805 | LSTTL output. ??? |
External Timing
Timings related to 14M clock.
─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
14M └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─
┌─────────────────────────────────────────────────────────────
/RESET ─┘
T states from reset (mod 16)
─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Ideal dynamic RAM timing signals with no Z80 access.
UA0–UA15 XXXX<-- stable -->XXXX<-- stable -->XXXXXXXXXXXXXXXXXXXXXXXX
UD0–UD7 XXXXXXXXXXXXXXXXXX<IN>XXXXXXXXXXXXXXXX<IN>XXXXXXXXXXXXXXXXXXXXXX
───────┐ ┌───────┐ ┌─────────────────────
/VRAS └───────────┘ └───────────┘
─────────┐ ┌───────┐ ┌───────────────────
/VMUX └───────────┘ └───────────┘
───────────┐ ┌───────────┐ ┌─────────────────────
/VCAS └───────┘ └───────┘
─────────────────────────────────────────────────────────────
/ACCESS
─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Transcriber's note: my reading of the above is that it is intended to show:
- /VRAS going active on the leading edges of cycles 2 and 7, inactive on the leading edges of cycles 5 and 10;
- /VMUX going active and inactive half a cycle after /VRAS;
- /VCAS going active a cycle laster than /VRAS but inactive simultaneously with it;
- UAx being stable from the leading edge of cycle 1 until the leading edge of cycle 5, and again from the leading edge of cycle 6 until the leading edge of cycle 10;
- UDx being sampled around the leading edge of cycle 5 and the leading edge of cycle 10; and
- /ACCESS is inactive for the entire period.
Ideal dynamic RAM timing signals with Z80 access for video write.
UA0–UA15 XXXX<-- stable -->XXXX<-- stable -->X<- supplied by Z80 ->XXX
UD0–UD7 XXXXXXXXXXXXXXXXXX<IN>XXXXXXXXXXXXXXXX<IN>X<-supplied by Z80->XXX
───────┐ ┌───────┐ ┌───────┐ ┌─
/VRAS └───────────┘ └───────────┘ └───────────────┘
─────────┐ ┌───────┐ ┌───────┐
/VMUX └───────────┘ └───────────┘ └───────────────
───────────┐ ┌───────────┐ ┌───────────┐ ┌─
/VCAS └───────┘ └───────┘ └───────────┘
───────────────────────────────────────┐ ┌─
/VW └───────────────────────┘
───────────────────────────────────────┐ ┌─
/ACCESS └───────────────────────┘
─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Transcriber's note: i.e. activity is the same as before up until the leading edge of cycle 10, but now:
- /VRAS, /VMUX and /VCAS signal an extra video address from the leading edge of cycle 12;
- /VW now signals a write from the leading edge of cycle 10 until the end of the 16-cycle window;
- /ACCESS signals for the same period as /VW; and
- UAx and UDx are passed through from/to the Z80.
Physical colour output.
Pixel data stable
(2c mode) <──><──><──><──><──><──><──><──><──><──><──><──><──><──><──><──>
(4c mode) <──────><──────><──────><──────><──────><──────><──────><──────>
(16c mode) <──────────────><──────────────><──────────────><──────────────>
(256c mode) <──────────────────────────────><──────────────────────────────>
─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
16 t-states make up a memory cycle — an M-cycle. There are 57 M-cycles (or 912 t-states) in a scanline.
┌┬┬┬┬┬┬┬──────────────────────────────────────────────────┬┬┐
01234567 54 ┘││
55 ─┘│
56 ──┘
<──────> <────── display data ────────────> <─>
line params refresh address
<───────────────────────── a scanline ──────────────────────>
┌─────────────────────────────────────────────────────────
/HSYNC ───┘
─────┐ ┌───────────────────────────────────────────────────
/BURST └───┘
(can start and stop on any M-cycle) i.e.:
───────────────────────────┐ ┌─────────
/VSYNC └───────────────────────┘
┐
/VIRQ └────────────────────────────────────────────────────────────
Allowable departure from ideal spec (in nS):
| Name | Transition | Min delay | Max delay | Remarks |
|---|---|---|---|---|
| /VRAS | +- -+ | 10 10 | 30 30 | |
| /VMUX | +- -+ | 10 10 | 30 30 | |
| /VCAS | +- -+ | 10 10 | 30 30 | |
| /VW | +- -+ | 10 10 | 30 30 | |
| /ACCESS | +- -+ | 10 10 | 30 30 | |
| VRES | -+ | -70 | 70 | Apply feedback to FF |
| RC0–RC7 | -+ +- | 10 10 | 40 40 | Want consistency here |
| I.HVID (???) | +- -+ | -70 -70 | 70 70 | Apply feedback to FF |
| EC0–EC3 | -+ +- | -70 70 | 70 70 | Apply feedback to FF |
| /EXTC | -+ +- | -70 70 | 70 70 | Apply feedback to FF |
| /HSYNC | -+ +- | 0 0 | 400 400 | |
| /BURST | -+ +- | 0 0 | 400 400 | |
| /VSYNC | -+ +- | 0 0 | 400 400 | |
| /VIRQ | +- -+ | 0 0 | 400 400 |
Other timings are highly conditional on previous inputs and do not lend themselves to expression in the above format. Generally they involve asynchronous signals which are associated with flipflops with feedback. It does not matter which clock transition the changes are clocked in on... only that no indeterminate states are generated i.e.: use feedback.
Device Operation
There are two master clock inputs. The 14M signal determines the timing of the video display and the 8M signal the clock of the Z80. The two clocks run asynchronously.
The 14M signal is not exactly 14Mhz. It is the pixel dot rate in the highest resolution display modes and allows for a horizontal resolution of 672 pixels. The line period is obtained by dividing the master clock by 912. (A line period consists of 57 memory cycles of 16 master clock periods.)
The 8M signal may be 12Mhz in some machines. It is twice the clock rate of the Z80 and is used to toggle a flip flop which generates the Z80 phi signal. i.e.: 8Mhz for a 4Mhz Z80A and 12Mhz for a 6Mhz Z80B. Clock stretch is achieved by inhibiting this toggle action.
For an NTSC (American) display the master clock is chosen to be four times the colour subcarrier i.e.: 14.318Mhz (3.58Mhz *4) which gives a line period of 63.7µs.
A PAL (UK and German) display has a line period of 64µs which would suggest a master clock of 14.25Mhz. In fact unless this was phaselocked to the 4.433Mhz colour subcarrier a modulated display would show shifting "combing" which greatly degrades display appearance.
There are two possibilities:
- The 4.433Mhz is divided by 568 to form a 7805Hz square wave which is used with H/2 to phaselock the master video clock to 14.2375Mhz. This gives a line period of 64.06µs.
- A 0.89Mhz output is provided which can be used to kick a 4.433Mhz PAL crystal at 1/5th its frequency. In this case the 14M clock is 14.188Mhz and the line period is 64.28µs which would give 280ns chrominance resolution error in a PAL-D receiver.
The SECAM (French) display will probably use a 14.25Mhz master clock though it may prove rather cheaper to use 14.101Mhz.
In the following description timings relate to the NTSC machine with a Z80A processor running at 4Mhz.
The VGC controls Z80 accesses of the SLOW or VIDEO address and data buses. Access of video memory occurs in cycles of 16 master clock periods. There are 57 such cycles in a video scanline and each cycle lasts for 16 master video clock periods. In a memory cycle there are three distinct memory processes. The first two 'slots' are used by the VDC to read data in the video RAM while the last slot may be requested by the Z80 to read from or write to the video RAM (/VRAM) or to write to the VDC registers (/VIO).
14.318Mhz ┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐┌┐
┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└┘└
<───5────><───5────><────6─────>
/VDC1 /VDC2 /Z80
<──349nS─><──349nS─><───419nS──>
<────────── 11173nS ──────────>
memory cycle
In one memory cycle the VDC reads 2 bytes of data from the video RAM and simultaneously clocks out 16, 8, 4, or 2 pixels of previously loaded data to the video display (the number of pixels depends on the display mode).
The Z80 running speed is slowed when it tries to access the video RAM or VDC as it has to wait until a slot is available. In practice the slowing should be about 60% when accessing the video RAM.
It can be assumed that the VIDEO address bus is stable some 50nS after the start of a slot and that the data is read at the end of the slot. Precise hold times for data read are undefined as yet but should be of the order of 20nS.
The hardware generates a /HSYNC pulse of 4.47µS duration every 63.7µs. A colour burst strobe /BURST of 4.47µs (for PAL) is generated 2.23µs after the rising edge of /HSYNC output. /BURST is inhibited in the VSYNC video mode. Note that the /VSYNC output is controlled by the data stored in RAM (see below).
The 16 VDC slots after the beginning of the /HSYNC pulse are used by the VDC to load up 16 registers in the VDC from the LINE PARAMETER table. The last 6 VDC slots in a scanline are used by the VDC to refresh the video RAM. The other VDC slots may be used by the VDC to access display data in RAM.
Control Registers
The following registers control the operation of the VIDEO DISPLAY CONTROLLER. They are addressed as IO and the Z80 clock is stretched to synchronise with the Z80 access slots on the video address bus. Addresses 080H to 08FH are reserved for VDC registers in this and future enhanced versions. The following registers are write-only.
(Addresses 090H to 0FFH are reserved for the memory paging, tape, RS423, keyboard, sound etc: (see below))
080H /FIXBIAS
| d7 | VC1 output used to kill external colour |
| (d6,d5) | (PRIOR1, PRIOR0) external colour priority |
| (d6,d5) = 00 | EC0–EC3 select corresponding palette colour whenever the display is active and /EXTC is low. |
| (d6,d5) = 01 | The external colour on EC0–EC3 selects the corresponding palette colour if /EXTC is low and the internal display is generating a logical colour in the range COL8–COL15. |
| (d6,d5) = 10 | The external colour on EC0–EC3 selects the corresponding palette colour if /EXTC is low and the internal display is generating a logical colour in the range COL8–COL15 OR the external colour is in the range COL0–COL7 (EC3 low). |
| (d5,d5) = 11 | The external colour on EC0–EC3 selects the corresponding palette colour if /EXTC is low and the internal display is generating a logical colour in the range COL8–COL15 OR the external colour is in the ranges COL0–COL3 or COL8–COL11 (EC2 low). |
| (d4...d0) | colour bias for logical colours 8–15 |
081H /BORDER
| d7...d0 | 8-bit border colour |
082H /LPL
| d7...d0 | (a11...a4) of pointer to line paramter table in video RAM. The index into an entry of 16 bytes, (a3...a0), is generated by the hardware. |
083H /LPH
| d7 | /(load line parameter base) normally 1 |
| d6 | /(clock in line parameter base) normally 1 |
| (d3...d0) | (a15...a12) of pointer to the line parameter table in video RAM. |
The video display is controlled by values loaded into the video RAM segment (up to 64K at the top of the 4M space) by the Z80. Once this 'line parameter table' has been loaded in and the line parameter base register has been loaded the display requires no more action on the part of the Z80.
The visible display is split into 'video mode lines'. These 'modelines' are made up of 1 to 256 scanlines. (A scanline is one scan of the electron beam across the CRT and takes about 64 microseconds.)
The following 16 registers are loaded from the line parameter table before each modeline:
| SC | scanlines in this modeline (two's complement) |
| MB | the MODEBYTE (defines video display mode) |
| LM | left display margin etc |
| RM | right margin etc |
| LD1L | (a7...a0) of line data pointer LD1 |
| LD1H | (a8...a15) of line data pointer LD1 |
| LD2L | (a7...a0) of line data pointer LD2 |
| LD2H | (a8...a15) of line data pointer LD2 |
| COL0 | 8-bit value of logical colour #0 |
| COL1 | 8-bit value of logical colour #1 |
| COL2 | 8-bit value of logical colour #2 |
| COL3 | 8-bit value of logical colour #3 |
| COL4 | 8-bit value of logical colour #4 |
| COL5 | 8-bit value of logical colour #5 |
| COL6 | 8-bit value of logical colour #6 |
| COL7 | 8-bit value of logical colour #7 |
Bus Activity for the Various Modes
The possible video modes are:
- VSYNC; no border colour and use margin information to control positioning of the vertical sync pulse. This gives considerable interlace flexibility.
- PIXEL; use information pointed to by LD1 as a bit-mapped display.
- ATTR; use information pointed to by LD2 as a 2-C bitmap display and information pointed to by LD1 as cell-based graphics attributes (i.e.: to define paper and ink colours in the cell)
- CH256; use information pointed to by LD1 as indices of characters in a font of 256 characters pointed to by LD2. These characters can be any number of lines deep (up to 256). NB: offsets in the font pointer define which line of the character to start on.
- CH128; as above but assumes a font of 128 characters.
- CH64; as above but assumes a font of 64 characters.
- LPIXEL; as for pixel mode but with half the horizontal resolution.
Note that all these modes may be mixed on the same screen and that one has the choice of 2-C, 4-C, 16-C and 256-C colour modes for PIXEL, LPIXEL, CH256, CH128 and CH64 modes. Also note the special interpretation of certain bits of display data described below.
Details of bus use during a memory cycle in the various modes:
PIXEL
| /VDC1 | /VDC2 | |
| Address | LD1(15...0) | LD1(15...0) |
| Data into | BUF1(7...0) | BUF2(7...0) |
BUF1 and BUF2 are loaded sequentially into the shift register and clocked out MSB first i.e.: both are display bytes. The line data pointer LD1 is incremented twice in each memory cycle. Screen data is fetched from memory and the LD1 counter is incremented only in the active part of the display i.e.: between the left and right margins of a scanline. The scanline count loaded at the beginning of the PIXEL modeline determines how many scanlines this mode lasts for.
ATTR
| /VDC1 | /VDC2 | |
| Address | LD1(15...0) | LD2(15...0) |
| Data into | BUF1(7...0) | BUF2(7...0) |
Cell based (Spectrum type) graphics. LD1 is used as a pointer to the colour array (paper and ink colours) and LD2 points at 2-C pixel data i.e.: the display bytes. LD2 is incremented once every memory cycle while the display is active and keeps incrementing for all scanlines in the modeline. LD1 restarts from the same address for each scanline so attribute data in BUF1 applies to cells which are 8 bits wide and have a depth of the number of scanlines in the modeline.
CH256
The character modes involve indirection through the character font. A different font may be defined for each modeline and line-by-line vertical scrolling is obtained by offsetting the original index.
| /VDC1 | /VDC2 | |
| Address | LD1(15...0) | LD2(7...0),BUF1(7...0) |
| Data into | BUF1(7...0) | BUF2(7...0) |
LD1 is reloaded at the start of each scanline and acts as a pointer into a section of RAM containing the indices of the characters to be displayed. It is incremented once in each memory cycle. LD2 is a pointer into the character font to be used and is incremented at the start of each scanline (it points to a row of a character in the font). Thus the font consists of 256 bytes defining the first row of each character and then another 256 bytes for the next row of each character, etc. If the characters are 9 lines deep this requires 2304 bytes of character font (256*9). The data in BUF2 is loaded into the shift register.
CH128
| /VDC1 | /VDC2 | |
| Address | LD1(15...0) | LD2(8...0),BUF1(6...0) |
| Data into | BUF1(7...0) | BUF2(7...0) |
This is basically the same as 256 character font mode but note that the font for 128 9-line-deep characters only requires 1152 bytes of memory.
CH64
| /VDC1 | /VDC2 | |
| Address | LD1(15...0) | LD2(9...0),BUF1(5...0) |
| Data into | BUF1(7...0) | BUF2(7...0) |
This is basically the same as 256 character font mode but note that the font for 64 9-line-deep characters only requires 576 bytes of memory.
LPIXEL
| /VDC1 | /VDC2 | |
| Address | LD1(15...0) | LD1(15...0) |
| Data into | BUF1(7...0) | BUF2(7...0) |
This is much the same as the PIXEL mode except that the LD1 pointer is only incremented once in each memory cycle and the BUF2 data is not used. This gives half the horizontal resolution of the PIXEL mode.
VSYNC
No use is made of the information loaded from memory. It is equivalent to the LPIXEL mode.
The Line Parameter Registers
SC
This is a 2's complement count of the number of scanlines in the modeline. i.e.: 0FFH for one scanline in modeline (i.e.: one line of graphics).
MB
d7
If set this takes the VIRQ line low.
(d6, d5)
Defines the colour mode:
00 2-C. Two colour mode. If a bit in the byte of display data is a 1 a pixel of logical colour #1 is output and if 0 a pixel of logical colour #0. The bits are output to the screen in the following order:
┌────┬────┬────┬────┬────┬────┬────┬────┐
│ d7 │ d6 │ d5 │ d4 │ d3 │ d2 │ d0 │ d0 │
└────┴────┴────┴────┴────┴────┴────┴────┘
01 4C. Four colour mode. Pairs of bits in the byte of display data define the colour of the pixel displayed. 00 for logical colour #0, 01 for logical colour #1, 10 for logical colour #2 and 11 for logical colour #3. The pixels are displayed in the following order:
┌──────────┬──────────┬──────────┬──────────┐
│ (d7, d3) │ (d6, d2) │ (d5, d1) │ (d4, d0) │
└──────────┴──────────┴──────────┴──────────┘
10 16-C. Sixteen colour mode. Groups of 4 bits in the byte of display data define the colour of the pixel displayed. 0000 for logical colour #0 up to 1111 for logical colour #15. The pixels are displayed in the following order:
┌──────────────────┬──────────────────┐
│ (d7, d5, d3, d1) │ (d6, d4, d2, d0) │
└──────────────────┴──────────────────┘
Note that the logical colours #0 to #7 have 8-bit values loaded from the line parameter table at the start of each scanline but that logical colours #8 to #15 have 8-bit values defined as follows:
logical colour #8 = (f4, f3, f2, f2, f0, 0, 0, 0)
logical colour #9 = (f4, f3, f2, f2, f0, 0, 0, 1)
...
logical colour #15 = (f4, f3, f2, f2, f0, 1, 1, 1)
where (f4, f3, f2, f1, f0) are the low 5 bits of the FIXBIAS register.
11 256-C Two hundred and fifty six colour mode. In this mode the byte of display data defines the colour of a single display pixel.
The actual colour produced is as follows:
RED = [b0]*(4/7) + [b3]*(2/7) + [b6]*(1/7)
GREEN = [b1]*(4/7) + [b4]*(2/7) + [b7]*(1/7)
BLUE = [b3]*(2/3) + [b5]*(1/3)
d4
= 0 for /VRES. In VRES mode the LD1 and LD2 data pointers are reloaded at the start of each scanline and so the display pattern is repeated for each scanline of the modelines.
(d3, d2, d1)
Defines the video mode (see above):
- 000 VSYNC mode;
- 001 PIXEL mode;
- 010 ATTR mode;
- 011 CH256 mode;
- 100 CH128 mode;
- 101 CH64 mode;
- 110 unused at present;
- 111 LPIXEL mode.
d0
If 1 this forces a reload of the line parameter base register. This will normally occur at the end of each video frame.
LM
d7
= 1 for MSBALT i.e.: if the top bit of the display byte is 1 this causes logical colours #2 and #3 to be selected instead of #0 and #1 in the 2-C display mode. If the top bit is 0 logical colours #0 and #1 are used as usual. In both bases the top bit seen by the shift register is forced to 0. This mode is useful in simulating an 80-column VDU in the PIXEL mode. Since the MSB or LHS of any character is 0 for character spacing it can be used to highlight areas of text.
d6
= 1 for LSBALT i.e.: if the bottom bit of the display byte is 1 this causes logical colours #4 and #5 to be selected instead of #0 and #1 in the 2-C display mode. If the bottom bit is 0 logical colours #0 and #1 are used as usual. In both cases the bottom bit seen by the shift register is forced to 0. This mode is useful in simulating an 80-column VDU in the PIXEL mode. Since the LSB or RHS of any character is 0 for character spacing it can be used to highlight areas of text.
(d5...d0)
Define the left-hand margin of the active display. In practice this value will not be below 10 for the left-hand edge of the CRT. The display changes from being border colour at the left-hand margin and the display data counters start being incremented. The left-hand margin defines the start of the vertical sync pulse in the VSYNC video mode.
RM
d7
ALTIND1. If a 2-C character mode is selected this will cause characters with an index above 080H to have a paper of logical colour #2 and an ink of logical colour #3 instead of #0 and #1.
d6
ALTIND0 If a 2-C character mode is selected this will cause characters which have their next-to-most-significant bit set to swap logical colours as follows:
d5...d0
These bits define the right-hand-side of the active display. The maximum value is normally 54 for the right-hand edge of the CRT. The display returns to the border colour at the right-hand margin and the line data pointers are not incremented until the next left-hand margin. In the VSYNC video mode the right-hand margin defines the end of the vertical sync pulse.
LD1L
This 8-bit value defines the starting value of (a7...a0) of the line data pointer LD1.
LD1H
This 8-bit value defines the starting value of (a8...a15) of the line data pointer LD1.
LD1 is used as a pointer to the next byte of display data in the PIXEL and LPIXEL modes. In the CH256, CH128 and CH64 modes it is the index of a character in the character font. In the ATTR mode it points to attribute information.
LD2L
This 8-bit value defines the starting value of (a7...a0) of the line data pointer LD2.
LD2H
This 8-bit value defines the starting value of (a8...a15) of the line data pointer LD2.
LD2 is used as a pointer for pixel information in the ATTR display moed and as a pointer to the character font in the CH256, CH128 and CH64 modes. It is not at present used in the PIXEL and LPIXEL modes but it is hoped that it will define vertical pixel resolution at a later date.
COL0
Logical colour #0. This is the paper colour in C-2 modes though note the exceptions above.
COL1
Logical colour #1. This is the ink colour in C-2 modes though note the exceptions above.
COL2
Logical colour #2 (Alternate paper).
COL3
Logical colour #3 (Alternate ink).
COL4
Logical colour #4.
COL5
Logical colour #5.
COL6
Logical colour #6.
COL7
Logical colour #7.