diff --git a/Apple-IIgs-Memory-Map.md b/Apple-IIgs-Memory-Map.md
index 1ea1e70..7a5d4ff 100644
--- a/Apple-IIgs-Memory-Map.md
+++ b/Apple-IIgs-Memory-Map.md
@@ -2,28 +2,42 @@ The Apple IIgs has a 24-bit address space, which is conventionally broken down i
 
 # Banks $F0–$FF: ROM
 
-The final 16 banks are set aside for up to one megabyte of ROM; the built-in ROMs for the IIgs were initially 128kb and later 256kb in size and in both cases they appear at the end of the ROM area.
+The final 16 banks are set aside for up to one megabyte of ROM.
+
+The built-in ROMs for the IIgs were initially 128kb, and later 256kb. In both cases they fill the end of the ROM area.
 
 ROM access is always 'fast' — access windows are five cycles of the 14Mhz clock.
 
 # Banks $E0 and $E1: Mega II RAM, card access
 
-Banks $E0 and $E1 access memory via the IIe-emulating Mega II chip. Bank $E0 contains main RAM and bank $E1 contains auxiliary RAM. They are subject to language-card banking only. The video buffer always natively lives in this area.
+Banks $E0 and $E1 access memory via the IIe-emulating Mega II chip. Bank $E0 contains main RAM and bank $E1 contains auxiliary RAM. They are subject to language-card banking only.
 
-Both reads and writes are performed via the Mega II so are 'slow' — access windows are usually fourteen cycles of the 14Mhz clock though every 64th is stretched to sixteen cycles as per the original hardware to ensure that IIe-style video remains in phase with the NTSC colour subcarrier.
+The video buffer always lives in this area.
+
+Both reads and writes are performed via the Mega II so are 'slow' — access windows are fourteen cycles of the 14Mhz clock, with one exception: every 64th window is sixteen cycles.
+
+The extended 64th window ensures that video remains in phase with the NTSC colour subcarrier.
 
 # Banks $02–$7f: Fast RAM
 
 Banks $02–$7f contain regular system RAM and are not subject to paging or other rearrangement.
 
-RAM access is 'fast' — windows are five cycles of the 14Mhz clock — but one window in ten is lost to memory refresh.
+RAM access is 'fast' — windows are five cycles of the 14Mhz clock, though one window in ten is lost to memory refresh.
 
 # Primarily banks $00 and $01: Some ROM, Fast RAM and Shadowing
 
 The first 128kb of fast RAM occupies banks $00 and $01.
 
-Language card banking affects both pages; other auxiliary/main selections may expose parts of bank $01 within bank $00. Regardless of language card setting, the 65816's VPB (i.e. vector pull) signal selects ROM rather than RAM.
+Language card banking affects both pages; other auxiliary/main selections may expose parts of bank $01 within bank $00.
 
-Parts of the pages may additionally be shadowed up to corresponding regions of $e0 and $e1, i.e. to act as a write-through cache, depending on the register at $c035. Auxiliary paging is applied before shadowing so a write to bank $00 that ends up being redirected to $01 will be shadowed to $e1 if shadowing is enabled.
+Parts of these pages may additionally be shadowed to corresponding regions of $e0 and $e1. Auxiliary paging is applied before shadowing, so a write to bank $00 that is redirected to $01 will be shadowed to $e1.
 
-The speed register at $c036 also has a bank shadowing control bit; if bit 4 is set to 1 then shadowing will apply in all banks, based only upon the lowest address line. Otherwise it will apply in banks $01 and $02 only.
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+# Additional Shadowing Options
+
+Bit 4 of the speed register can enable shadowing in all banks, based only upon address line 16. It will otherwise it will apply in banks $01 and $02 only.
+
+Orthogonally, bit 0 of the new video register permits address line 16 to be blocked for shadowing. In that case all shadowed writes will be directed to bank $e0.
+
+# Special Case: Vector Pull
+
+The 65816's VPB (i.e. vector pull) signal always selects the final page of ROM.
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