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My first stab at a restatement of ZX80 and ZX81 hardware.

Thomas Harte 2017-06-14 09:49:27 -04:00
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The unexpanded ZX80 and ZX81 combine a Z80 microprocessor, 1kb of static RAM, 4 or 8kb of ROM and various bits of support logic. In the ZX81 the support logic is provided in a single ULA.
The Z80 is clocked at 3.25Mhz and its display is generated programmatically.
# Memory map
The ZX80 has a 4kb ROM. That ROM is mapped from address 0x0000. It has 1kb RAM which appears at 0x4000. The RAM is mirrored to 0x8000.
# Video Generation on the ZX80
Programmatic sync is used for vertical synchronisation. Reading from any port which had an address with the low bit clear causes the synchronisation signal to begin. Writing to any port causes it to end.
A combination of the Z80's program counter and refresh counter, and an external 3-bit counter — the line counter — is used to generate lines of video.
When:
* M1 is set; and
* bit 15 of the address bus is set; and
* the HALT line is not set:
the support circuitry will intercept the value being read from memory before the CPU has sampled it.
If bit 6 of the value intercepted is clear then a video value will be output, which means that:
* the value being supplied to the Z80 will be forced to 0x00;
* having received the refresh address R, a ROM access to the address `(R & 0xff00) | (((intercepted value) & 0x3f) << 3) | (line counter)` is attempted;
* the value on the bus will then be output as pixels. If the top bit of the intercepted value was set, it will be inverted.
If the address formed from the refresh address, intercepted value and line counter is located in RAM and the RAM in use loads the data bus during refresh cycles, the value output will actually be that directly addressed by the refresh counter rather than one from ROM.
If bit 6 of the refresh address is clear during a refresh cycle then an interrupt is signalled.
If the bus signals an interrupt acknowledge then:
* the line counter is incremented; and
* a 20-cycle period of video sync will be signalled 13 cycles later.
The line counter is reset on any port output.
## Net Effect
As designed, lines of text are assembled in memory, terminated by a HALT instruction. At an appropriate moment during display, the CPU is sent to execute those lines from the 0x8000 mirror of RAM. The video circuit captures the opcodes it would have performed and outputs them as video, feeding NOPs to the CPU. If it hits a HALT instruction, that instruction is let through and the CPU enters a halted state. It is next awoken when the incrementing refresh address triggers an interrupt.
Unintentionally, the refresh counter can be used as a direct video address with compatible RAM.
It's also possible to reset the line counter repeatedly by triggering programmatic sync at the same time as the automatic sync would occur anyway, as the two things are ORd.