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Some corrections on banks $00 and $01 as I learn more.

Thomas Harte 2020-10-21 16:32:05 -04:00
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Apple-IIgs-Memory-Map.md

@ -6,9 +6,9 @@ The final 16 banks are set aside for up to one megabyte of ROM; the built-in ROM
ROM access is always 'fast' — access windows are five cycles of the 14Mhz clock.
# Banks $E0 and $E1: Mega II RAM
# Banks $E0 and $E1: Mega II RAM, card access
Banks $E0 and $E1 access RAM via the IIe-emulating Mega II chip. Bank $E0 contains main RAM and bank $E1 contains auxiliary RAM. These areas are not subject to any further paging or other rearrangement. The video buffer always natively lives in this area.
Banks $E0 and $E1 access memory via the IIe-emulating Mega II chip. Bank $E0 contains main RAM and bank $E1 contains auxiliary RAM and are subject to language-card banking only. The video buffer always natively lives in this area.
Both reads and writes are performed via the Mega II so are 'slow' — access windows are usually fourteen cycles of the 14Mhz clock though every 64th is stretched to sixteen cycles as per the original hardware to ensure that IIe-style video remains in phase with the colour subcarrier.
@ -18,23 +18,12 @@ Banks $02–$7f contain regular system RAM and are not subject to paging or othe
RAM access is 'fast' — windows are five cycles of the 14Mhz clock — but one window is lost after every XX to memory refresh.
# Primarily banks $01 and $02: Some ROM, Fast RAM and Shadowing
# Primarily banks $00 and $01: Some ROM, Fast RAM and Shadowing
The first 128kb of fast RAM occupies banks $01 and $02. The IIgs supports two additional features in those banks:
The first 128kb of fast RAM occupies banks $00 and $01.
* shadowing, in which banks $01 and $02 act as a write-through cache for parts of banks $E0 and $E1; which parts and how they're mapped varies but is designed to mimic the main/auxiliary selections available on a IIe; and
* mirroring the final part of ROM into the top of bank $00, also to mimic the memory map of a IIe.
Language card banking affects both pages; other auxiliary/main selections may expose parts of bank $01 within bank $00. Regardless of language card setting, the 65816's VPB (i.e. vector pull) signal selects ROM rather than RAM.
As an additional caveat, the 65816's VPL (i.e. vector pull) signal may be used to select ROM rather than RAM.
Shadowing is permitted or inhibited in ranges using the shadow register at $c035; anywhere it is disabled by writing a 1 to the corresponding bit no shadowing occurs, otherwise:
* if bit 6 is clear, the region from $C000 onwards acts as a cache for the equivalent area on a IIe, subject to the proviso that vector pulls always go to ROM even if the IIe-esque softswitches have selected RAM;
* bit 5 inhibits text page 2 and auxiliary text page 2, i.e. the region $0800–$0DFF in both banks;
* bit 4 inhibits auxiliary high-res graphics pages 1 and 2; setting it to 1 overrides bits 0–3;
* bit 3 inhibits super high-resolution graphics, i.e. $2000–$BFFF;
* bit 2 inhibits page 2 high-resolution graphics, i.e. the region from $4000–$5FFF;
* bit 1 inhibits page 1 high-resolution graphics, i.e. the region from $2000–$3FFF; and
* bit 0 inhibits text page 1, i.e. $0400–$07FF.
Parts of the pages may additionally be shadowed up to corresponding regions of $e0 and $e1, i.e. to act as a write-through cache, depending on the register at $c035.
The speed register at $c036 also has a bank shadowing control bit; if bit 4 is set to 1 then shadowing will apply in all banks. Otherwise it will apply in $01 and $02 only.