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https://github.com/Russell-S-Harper/COMMON.git
synced 2024-12-26 06:29:38 +00:00
Revised MOD to prevent overflow.
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@ -261,11 +261,11 @@ _3 ORA _F
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RTS
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.)
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_DEC .( ; DEC r 8r Rr <- dec(Rr) - convert Rr from hex aabbcc.dd to decimal ######.##
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_DEC .( ; DEC r 8r Rr <- dec(Rr) - convert Rr from hex aabbccdd to decimal ######.###
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RTS
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.)
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_HEX .( ; HEX r 9r Rr <- hex(Rr) - convert Rr from decimal ######.## to hex aabbcc.dd
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_HEX .( ; HEX r 9r Rr <- hex(Rr) - convert Rr from decimal ######.### to hex aabbccdd
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RTS
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.)
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@ -604,7 +604,7 @@ _2 JSR _CPXI0 ; copy p to I0
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STA _I3+2
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LDA _R0+3,Y
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STA _I3+3
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; I4 / I5 will form 64-bit result
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; I4 / I5 will form 64-bit result for DIV
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LDX #_I4-_R0
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JSR _ZERQX
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LDA _I0+3 ; get sign of result
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@ -613,37 +613,37 @@ _2 JSR _CPXI0 ; copy p to I0
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RTS
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.)
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_CMPDM .( ; compare I0/I1 to I2/I3, return result in status
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_CPQXDM .( ; compare I0/I1 to quadword pointed by X, return result in status
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LDA _I1+3
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CMP _I3+3
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CMP _R1+3,X
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _I1+2
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CMP _I3+2
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CMP _R1+2,X
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _I1+1
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CMP _I3+1
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CMP _R1+1,X
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _I1
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CMP _I3
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CMP _R1,X
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _I0+3
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CMP _I2+3
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CMP _R0+3,X
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _I0+2
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CMP _I2+2
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CMP _R0+2,X
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _I0+1
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CMP _I2+1
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CMP _R0+1,X
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _I0
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CMP _I2
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CMP _R0,X
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_1 RTS
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.)
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@ -711,7 +711,8 @@ _DIV .( ; DIV r pq dr pq Rr <- Rp / Rq - division
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LDX #_I3-_R0 ; absolute value of register q saved in I3
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JSR _ABSX
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LDY #51 ; 51 bits are enough, and ensure alignment
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_1 JSR _CMPDM ; is I0/I1 < I2/I3
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_1 LDX #_I2-_R0 ; is I0/I1 < I2/I3
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JSR _CPQXDM
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BCC _2 ; yes, skip subtraction
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BEQ _4 ; special case when p = q
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JSR _UPDDM ; I0/I1 -= I2/I3
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@ -733,10 +734,44 @@ _5 LDX #_I4-_R0
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_6 JMP _RETI0X ; pull X, transfer I0 to r register, let it handle the return
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.)
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_MOD .(
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RTS
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_MOD .( ; MOD r pq er pq Rr <- Rp % Rq - modulus
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TXA
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PHA ; save r register for later
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JSR _INTDM ; initialize
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PHA ; save sign of result
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LDX #_I0-_R0 ; absolute value of register p saved in I0
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JSR _ABSX
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LDX #_I3-_R0 ; absolute value of register q saved in I3
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JSR _ABSX
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LDA _I3 ; copy |q| in I3 to I4
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STA _I4
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LDA _I3+1
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STA _I4+1
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LDA _I3+2
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STA _I4+2
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LDA _I3+3
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STA _I4+3
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LDY #34 ; 34 shifts are enough
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_1 LDX #_I4-_R0 ; is I0/I1 < I4/I5?
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JSR _CPQXDM
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BCC _3 ; yes, all done
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LDX #_I2-_R0 ; is I0/I1 < I2/I3
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JSR _CPQXDM
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BCC _2 ; yes, skip subtraction
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JSR _UPDDM ; I0/I1 -= I2/I3
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_2 JSR _SHDDM ; I2/I3 /= 2
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DEY
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BNE _1
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_3 LDA _F ; clear underflow
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AND #_F_U^$FF
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STA _F
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PLA ; set the sign of the product
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BEQ _4
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LDX #_I0-_R0 ; negate I0
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JSR _NEGX
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_4 JMP _RETI0X ; pull X, transfer I0 to r register, let it handle the return
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.)
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_ESC .( ; ESC 00 - escape back into regular assembler
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PLA ; discard the COMMON _1 return address
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PLA
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@ -20,8 +20,8 @@
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; INR r 5r Rr <- Rr + 1.0 - increment register
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; DCR r 6r Rr <- Rr - 1.0 - decrement register
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; TST r 7r F <- Rr <=> 0.0 - test register
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; DEC r 8r Rr <- dec(Rr) - convert Rr from hex aabbccdd to decimal #########
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; HEX r 9r Rr <- hex(Rr) - convert Rr from decimal ######### to hex aabbccdd
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; DEC r 8r Rr <- dec(Rr) - convert Rr from hex aabbccdd to decimal ######.###
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; HEX r 9r Rr <- hex(Rr) - convert Rr from decimal ######.### to hex aabbccdd
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; ADD r pq ar pq Rr <- Rp + Rq - addition
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; SUB r pq br pq Rr <- Rp - Rq - subtraction
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; MUL r pq cr pq Rr <- Rp * Rq - multiplication
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@ -5,10 +5,10 @@
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HDR(DEMO)
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CMN
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SET(R0, 1048575.9995)
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SET(R1, 3)
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DIV(R2, R0, R1)
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MUL(R3, R2, R1)
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SET(R0, 1048575)
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SET(R1, 3 * 5 * 5)
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MOD(R2, R0, R1)
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;SUB(R3, R0, R2)
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ESC
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BRK
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