2017-06-04 20:38:34 +00:00
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#include "stdafx.h"
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#include "Z80.h"
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// based on http://www.z80.info/decoding.htm
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// Half carry flag help from https://github.com/oubiwann/z80
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2017-06-05 21:39:15 +00:00
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EightBit::Z80::Z80(Memory& memory, InputOutput& ports)
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2017-06-11 08:45:34 +00:00
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: IntelProcessor(memory),
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2017-06-05 21:39:15 +00:00
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m_ports(ports),
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2017-06-04 20:38:34 +00:00
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m_registerSet(0),
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m_accumulatorFlagsSet(0),
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m_refresh(0x7f),
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iv(0xff),
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m_interruptMode(0),
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m_iff1(false),
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m_iff2(false),
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m1(false),
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m_prefixCB(false),
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m_prefixDD(false),
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m_prefixED(false),
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m_prefixFD(false) {
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IX().word = 0xffff;
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IY().word = 0xffff;
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}
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2017-06-05 21:39:15 +00:00
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void EightBit::Z80::reset() {
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2017-06-11 08:45:34 +00:00
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IntelProcessor::reset();
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2017-06-11 20:08:40 +00:00
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di();
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2017-06-04 20:38:34 +00:00
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}
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2017-06-05 21:39:15 +00:00
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void EightBit::Z80::initialise() {
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2017-06-04 20:38:34 +00:00
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2017-06-11 08:45:34 +00:00
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IntelProcessor::initialise();
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2017-06-04 20:38:34 +00:00
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IM() = 0;
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AF().word = 0xffff;
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BC().word = 0xffff;
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DE().word = 0xffff;
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HL().word = 0xffff;
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exxAF();
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exx();
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AF().word = 0xffff;
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BC().word = 0xffff;
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DE().word = 0xffff;
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HL().word = 0xffff;
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IX().word = 0xffff;
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IY().word = 0xffff;
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REFRESH() = 0x7f;
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IV() = 0xff;
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m_prefixCB = false;
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m_prefixDD = false;
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m_prefixED = false;
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m_prefixFD = false;
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}
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#pragma region Interrupt routines
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2017-06-11 20:08:40 +00:00
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void EightBit::Z80::di() {
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2017-06-04 20:38:34 +00:00
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IFF1() = IFF2() = false;
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}
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2017-06-11 20:08:40 +00:00
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void EightBit::Z80::ei() {
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IFF1() = IFF2() = true;
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}
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2017-06-05 21:39:15 +00:00
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int EightBit::Z80::interrupt(bool maskable, uint8_t value) {
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cycles = 0;
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if (!maskable || (maskable && IFF1())) {
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if (maskable) {
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di();
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switch (IM()) {
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case 0:
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M1() = true;
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cycles += execute(value);
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break;
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case 1:
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restart(7 << 3);
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cycles += 13;
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break;
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case 2:
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pushWord(pc);
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pc.low = value;
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pc.high = IV();
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cycles += 19;
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break;
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}
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} else {
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IFF1() = false;
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restart(0x66);
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cycles += 13;
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}
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}
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// Could be zero for a masked interrupt...
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return cycles;
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}
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#pragma endregion Interrupt routines
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#pragma region Flag manipulation helpers
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::adjustSign(uint8_t& f, uint8_t value) {
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setFlag(f, SF, value & SF);
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::adjustZero(uint8_t& f, uint8_t value) {
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clearFlag(f, ZF, value);
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::adjustParity(uint8_t& f, uint8_t value) {
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static const uint8_t lookup[0x10] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
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auto set = lookup[highNibble(value)] + lookup[lowNibble(value)];
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clearFlag(f, PF, set % 2);
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}
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void EightBit::Z80::adjustSZ(uint8_t& f, uint8_t value) {
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adjustSign(f, value);
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adjustZero(f, value);
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::adjustSZP(uint8_t& f, uint8_t value) {
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adjustSZ(f, value);
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adjustParity(f, value);
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::adjustXY(uint8_t& f, uint8_t value) {
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setFlag(f, XF, value & XF);
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setFlag(f, YF, value & YF);
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::adjustSZPXY(uint8_t& f, uint8_t value) {
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adjustSZP(f, value);
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adjustXY(f, value);
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::adjustSZXY(uint8_t& f, uint8_t value) {
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adjustSZ(f, value);
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adjustXY(f, value);
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::postIncrement(uint8_t& f, uint8_t value) {
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adjustSZXY(f, value);
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clearFlag(f, NF);
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setFlag(f, VF, value == Bit7);
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clearFlag(f, HC, lowNibble(value));
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::Z80::postDecrement(uint8_t& f, uint8_t value) {
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adjustSZXY(f, value);
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setFlag(f, NF);
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setFlag(f, VF, value == Mask7);
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clearFlag(f, HC, lowNibble(value + 1));
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}
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#pragma endregion Flag manipulation helpers
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#pragma region PC manipulation: call/ret/jp/jr
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2017-06-11 20:08:40 +00:00
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bool EightBit::Z80::jrConditionalFlag(int flag) {
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switch (flag) {
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case 0: // NZ
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return jrConditional(!(F() & ZF));
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case 1: // Z
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return jrConditional(F() & ZF);
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case 2: // NC
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return jrConditional(!(F() & CF));
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case 3: // C
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return jrConditional(F() & CF);
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case 4: // PO
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return jrConditional(!(F() & PF));
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case 5: // PE
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return jrConditional(F() & PF);
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case 6: // P
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return jrConditional(!(F() & SF));
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case 7: // M
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return jrConditional(F() & SF);
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}
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throw std::logic_error("Unhandled JR conditional");
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}
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2017-06-11 20:08:40 +00:00
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bool EightBit::Z80::jumpConditionalFlag(int flag) {
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switch (flag) {
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case 0: // NZ
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return jumpConditional(!(F() & ZF));
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case 1: // Z
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return jumpConditional(F() & ZF);
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case 2: // NC
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return jumpConditional(!(F() & CF));
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case 3: // C
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return jumpConditional(F() & CF);
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case 4: // PO
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return jumpConditional(!(F() & PF));
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case 5: // PE
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return jumpConditional(F() & PF);
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case 6: // P
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return jumpConditional(!(F() & SF));
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case 7: // M
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return jumpConditional(F() & SF);
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}
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throw std::logic_error("Unhandled JP conditional");
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}
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2017-06-05 21:39:15 +00:00
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void EightBit::Z80::retn() {
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ret();
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IFF1() = IFF2();
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}
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2017-06-05 21:39:15 +00:00
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void EightBit::Z80::reti() {
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retn();
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}
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2017-06-11 20:08:40 +00:00
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bool EightBit::Z80::returnConditionalFlag(int flag) {
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switch (flag) {
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case 0: // NZ
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return returnConditional(!(F() & ZF));
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case 1: // Z
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return returnConditional(F() & ZF);
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case 2: // NC
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return returnConditional(!(F() & CF));
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case 3: // C
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return returnConditional(F() & CF);
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case 4: // PO
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return returnConditional(!(F() & PF));
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case 5: // PE
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return returnConditional(F() & PF);
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case 6: // P
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return returnConditional(!(F() & SF));
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case 7: // M
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return returnConditional(F() & SF);
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}
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throw std::logic_error("Unhandled RET conditional");
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}
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2017-06-11 20:08:40 +00:00
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bool EightBit::Z80::callConditionalFlag(int flag) {
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switch (flag) {
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case 0: // NZ
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return callConditional(!(F() & ZF));
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case 1: // Z
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return callConditional(F() & ZF);
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case 2: // NC
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return callConditional(!(F() & CF));
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case 3: // C
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return callConditional(F() & CF);
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case 4: // PO
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return callConditional(!(F() & PF));
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case 5: // PE
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return callConditional(F() & PF);
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case 6: // P
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return callConditional(!(F() & SF));
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case 7: // M
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return callConditional(F() & SF);
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}
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throw std::logic_error("Unhandled CALL conditional");
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}
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#pragma endregion PC manipulation: call/ret/jp/jr
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#pragma region 16-bit arithmetic
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void EightBit::Z80::sbc(register16_t& operand, register16_t value) {
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auto& f = F();
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auto before = operand;
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auto beforeNegative = before.high & SF;
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auto valueNegative = value.high & SF;
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auto result = before.word - value.word - (f & CF);
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operand.word = result;
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auto afterNegative = operand.high & SF;
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2017-06-18 17:14:39 +00:00
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setFlag(f, SF, afterNegative);
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clearFlag(f, ZF, operand.word);
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adjustHalfCarrySub(f, before.high, value.high, operand.high);
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adjustOverflowSub(f, beforeNegative, valueNegative, afterNegative);
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setFlag(f, NF);
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setFlag(f, CF, result & Bit16);
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adjustXY(f, operand.high);
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}
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void EightBit::Z80::adc(register16_t& operand, register16_t value) {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
|
2017-06-04 20:38:34 +00:00
|
|
|
auto before = operand;
|
|
|
|
|
|
|
|
auto beforeNegative = before.high & SF;
|
|
|
|
auto valueNegative = value.high & SF;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
auto result = before.word + value.word + (f & CF);
|
2017-06-04 20:38:34 +00:00
|
|
|
operand.word = result;
|
|
|
|
|
|
|
|
auto afterNegative = operand.high & SF;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, SF, afterNegative);
|
|
|
|
clearFlag(f, ZF, result);
|
|
|
|
adjustHalfCarryAdd(f, before.high, value.high, operand.high);
|
|
|
|
adjustOverflowAdd(f, beforeNegative, valueNegative, afterNegative);
|
|
|
|
clearFlag(f, NF);
|
|
|
|
setFlag(f, CF, result & Bit16);
|
|
|
|
adjustXY(f, operand.high);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::add(register16_t& operand, register16_t value) {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
|
2017-06-04 20:38:34 +00:00
|
|
|
auto before = operand;
|
|
|
|
|
|
|
|
auto result = before.word + value.word;
|
|
|
|
|
|
|
|
operand.word = result;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, NF);
|
|
|
|
setFlag(f, CF, result & Bit16);
|
|
|
|
adjustHalfCarryAdd(f, before.high, value.high, operand.high);
|
|
|
|
adjustXY(f, operand.high);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion 16-bit arithmetic
|
|
|
|
|
|
|
|
#pragma region ALU
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::add(uint8_t& operand, uint8_t value, int carry) {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
|
2017-06-04 20:38:34 +00:00
|
|
|
register16_t result;
|
|
|
|
result.word = operand + value + carry;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustHalfCarryAdd(f, operand, value, result.low);
|
|
|
|
adjustOverflowAdd(f, operand, value, result.low);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
|
|
|
operand = result.low;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, NF);
|
|
|
|
setFlag(f, CF, result.word & Bit8);
|
|
|
|
adjustSZXY(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::adc(uint8_t& operand, uint8_t value) {
|
2017-06-04 20:38:34 +00:00
|
|
|
add(operand, value, F() & CF);
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::sub(uint8_t& operand, uint8_t value, int carry) {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
|
2017-06-04 20:38:34 +00:00
|
|
|
register16_t result;
|
|
|
|
result.word = operand - value - carry;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustHalfCarrySub(f, operand, value, result.low);
|
|
|
|
adjustOverflowSub(f, operand, value, result.low);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
|
|
|
operand = result.low;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, NF);
|
|
|
|
setFlag(f, CF, result.word & Bit8);
|
|
|
|
adjustSZXY(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::sbc(uint8_t& operand, uint8_t value) {
|
2017-06-04 20:38:34 +00:00
|
|
|
sub(operand, value, F() & CF);
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::andr(uint8_t& operand, uint8_t value) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
operand &= value;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, HC);
|
|
|
|
clearFlag(f, CF | NF);
|
|
|
|
adjustSZPXY(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::xorr(uint8_t& operand, uint8_t value) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
operand ^= value;
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, HC | CF | NF);
|
|
|
|
adjustSZPXY(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::orr(uint8_t& operand, uint8_t value) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
operand |= value;
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, HC | CF | NF);
|
|
|
|
adjustSZPXY(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::compare(uint8_t value) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto check = A();
|
|
|
|
sub(check, value);
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustXY(f, value);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion ALU
|
|
|
|
|
|
|
|
#pragma region Shift and rotate
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
uint8_t& EightBit::Z80::rlc(uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto carry = operand & Bit7;
|
|
|
|
operand <<= 1;
|
|
|
|
carry ? operand |= Bit0 : operand &= ~Bit0;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, carry);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
adjustXY(f, operand);
|
2017-06-15 21:21:26 +00:00
|
|
|
return operand;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
uint8_t& EightBit::Z80::rrc(uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto carry = operand & Bit0;
|
|
|
|
operand >>= 1;
|
|
|
|
carry ? operand |= Bit7 : operand &= ~Bit7;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, carry);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
adjustXY(f, operand);
|
2017-06-15 21:21:26 +00:00
|
|
|
return operand;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
uint8_t& EightBit::Z80::rl(uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
auto oldCarry = f & CF;
|
2017-06-04 20:38:34 +00:00
|
|
|
auto newCarry = operand & Bit7;
|
|
|
|
operand <<= 1;
|
|
|
|
oldCarry ? operand |= Bit0 : operand &= ~Bit0;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, newCarry);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
adjustXY(f, operand);
|
2017-06-15 21:21:26 +00:00
|
|
|
return operand;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
uint8_t& EightBit::Z80::rr(uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
auto oldCarry = f & CF;
|
2017-06-04 20:38:34 +00:00
|
|
|
auto newCarry = operand & Bit0;
|
|
|
|
operand >>= 1;
|
|
|
|
operand |= oldCarry << 7;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, newCarry);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
adjustXY(f, operand);
|
2017-06-15 21:21:26 +00:00
|
|
|
return operand;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
uint8_t& EightBit::Z80::sla(uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto newCarry = operand & Bit7;
|
|
|
|
operand <<= 1;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, newCarry);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
adjustXY(f, operand);
|
2017-06-15 21:21:26 +00:00
|
|
|
return operand;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
uint8_t& EightBit::Z80::sra(uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto new7 = operand & Bit7;
|
|
|
|
auto newCarry = operand & Bit0;
|
|
|
|
operand >>= 1;
|
|
|
|
operand |= new7;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, newCarry);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
adjustXY(f, operand);
|
2017-06-15 21:21:26 +00:00
|
|
|
return operand;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
uint8_t& EightBit::Z80::sll(uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto newCarry = operand & Bit7;
|
|
|
|
operand <<= 1;
|
|
|
|
operand |= 1;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, newCarry);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
adjustXY(f, operand);
|
2017-06-15 21:21:26 +00:00
|
|
|
return operand;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
uint8_t& EightBit::Z80::srl(uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto newCarry = operand & Bit0;
|
|
|
|
operand >>= 1;
|
|
|
|
operand &= ~Bit7; // clear bit 7
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, newCarry);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
adjustXY(f, operand);
|
|
|
|
setFlag(f, ZF, operand);
|
2017-06-15 21:21:26 +00:00
|
|
|
return operand;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion Shift and rotate
|
|
|
|
|
|
|
|
#pragma region BIT/SET/RES
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::bit(int n, uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
auto carry = f & CF;
|
2017-06-04 20:38:34 +00:00
|
|
|
uint8_t discarded = operand;
|
|
|
|
andr(discarded, 1 << n);
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, PF, discarded);
|
|
|
|
setFlag(f, CF, carry);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::res(int n, uint8_t& operand) {
|
2017-06-04 20:38:34 +00:00
|
|
|
auto bit = 1 << n;
|
|
|
|
operand &= ~bit;
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::set(int n, uint8_t& operand) {
|
2017-06-04 20:38:34 +00:00
|
|
|
auto bit = 1 << n;
|
|
|
|
operand |= bit;
|
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion BIT/SET/RES
|
|
|
|
|
|
|
|
#pragma region Miscellaneous instructions
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::neg() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto original = A();
|
|
|
|
A() = 0;
|
|
|
|
sub(A(), original);
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, PF, original == Bit7);
|
|
|
|
setFlag(f, CF, original);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::daa() {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
|
2017-06-04 20:38:34 +00:00
|
|
|
uint8_t a = A();
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
auto lowAdjust = (f & HC) | (lowNibble(A()) > 9);
|
|
|
|
auto highAdjust = (f & CF) | (A() > 0x99);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
if (f & NF) {
|
2017-06-04 20:38:34 +00:00
|
|
|
if (lowAdjust)
|
|
|
|
a -= 6;
|
|
|
|
if (highAdjust)
|
|
|
|
a -= 0x60;
|
|
|
|
} else {
|
|
|
|
if (lowAdjust)
|
|
|
|
a += 6;
|
|
|
|
if (highAdjust)
|
|
|
|
a += 0x60;
|
|
|
|
}
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
f = (f & (CF | NF)) | (A() > 0x99) | ((A() ^ a) & HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZPXY(f, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
|
|
|
A() = a;
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::cpl() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
A() = ~A();
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustXY(f, A());
|
|
|
|
setFlag(f, HC | NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::scf() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
setFlag(f, CF);
|
|
|
|
adjustXY(f, A());
|
|
|
|
clearFlag(f, HC | NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::ccf() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
auto carry = f & CF;
|
|
|
|
setFlag(f, HC, carry);
|
|
|
|
clearFlag(f, CF, carry);
|
|
|
|
clearFlag(f, NF);
|
|
|
|
adjustXY(f, A());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::xhtl(register16_t& operand) {
|
2017-06-04 20:38:34 +00:00
|
|
|
m_memory.ADDRESS() = sp;
|
|
|
|
MEMPTR().low = m_memory.reference();
|
|
|
|
m_memory.reference() = operand.low;
|
|
|
|
operand.low = MEMPTR().low;
|
|
|
|
m_memory.ADDRESS().word++;
|
|
|
|
MEMPTR().high = m_memory.reference();
|
|
|
|
m_memory.reference() = operand.high;
|
|
|
|
operand.high = MEMPTR().high;
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::xhtl() {
|
2017-06-15 21:21:26 +00:00
|
|
|
xhtl(HL2());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion Miscellaneous instructions
|
|
|
|
|
|
|
|
#pragma region Block instructions
|
|
|
|
|
|
|
|
#pragma region Block compare instructions
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::blockCompare() {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
|
|
|
|
2017-06-04 20:38:34 +00:00
|
|
|
m_memory.ADDRESS() = HL();
|
|
|
|
|
|
|
|
auto value = m_memory.reference();
|
|
|
|
uint8_t result = A() - value;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, PF, --BC().word);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZ(f, result);
|
|
|
|
adjustHalfCarrySub(f, A(), value, result);
|
|
|
|
setFlag(f, NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
if (f & HC)
|
2017-06-04 20:38:34 +00:00
|
|
|
result -= 1;
|
|
|
|
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, YF, result & Bit1);
|
|
|
|
setFlag(f, XF, result & Bit3);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::cpi() {
|
2017-06-04 20:38:34 +00:00
|
|
|
blockCompare();
|
|
|
|
HL().word++;
|
|
|
|
MEMPTR().word++;
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::cpd() {
|
2017-06-04 20:38:34 +00:00
|
|
|
blockCompare();
|
|
|
|
HL().word--;
|
|
|
|
MEMPTR().word--;
|
|
|
|
}
|
|
|
|
|
2017-06-12 13:33:00 +00:00
|
|
|
bool EightBit::Z80::cpir() {
|
2017-06-04 20:38:34 +00:00
|
|
|
cpi();
|
2017-06-12 13:33:00 +00:00
|
|
|
MEMPTR().word = pc.word;
|
|
|
|
auto again = (F() & PF) && !(F() & ZF); // See CPI
|
2017-06-14 21:33:02 +00:00
|
|
|
if (again)
|
2017-06-12 13:33:00 +00:00
|
|
|
MEMPTR().word--;
|
|
|
|
return again;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-12 13:33:00 +00:00
|
|
|
bool EightBit::Z80::cpdr() {
|
2017-06-04 20:38:34 +00:00
|
|
|
cpd();
|
2017-06-14 21:33:02 +00:00
|
|
|
MEMPTR().word = pc.word - 1;
|
2017-06-12 13:33:00 +00:00
|
|
|
auto again = (F() & PF) && !(F() & ZF); // See CPD
|
2017-06-15 21:21:26 +00:00
|
|
|
if (!again)
|
2017-06-12 13:33:00 +00:00
|
|
|
MEMPTR().word--;
|
|
|
|
return again;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion Block compare instructions
|
|
|
|
|
|
|
|
#pragma region Block load instructions
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::blockLoad(register16_t source, register16_t destination) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
m_memory.ADDRESS() = source;
|
|
|
|
auto value = m_memory.reference();
|
|
|
|
m_memory.ADDRESS() = destination;
|
|
|
|
m_memory.reference() = value;
|
|
|
|
auto xy = A() + value;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, XF, xy & 8);
|
|
|
|
setFlag(f, YF, xy & 2);
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
setFlag(f, PF, --BC().word);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::ldd() {
|
2017-06-04 20:38:34 +00:00
|
|
|
blockLoad(HL(), DE());
|
|
|
|
HL().word--;
|
|
|
|
DE().word--;
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::ldi() {
|
2017-06-04 20:38:34 +00:00
|
|
|
blockLoad(HL(), DE());
|
|
|
|
HL().word++;
|
|
|
|
DE().word++;
|
|
|
|
}
|
|
|
|
|
2017-06-12 13:33:00 +00:00
|
|
|
bool EightBit::Z80::ldir() {
|
2017-06-04 20:38:34 +00:00
|
|
|
ldi();
|
2017-06-12 13:33:00 +00:00
|
|
|
auto again = (F() & PF) != 0;
|
2017-06-14 21:33:02 +00:00
|
|
|
if (again) // See LDI
|
2017-06-12 13:33:00 +00:00
|
|
|
MEMPTR().word = pc.word - 1;
|
|
|
|
return again;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-12 13:33:00 +00:00
|
|
|
bool EightBit::Z80::lddr() {
|
2017-06-04 20:38:34 +00:00
|
|
|
ldd();
|
2017-06-12 13:33:00 +00:00
|
|
|
auto again = (F() & PF) != 0;
|
2017-06-14 21:33:02 +00:00
|
|
|
if (again) // See LDR
|
2017-06-12 13:33:00 +00:00
|
|
|
MEMPTR().word = pc.word - 1;
|
|
|
|
return again;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion Block load instructions
|
|
|
|
|
|
|
|
#pragma region Block input instructions
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::ini() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-07 21:54:55 +00:00
|
|
|
MEMPTR() = m_memory.ADDRESS() = BC();
|
|
|
|
MEMPTR().word++;
|
2017-06-04 20:38:34 +00:00
|
|
|
readPort();
|
|
|
|
auto value = m_memory.DATA();
|
|
|
|
m_memory.ADDRESS().word = HL().word++;
|
|
|
|
m_memory.reference() = value;
|
2017-06-18 17:14:39 +00:00
|
|
|
postDecrement(f, --B());
|
|
|
|
setFlag(f, NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::ind() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-07 21:54:55 +00:00
|
|
|
MEMPTR() = m_memory.ADDRESS() = BC();
|
|
|
|
MEMPTR().word--;
|
2017-06-04 20:38:34 +00:00
|
|
|
readPort();
|
|
|
|
auto value = m_memory.DATA();
|
|
|
|
m_memory.ADDRESS().word = HL().word--;
|
|
|
|
m_memory.reference() = value;
|
2017-06-18 17:14:39 +00:00
|
|
|
postDecrement(f, --B());
|
|
|
|
setFlag(f, NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-12 13:33:00 +00:00
|
|
|
bool EightBit::Z80::inir() {
|
2017-06-04 20:38:34 +00:00
|
|
|
ini();
|
2017-06-14 21:33:02 +00:00
|
|
|
return !(F() & ZF); // See INI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-12 13:33:00 +00:00
|
|
|
bool EightBit::Z80::indr() {
|
2017-06-04 20:38:34 +00:00
|
|
|
ind();
|
2017-06-14 21:33:02 +00:00
|
|
|
return !(F() & ZF); // See IND
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion Block input instructions
|
|
|
|
|
|
|
|
#pragma region Block output instructions
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::blockOut() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
auto value = m_memory.reference();
|
|
|
|
m_memory.ADDRESS().word = BC().word;
|
|
|
|
writePort();
|
2017-06-18 17:14:39 +00:00
|
|
|
postDecrement(f, --B());
|
|
|
|
setFlag(f, NF, value & Bit7);
|
|
|
|
setFlag(f, HC | CF, (L() + value) > 0xff);
|
|
|
|
adjustParity(f, ((value + L()) & 7) ^ B());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::outi() {
|
2017-06-04 20:38:34 +00:00
|
|
|
m_memory.ADDRESS().word = HL().word++;
|
|
|
|
blockOut();
|
|
|
|
MEMPTR().word = BC().word + 1;
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::outd() {
|
2017-06-04 20:38:34 +00:00
|
|
|
m_memory.ADDRESS().word = HL().word--;
|
|
|
|
blockOut();
|
|
|
|
MEMPTR().word = BC().word - 1;
|
|
|
|
}
|
|
|
|
|
2017-06-12 13:33:00 +00:00
|
|
|
bool EightBit::Z80::otir() {
|
2017-06-04 20:38:34 +00:00
|
|
|
outi();
|
2017-06-14 21:33:02 +00:00
|
|
|
return !(F() & ZF); // See OUTI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-12 13:33:00 +00:00
|
|
|
bool EightBit::Z80::otdr() {
|
2017-06-04 20:38:34 +00:00
|
|
|
outd();
|
2017-06-14 21:33:02 +00:00
|
|
|
return !(F() & ZF); // See OUTD
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion Block output instructions
|
|
|
|
|
|
|
|
#pragma endregion Block instructions
|
|
|
|
|
|
|
|
#pragma region Nibble rotation
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::rrd() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-12 13:33:00 +00:00
|
|
|
MEMPTR() = HL();
|
2017-06-15 21:21:26 +00:00
|
|
|
auto memory = memptrReference();
|
|
|
|
m_memory.reference() = promoteNibble(A()) | highNibble(memory);
|
|
|
|
A() = (A() & 0xf0) | lowNibble(memory);
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZPXY(f, A());
|
|
|
|
clearFlag(f, NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::rld() {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-12 13:33:00 +00:00
|
|
|
MEMPTR() = HL();
|
2017-06-15 21:21:26 +00:00
|
|
|
auto memory = memptrReference();
|
|
|
|
m_memory.reference() = promoteNibble(memory) | lowNibble(A());
|
|
|
|
A() = (A() & 0xf0) | highNibble(memory);
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZPXY(f, A());
|
|
|
|
clearFlag(f, NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#pragma endregion Nibble rotation
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
int EightBit::Z80::step() {
|
2017-06-04 20:38:34 +00:00
|
|
|
ExecutingInstruction.fire(*this);
|
2017-06-15 21:21:26 +00:00
|
|
|
m_displaced = m_prefixCB = m_prefixDD = m_prefixED = m_prefixFD = false;
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles = 0;
|
|
|
|
return fetchExecute();
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
int EightBit::Z80::execute(uint8_t opcode) {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
|
|
|
if (!getM1())
|
|
|
|
throw std::logic_error("M1 cannot be high");
|
|
|
|
|
|
|
|
auto x = (opcode & 0b11000000) >> 6;
|
|
|
|
auto y = (opcode & 0b111000) >> 3;
|
|
|
|
auto z = (opcode & 0b111);
|
|
|
|
|
|
|
|
auto p = (y & 0b110) >> 1;
|
|
|
|
auto q = (y & 1);
|
|
|
|
|
2017-06-15 21:21:26 +00:00
|
|
|
if (!(m_prefixCB && m_displaced)) {
|
2017-06-04 20:38:34 +00:00
|
|
|
incrementRefresh();
|
|
|
|
M1() = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (m_prefixCB)
|
|
|
|
executeCB(x, y, z, p, q);
|
|
|
|
else if (m_prefixED)
|
|
|
|
executeED(x, y, z, p, q);
|
|
|
|
else
|
|
|
|
executeOther(x, y, z, p, q);
|
|
|
|
|
|
|
|
if (cycles == 0)
|
|
|
|
throw std::logic_error("Unhandled opcode");
|
|
|
|
|
|
|
|
return cycles;
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::executeCB(int x, int y, int z, int p, int q) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0: // rot[y] r[z]
|
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZP(f, m_displaced ? R2(z) = rlc(DISPLACED()) : rlc(R(z)));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZP(f, m_displaced ? R2(z) = rrc(DISPLACED()) : rrc(R(z)));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZP(f, m_displaced ? R2(z) = rl(DISPLACED()) : rl(R(z)));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZP(f, m_displaced ? R2(z) = rr(DISPLACED()) : rr(R(z)));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZP(f, m_displaced ? R2(z) = sla(DISPLACED()) : sla(R(z)));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZP(f, m_displaced ? R2(z) = sra(DISPLACED()) : sra(R(z)));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6:
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZP(f, m_displaced ? R2(z) = sll(DISPLACED()) : sll(R(z)));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7:
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZP(f, m_displaced ? R2(z) = srl(DISPLACED()) : srl(R(z)));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
2017-06-15 21:21:26 +00:00
|
|
|
if (m_displaced) {
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 23;
|
|
|
|
} else {
|
|
|
|
cycles += 8;
|
|
|
|
if (z == 6)
|
|
|
|
cycles += 7;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // BIT y, r[z]
|
2017-06-15 21:21:26 +00:00
|
|
|
if (m_displaced) {
|
2017-06-04 20:38:34 +00:00
|
|
|
bit(y, DISPLACED());
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustXY(f, MEMPTR().high);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 20;
|
|
|
|
} else {
|
|
|
|
auto operand = R(z);
|
|
|
|
bit(y, operand);
|
|
|
|
cycles += 8;
|
|
|
|
if (z == 6) {
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustXY(f, MEMPTR().high);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 4;
|
|
|
|
} else {
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustXY(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // RES y, r[z]
|
2017-06-15 21:21:26 +00:00
|
|
|
if (m_displaced) {
|
2017-06-04 20:38:34 +00:00
|
|
|
res(y, DISPLACED());
|
|
|
|
R2(z) = DISPLACED();
|
|
|
|
cycles += 23;
|
|
|
|
} else {
|
|
|
|
res(y, R(z));
|
|
|
|
cycles += 8;
|
|
|
|
if (z == 6)
|
|
|
|
cycles += 7;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // SET y, r[z]
|
2017-06-15 21:21:26 +00:00
|
|
|
if (m_displaced) {
|
2017-06-04 20:38:34 +00:00
|
|
|
set(y, DISPLACED());
|
|
|
|
R2(z) = DISPLACED();
|
|
|
|
cycles += 23;
|
|
|
|
} else {
|
|
|
|
set(y, R(z));
|
|
|
|
cycles += 8;
|
|
|
|
if (z == 6)
|
|
|
|
cycles += 7;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::executeED(int x, int y, int z, int p, int q) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0:
|
|
|
|
case 3: // Invalid instruction, equivalent to NONI followed by NOP
|
|
|
|
cycles += 8;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Input from port with 16-bit address
|
|
|
|
MEMPTR() = m_memory.ADDRESS() = BC();
|
2017-06-07 21:54:55 +00:00
|
|
|
MEMPTR().word++;
|
2017-06-04 20:38:34 +00:00
|
|
|
readPort();
|
|
|
|
if (y != 6) // IN r[y],(C)
|
|
|
|
R(y) = m_memory.DATA();
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZPXY(f, m_memory.DATA());
|
|
|
|
clearFlag(f, NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 12;
|
|
|
|
break;
|
|
|
|
case 1: // Output to port with 16-bit address
|
|
|
|
MEMPTR() = m_memory.ADDRESS() = BC();
|
2017-06-07 21:54:55 +00:00
|
|
|
MEMPTR().word++;
|
2017-06-04 20:38:34 +00:00
|
|
|
if (y == 6) // OUT (C),0
|
|
|
|
m_memory.placeDATA(0);
|
|
|
|
else // OUT (C),r[y]
|
|
|
|
m_memory.placeDATA(R(y));
|
|
|
|
writePort();
|
|
|
|
cycles += 12;
|
|
|
|
break;
|
|
|
|
case 2: // 16-bit add/subtract with carry
|
|
|
|
switch (q) {
|
|
|
|
case 0: // SBC HL, rp[p]
|
2017-06-15 21:21:26 +00:00
|
|
|
sbcViaMemptr(HL2(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC HL, rp[p]
|
2017-06-15 21:21:26 +00:00
|
|
|
adcViaMemptr(HL2(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 15;
|
|
|
|
break;
|
|
|
|
case 3: // Retrieve/store register pair from/to immediate address
|
|
|
|
switch (q) {
|
|
|
|
case 0: // LD (nn), rp[p]
|
2017-06-07 21:54:55 +00:00
|
|
|
fetchWord();
|
|
|
|
setWordViaMemptr(RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD rp[p], (nn)
|
2017-06-07 21:54:55 +00:00
|
|
|
fetchWord();
|
|
|
|
getWordViaMemptr(RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 20;
|
|
|
|
break;
|
|
|
|
case 4: // Negate accumulator
|
|
|
|
neg();
|
|
|
|
cycles += 8;
|
|
|
|
break;
|
|
|
|
case 5: // Return from interrupt
|
|
|
|
switch (y) {
|
|
|
|
case 1:
|
|
|
|
reti(); // RETI
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
retn(); // RETN
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 14;
|
|
|
|
break;
|
|
|
|
case 6: // Set interrupt mode
|
|
|
|
switch (y) {
|
|
|
|
case 0:
|
|
|
|
case 4:
|
|
|
|
IM() = 0;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
case 6:
|
|
|
|
IM() = 1;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
case 7:
|
|
|
|
IM() = 2;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
case 5:
|
|
|
|
IM() = 0;
|
|
|
|
}
|
|
|
|
cycles += 8;
|
|
|
|
break;
|
|
|
|
case 7: // Assorted ops
|
|
|
|
switch (y) {
|
|
|
|
case 0: // LD I,A
|
|
|
|
IV() = A();
|
|
|
|
cycles += 9;
|
|
|
|
break;
|
|
|
|
case 1: // LD R,A
|
|
|
|
REFRESH() = A();
|
|
|
|
cycles += 9;
|
|
|
|
break;
|
|
|
|
case 2: // LD A,I
|
|
|
|
A() = IV();
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZXY(f, A());
|
|
|
|
setFlag(f, PF, IFF2());
|
|
|
|
clearFlag(f, NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 9;
|
|
|
|
break;
|
|
|
|
case 3: // LD A,R
|
|
|
|
A() = REFRESH();
|
2017-06-18 17:14:39 +00:00
|
|
|
adjustSZXY(f, A());
|
|
|
|
clearFlag(f, NF | HC);
|
|
|
|
setFlag(f, PF, IFF2());
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 9;
|
|
|
|
break;
|
|
|
|
case 4: // RRD
|
|
|
|
rrd();
|
|
|
|
cycles += 18;
|
|
|
|
break;
|
|
|
|
case 5: // RLD
|
|
|
|
rld();
|
|
|
|
cycles += 18;
|
|
|
|
break;
|
|
|
|
case 6: // NOP
|
|
|
|
case 7: // NOP
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // LD
|
|
|
|
switch (y) {
|
|
|
|
case 4: // LDI
|
|
|
|
ldi();
|
|
|
|
break;
|
|
|
|
case 5: // LDD
|
|
|
|
ldd();
|
|
|
|
break;
|
|
|
|
case 6: // LDIR
|
2017-06-14 21:33:02 +00:00
|
|
|
if (ldir()) {
|
|
|
|
pc.word -= 2;
|
2017-06-12 13:33:00 +00:00
|
|
|
cycles += 5;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // LDDR
|
2017-06-14 21:33:02 +00:00
|
|
|
if (lddr()) {
|
|
|
|
pc.word -= 2;
|
2017-06-12 13:33:00 +00:00
|
|
|
cycles += 5;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // CP
|
|
|
|
switch (y) {
|
|
|
|
case 4: // CPI
|
|
|
|
cpi();
|
|
|
|
break;
|
|
|
|
case 5: // CPD
|
|
|
|
cpd();
|
|
|
|
break;
|
|
|
|
case 6: // CPIR
|
2017-06-14 21:33:02 +00:00
|
|
|
if (cpir()) {
|
|
|
|
pc.word -= 2;
|
2017-06-12 13:33:00 +00:00
|
|
|
cycles += 5;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CPDR
|
2017-06-14 21:33:02 +00:00
|
|
|
if (cpdr()) {
|
|
|
|
pc.word -= 2;
|
2017-06-12 13:33:00 +00:00
|
|
|
cycles += 5;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // IN
|
|
|
|
switch (y) {
|
|
|
|
case 4: // INI
|
|
|
|
ini();
|
|
|
|
break;
|
|
|
|
case 5: // IND
|
|
|
|
ind();
|
|
|
|
break;
|
|
|
|
case 6: // INIR
|
2017-06-14 21:33:02 +00:00
|
|
|
if (inir()) {
|
|
|
|
pc.word -= 2;
|
2017-06-12 13:33:00 +00:00
|
|
|
cycles += 5;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // INDR
|
2017-06-14 21:33:02 +00:00
|
|
|
if (indr()) {
|
|
|
|
pc.word -= 2;
|
2017-06-12 13:33:00 +00:00
|
|
|
cycles += 5;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // OUT
|
|
|
|
switch (y) {
|
|
|
|
case 4: // OUTI
|
|
|
|
outi();
|
|
|
|
break;
|
|
|
|
case 5: // OUTD
|
|
|
|
outd();
|
|
|
|
break;
|
|
|
|
case 6: // OTIR
|
2017-06-14 21:33:02 +00:00
|
|
|
if (otir()) {
|
|
|
|
pc.word -= 2;
|
2017-06-12 13:33:00 +00:00
|
|
|
cycles += 5;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // OTDR
|
2017-06-14 21:33:02 +00:00
|
|
|
if (otdr()) {
|
|
|
|
pc.word -= 2;
|
2017-06-12 13:33:00 +00:00
|
|
|
cycles += 5;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 16;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
void EightBit::Z80::executeOther(int x, int y, int z, int p, int q) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Relative jumps and assorted ops
|
|
|
|
switch (y) {
|
|
|
|
case 0: // NOP
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 1: // EX AF AF'
|
|
|
|
exxAF();
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 2: // DJNZ d
|
2017-06-11 20:08:40 +00:00
|
|
|
if (jrConditional(--B()))
|
|
|
|
cycles += 5;
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 8;
|
|
|
|
break;
|
|
|
|
case 3: // JR d
|
2017-06-11 20:08:40 +00:00
|
|
|
jr(fetchByte());
|
|
|
|
cycles += 12;
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
default: // JR cc,d
|
2017-06-11 20:08:40 +00:00
|
|
|
if (jrConditionalFlag(y - 4))
|
|
|
|
cycles += 5;
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 5;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // 16-bit load immediate/add
|
|
|
|
switch (q) {
|
2017-06-07 21:54:55 +00:00
|
|
|
case 0: // LD rp,nn
|
|
|
|
Processor::fetchWord(RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 10;
|
|
|
|
break;
|
|
|
|
case 1: // ADD HL,rp
|
2017-06-15 21:21:26 +00:00
|
|
|
addViaMemptr(HL2(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 11;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // Indirect loading
|
|
|
|
switch (q) {
|
|
|
|
case 0:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // LD (BC),A
|
2017-06-07 21:54:55 +00:00
|
|
|
MEMPTR() = BC();
|
2017-06-15 21:21:26 +00:00
|
|
|
MEMPTR().high = memptrReference() = A();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 7;
|
|
|
|
break;
|
|
|
|
case 1: // LD (DE),A
|
2017-06-07 21:54:55 +00:00
|
|
|
MEMPTR() = DE();
|
2017-06-15 21:21:26 +00:00
|
|
|
MEMPTR().high = memptrReference() = A();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 7;
|
|
|
|
break;
|
|
|
|
case 2: // LD (nn),HL
|
2017-06-07 21:54:55 +00:00
|
|
|
fetchWord();
|
2017-06-15 21:21:26 +00:00
|
|
|
setWordViaMemptr(HL2());
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 16;
|
|
|
|
break;
|
|
|
|
case 3: // LD (nn),A
|
2017-06-07 21:54:55 +00:00
|
|
|
fetchWord();
|
2017-06-15 21:21:26 +00:00
|
|
|
MEMPTR().high = memptrReference() = A();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 13;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // LD A,(BC)
|
2017-06-07 21:54:55 +00:00
|
|
|
MEMPTR() = BC();
|
2017-06-15 21:21:26 +00:00
|
|
|
A() = memptrReference();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 7;
|
|
|
|
break;
|
|
|
|
case 1: // LD A,(DE)
|
2017-06-07 21:54:55 +00:00
|
|
|
MEMPTR() = DE();
|
2017-06-15 21:21:26 +00:00
|
|
|
A() = memptrReference();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 7;
|
|
|
|
break;
|
|
|
|
case 2: // LD HL,(nn)
|
2017-06-07 21:54:55 +00:00
|
|
|
fetchWord();
|
2017-06-15 21:21:26 +00:00
|
|
|
getWordViaMemptr(HL2());
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 16;
|
|
|
|
break;
|
|
|
|
case 3: // LD A,(nn)
|
2017-06-07 21:54:55 +00:00
|
|
|
fetchWord();
|
2017-06-15 21:21:26 +00:00
|
|
|
A() = memptrReference();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 13;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // 16-bit INC/DEC
|
|
|
|
switch (q) {
|
|
|
|
case 0: // INC rp
|
|
|
|
++RP(p).word;
|
|
|
|
break;
|
|
|
|
case 1: // DEC rp
|
|
|
|
--RP(p).word;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 6;
|
|
|
|
break;
|
|
|
|
case 4: // 8-bit INC
|
2017-06-18 17:14:39 +00:00
|
|
|
postIncrement(f, ++R(y)); // INC r
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 5: // 8-bit DEC
|
2017-06-18 17:14:39 +00:00
|
|
|
postDecrement(f, --R(y)); // DEC r
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 4;
|
|
|
|
if (y == 6)
|
|
|
|
cycles += 7;
|
|
|
|
break;
|
2017-06-15 21:21:26 +00:00
|
|
|
case 6: // 8-bit load immediate
|
2017-06-11 20:08:40 +00:00
|
|
|
R(y) = fetchByte(); // LD r,n
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 7;
|
|
|
|
if (y == 6)
|
|
|
|
cycles += 3;
|
|
|
|
break;
|
2017-06-15 21:21:26 +00:00
|
|
|
case 7: // Assorted operations on accumulator/flags
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2017-06-15 21:21:26 +00:00
|
|
|
rlc(A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2017-06-15 21:21:26 +00:00
|
|
|
rrc(A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2017-06-15 21:21:26 +00:00
|
|
|
rl(A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
2017-06-15 21:21:26 +00:00
|
|
|
rr(A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
daa();
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
cpl();
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
scf();
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
ccf();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // 8-bit loading
|
|
|
|
if (z == 6 && y == 6) { // Exception (replaces LD (HL), (HL))
|
|
|
|
halt();
|
|
|
|
} else {
|
|
|
|
bool normal = true;
|
2017-06-15 21:21:26 +00:00
|
|
|
if (m_displaced) {
|
2017-06-04 20:38:34 +00:00
|
|
|
if (z == 6) {
|
|
|
|
switch (y) {
|
|
|
|
case 4:
|
|
|
|
H() = R(z);
|
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
L() = R(z);
|
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (y == 6) {
|
|
|
|
switch (z) {
|
|
|
|
case 4:
|
|
|
|
R(y) = H();
|
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
R(y) = L();
|
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (normal)
|
|
|
|
R(y) = R(z);
|
|
|
|
if ((y == 6) || (z == 6)) // M operations
|
|
|
|
cycles += 3;
|
|
|
|
}
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 2: // Operate on accumulator and register/memory location
|
|
|
|
switch (y) {
|
|
|
|
case 0: // ADD A,r
|
|
|
|
add(A(), R(z));
|
|
|
|
break;
|
|
|
|
case 1: // ADC A,r
|
|
|
|
adc(A(), R(z));
|
|
|
|
break;
|
|
|
|
case 2: // SUB r
|
|
|
|
sub(A(), R(z));
|
|
|
|
break;
|
|
|
|
case 3: // SBC A,r
|
|
|
|
sbc(A(), R(z));
|
|
|
|
break;
|
|
|
|
case 4: // AND r
|
|
|
|
andr(A(), R(z));
|
|
|
|
break;
|
|
|
|
case 5: // XOR r
|
|
|
|
xorr(A(), R(z));
|
|
|
|
break;
|
|
|
|
case 6: // OR r
|
|
|
|
orr(A(), R(z));
|
|
|
|
break;
|
|
|
|
case 7: // CP r
|
|
|
|
compare(R(z));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 4;
|
|
|
|
if (z == 6)
|
|
|
|
cycles += 3;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Conditional return
|
2017-06-11 20:08:40 +00:00
|
|
|
if (returnConditionalFlag(y))
|
|
|
|
cycles += 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 5;
|
|
|
|
break;
|
|
|
|
case 1: // POP & various ops
|
|
|
|
switch (q) {
|
|
|
|
case 0: // POP rp2[p]
|
2017-06-07 21:54:55 +00:00
|
|
|
popWord(RP2(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 10;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // RET
|
|
|
|
ret();
|
|
|
|
cycles += 10;
|
|
|
|
break;
|
|
|
|
case 1: // EXX
|
|
|
|
exx();
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 2: // JP HL
|
2017-06-15 21:21:26 +00:00
|
|
|
pc = HL2();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 3: // LD SP,HL
|
2017-06-15 21:21:26 +00:00
|
|
|
sp = HL2();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // Conditional jump
|
|
|
|
jumpConditionalFlag(y);
|
|
|
|
cycles += 10;
|
|
|
|
break;
|
|
|
|
case 3: // Assorted operations
|
|
|
|
switch (y) {
|
|
|
|
case 0: // JP nn
|
2017-06-07 21:54:55 +00:00
|
|
|
fetchWord();
|
2017-06-11 20:08:40 +00:00
|
|
|
jump();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 10;
|
|
|
|
break;
|
|
|
|
case 1: // CB prefix
|
|
|
|
m_prefixCB = true;
|
2017-06-15 21:21:26 +00:00
|
|
|
if (m_displaced)
|
2017-06-11 20:08:40 +00:00
|
|
|
m_displacement = fetchByte();
|
2017-06-04 20:38:34 +00:00
|
|
|
fetchExecute();
|
|
|
|
break;
|
|
|
|
case 2: // OUT (n),A
|
2017-06-11 20:08:40 +00:00
|
|
|
m_memory.ADDRESS().low = fetchByte();
|
2017-06-04 20:38:34 +00:00
|
|
|
m_memory.ADDRESS().high = A();
|
|
|
|
MEMPTR() = m_memory.ADDRESS();
|
|
|
|
m_memory.placeDATA(A());
|
|
|
|
writePort();
|
|
|
|
MEMPTR().low++;
|
|
|
|
cycles += 11;
|
|
|
|
break;
|
|
|
|
case 3: // IN A,(n)
|
2017-06-11 20:08:40 +00:00
|
|
|
m_memory.ADDRESS().low = fetchByte();
|
2017-06-04 20:38:34 +00:00
|
|
|
m_memory.ADDRESS().high = A();
|
|
|
|
MEMPTR() = m_memory.ADDRESS();
|
|
|
|
readPort();
|
|
|
|
A() = m_memory.DATA();
|
|
|
|
MEMPTR().low++;
|
|
|
|
cycles += 11;
|
|
|
|
break;
|
|
|
|
case 4: // EX (SP),HL
|
|
|
|
xhtl();
|
|
|
|
cycles += 19;
|
|
|
|
break;
|
|
|
|
case 5: // EX DE,HL
|
|
|
|
std::swap(DE(), HL());
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 6: // DI
|
2017-06-11 20:08:40 +00:00
|
|
|
di();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 7: // EI
|
2017-06-11 20:08:40 +00:00
|
|
|
ei();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 4: // Conditional call: CALL cc[y], nn
|
2017-06-11 20:08:40 +00:00
|
|
|
if (callConditionalFlag(y))
|
|
|
|
cycles += 7;
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 10;
|
|
|
|
break;
|
|
|
|
case 5: // PUSH & various ops
|
|
|
|
switch (q) {
|
|
|
|
case 0: // PUSH rp2[p]
|
|
|
|
pushWord(RP2(p));
|
|
|
|
cycles += 11;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // CALL nn
|
2017-06-07 21:54:55 +00:00
|
|
|
fetchWord();
|
|
|
|
call();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 17;
|
|
|
|
break;
|
|
|
|
case 1: // DD prefix
|
2017-06-15 21:21:26 +00:00
|
|
|
m_displaced = m_prefixDD = true;
|
2017-06-04 20:38:34 +00:00
|
|
|
fetchExecute();
|
|
|
|
break;
|
|
|
|
case 2: // ED prefix
|
|
|
|
m_prefixED = true;
|
|
|
|
fetchExecute();
|
|
|
|
break;
|
|
|
|
case 3: // FD prefix
|
2017-06-15 21:21:26 +00:00
|
|
|
m_displaced = m_prefixFD = true;
|
2017-06-04 20:38:34 +00:00
|
|
|
fetchExecute();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 6: // Operate on accumulator and immediate operand: alu[y] n
|
|
|
|
switch (y) {
|
|
|
|
case 0: // ADD A,n
|
2017-06-11 20:08:40 +00:00
|
|
|
add(A(), fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC A,n
|
2017-06-11 20:08:40 +00:00
|
|
|
adc(A(), fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // SUB n
|
2017-06-11 20:08:40 +00:00
|
|
|
sub(A(), fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SBC A,n
|
2017-06-11 20:08:40 +00:00
|
|
|
sbc(A(), fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // AND n
|
2017-06-11 20:08:40 +00:00
|
|
|
andr(A(), fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // XOR n
|
2017-06-11 20:08:40 +00:00
|
|
|
xorr(A(), fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OR n
|
2017-06-11 20:08:40 +00:00
|
|
|
orr(A(), fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CP n
|
2017-06-11 20:08:40 +00:00
|
|
|
compare(fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 7;
|
|
|
|
break;
|
|
|
|
case 7: // Restart: RST y * 8
|
|
|
|
restart(y << 3);
|
|
|
|
cycles += 11;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|