2017-06-04 20:38:34 +00:00
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#include "stdafx.h"
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#include "Z80.h"
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// based on http://www.z80.info/decoding.htm
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2017-08-30 22:17:34 +00:00
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2017-09-07 00:04:09 +00:00
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EightBit::Z80::Z80(Bus& bus, InputOutput& ports)
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: IntelProcessor(bus),
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2017-11-10 22:41:50 +00:00
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m_ports(ports) {
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2019-09-06 22:55:57 +00:00
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RaisedPOWER.connect([this](EventArgs) {
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raiseM1();
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di();
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IM() = 0;
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REFRESH() = 0;
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IV() = Mask8;
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AF() = IX() = IY() = BC() = DE() = HL() = Mask16;
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exxAF();
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exx();
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m_prefixCB = m_prefixDD = m_prefixED = m_prefixFD = false;
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});
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2019-09-14 14:04:46 +00:00
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LoweredM1.connect([this](EventArgs) {
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++REFRESH();
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});
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2017-06-04 20:38:34 +00:00
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}
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2019-01-14 23:17:54 +00:00
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DEFINE_PIN_LEVEL_CHANGERS(NMI, Z80);
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DEFINE_PIN_LEVEL_CHANGERS(M1, Z80);
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2017-11-05 14:48:15 +00:00
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EightBit::register16_t& EightBit::Z80::AF() {
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return m_accumulatorFlags[m_accumulatorFlagsSet];
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}
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EightBit::register16_t& EightBit::Z80::BC() {
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return m_registers[m_registerSet][BC_IDX];
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}
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EightBit::register16_t& EightBit::Z80::DE() {
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return m_registers[m_registerSet][DE_IDX];
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}
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EightBit::register16_t& EightBit::Z80::HL() {
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return m_registers[m_registerSet][HL_IDX];
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}
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2018-08-25 00:34:30 +00:00
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void EightBit::Z80::handleRESET() {
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2018-10-27 17:41:55 +00:00
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IntelProcessor::handleRESET();
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2018-08-25 00:34:30 +00:00
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di();
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2019-01-09 23:24:33 +00:00
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tick(3);
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2018-08-25 00:34:30 +00:00
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}
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void EightBit::Z80::handleNMI() {
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2019-01-14 02:10:17 +00:00
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raiseNMI();
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2019-08-29 07:51:15 +00:00
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raiseHALT();
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2018-08-25 00:34:30 +00:00
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IFF1() = false;
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restart(0x66);
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2019-01-09 23:24:33 +00:00
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tick(13);
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2018-08-25 00:34:30 +00:00
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}
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void EightBit::Z80::handleINT() {
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2018-10-27 17:41:55 +00:00
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IntelProcessor::handleINT();
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2019-09-08 15:28:19 +00:00
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di();
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switch (IM()) {
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case 0: // i8080 equivalent
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execute(BUS().DATA());
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break;
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case 1:
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restart(7 << 3);
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tick(13);
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break;
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case 2:
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call(MEMPTR() = register16_t(BUS().DATA(), IV()));
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tick(19);
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break;
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default:
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UNREACHABLE;
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2018-08-25 00:34:30 +00:00
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}
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}
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2017-06-11 20:08:40 +00:00
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void EightBit::Z80::di() {
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2017-06-04 20:38:34 +00:00
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IFF1() = IFF2() = false;
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}
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2017-06-11 20:08:40 +00:00
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void EightBit::Z80::ei() {
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2017-06-04 20:38:34 +00:00
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IFF1() = IFF2() = true;
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}
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2018-11-29 00:09:40 +00:00
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uint8_t EightBit::Z80::increment(const uint8_t operand) {
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2018-06-10 23:50:46 +00:00
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clearFlag(F(), NF);
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2018-11-29 00:09:40 +00:00
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const uint8_t result = operand + 1;
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adjustSZXY<Z80>(F(), result);
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setFlag(F(), VF, result == Bit7);
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clearFlag(F(), HC, lowNibble(result));
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2018-11-29 00:09:40 +00:00
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uint8_t EightBit::Z80::decrement(const uint8_t operand) {
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2018-06-10 23:50:46 +00:00
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setFlag(F(), NF);
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clearFlag(F(), HC, lowNibble(operand));
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2018-11-29 00:09:40 +00:00
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const uint8_t result = operand - 1;
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adjustSZXY<Z80>(F(), result);
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setFlag(F(), VF, result == Mask7);
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2018-06-10 23:50:46 +00:00
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bool EightBit::Z80::jrConditionalFlag(const int flag) {
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2018-03-10 01:53:57 +00:00
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ASSUME(flag >= 0);
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ASSUME(flag <= 3);
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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case 0: // NZ
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2018-06-10 23:50:46 +00:00
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return jrConditional(!(F() & ZF));
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2017-06-04 20:38:34 +00:00
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case 1: // Z
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2018-06-10 23:50:46 +00:00
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return jrConditional(F() & ZF);
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2017-06-04 20:38:34 +00:00
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case 2: // NC
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2018-06-10 23:50:46 +00:00
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return jrConditional(!(F() & CF));
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2017-06-04 20:38:34 +00:00
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case 3: // C
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2018-06-10 23:50:46 +00:00
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return jrConditional(F() & CF);
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2017-07-02 16:38:19 +00:00
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default:
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2017-10-29 18:47:23 +00:00
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UNREACHABLE;
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2017-06-04 20:38:34 +00:00
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}
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}
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2018-06-10 23:50:46 +00:00
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bool EightBit::Z80::jumpConditionalFlag(const int flag) {
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2018-03-10 01:53:57 +00:00
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ASSUME(flag >= 0);
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ASSUME(flag <= 7);
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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case 0: // NZ
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2018-06-10 23:50:46 +00:00
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return jumpConditional(!(F() & ZF));
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2017-06-04 20:38:34 +00:00
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case 1: // Z
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2018-06-10 23:50:46 +00:00
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return jumpConditional(F() & ZF);
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2017-06-04 20:38:34 +00:00
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case 2: // NC
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2018-06-10 23:50:46 +00:00
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return jumpConditional(!(F() & CF));
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2017-06-04 20:38:34 +00:00
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case 3: // C
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2018-06-10 23:50:46 +00:00
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return jumpConditional(F() & CF);
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2017-06-04 20:38:34 +00:00
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case 4: // PO
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2018-06-10 23:50:46 +00:00
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return jumpConditional(!(F() & PF));
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2017-06-04 20:38:34 +00:00
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case 5: // PE
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2018-06-10 23:50:46 +00:00
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return jumpConditional(F() & PF);
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2017-06-04 20:38:34 +00:00
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case 6: // P
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2018-06-10 23:50:46 +00:00
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return jumpConditional(!(F() & SF));
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2017-06-04 20:38:34 +00:00
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case 7: // M
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2018-06-10 23:50:46 +00:00
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return jumpConditional(F() & SF);
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2017-07-02 16:38:19 +00:00
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default:
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2017-10-29 18:47:23 +00:00
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UNREACHABLE;
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2017-06-04 20:38:34 +00:00
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}
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}
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2017-06-05 21:39:15 +00:00
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void EightBit::Z80::retn() {
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2017-06-04 20:38:34 +00:00
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ret();
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IFF1() = IFF2();
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}
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2017-06-05 21:39:15 +00:00
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void EightBit::Z80::reti() {
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2017-06-04 20:38:34 +00:00
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retn();
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}
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2018-06-10 23:50:46 +00:00
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bool EightBit::Z80::returnConditionalFlag(const int flag) {
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2018-03-10 01:53:57 +00:00
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ASSUME(flag >= 0);
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ASSUME(flag <= 7);
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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case 0: // NZ
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2018-06-10 23:50:46 +00:00
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return returnConditional(!(F() & ZF));
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2017-06-04 20:38:34 +00:00
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case 1: // Z
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2018-06-10 23:50:46 +00:00
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return returnConditional(F() & ZF);
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2017-06-04 20:38:34 +00:00
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case 2: // NC
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2018-06-10 23:50:46 +00:00
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return returnConditional(!(F() & CF));
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2017-06-04 20:38:34 +00:00
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case 3: // C
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2018-06-10 23:50:46 +00:00
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return returnConditional(F() & CF);
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2017-06-04 20:38:34 +00:00
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case 4: // PO
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2018-06-10 23:50:46 +00:00
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return returnConditional(!(F() & PF));
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2017-06-04 20:38:34 +00:00
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case 5: // PE
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2018-06-10 23:50:46 +00:00
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return returnConditional(F() & PF);
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2017-06-04 20:38:34 +00:00
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case 6: // P
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2018-06-10 23:50:46 +00:00
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return returnConditional(!(F() & SF));
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2017-06-04 20:38:34 +00:00
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case 7: // M
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2018-06-10 23:50:46 +00:00
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return returnConditional(F() & SF);
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2017-07-02 16:38:19 +00:00
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default:
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2017-10-29 18:47:23 +00:00
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UNREACHABLE;
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2017-06-04 20:38:34 +00:00
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}
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}
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2018-06-10 23:50:46 +00:00
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bool EightBit::Z80::callConditionalFlag(const int flag) {
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2018-03-10 01:53:57 +00:00
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ASSUME(flag >= 0);
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ASSUME(flag <= 7);
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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case 0: // NZ
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2018-06-10 23:50:46 +00:00
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return callConditional(!(F() & ZF));
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2017-06-04 20:38:34 +00:00
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case 1: // Z
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2018-06-10 23:50:46 +00:00
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return callConditional(F() & ZF);
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2017-06-04 20:38:34 +00:00
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case 2: // NC
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2018-06-10 23:50:46 +00:00
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return callConditional(!(F() & CF));
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2017-06-04 20:38:34 +00:00
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case 3: // C
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2018-06-10 23:50:46 +00:00
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return callConditional(F() & CF);
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2017-06-04 20:38:34 +00:00
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case 4: // PO
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2018-06-10 23:50:46 +00:00
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return callConditional(!(F() & PF));
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2017-06-04 20:38:34 +00:00
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case 5: // PE
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2018-06-10 23:50:46 +00:00
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return callConditional(F() & PF);
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2017-06-04 20:38:34 +00:00
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case 6: // P
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2018-06-10 23:50:46 +00:00
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return callConditional(!(F() & SF));
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2017-06-04 20:38:34 +00:00
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case 7: // M
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2018-06-10 23:50:46 +00:00
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return callConditional(F() & SF);
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2017-07-02 16:38:19 +00:00
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default:
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2017-10-29 18:47:23 +00:00
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UNREACHABLE;
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2017-06-04 20:38:34 +00:00
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}
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}
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2019-09-14 14:04:46 +00:00
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EightBit::register16_t EightBit::Z80::sbc(const register16_t operand, const register16_t value) {
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2017-06-18 17:14:39 +00:00
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2019-09-14 14:04:46 +00:00
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const auto subtraction = operand.word - value.word - (F() & CF);
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2017-06-04 20:38:34 +00:00
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2019-09-14 14:04:46 +00:00
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const register16_t result = subtraction;
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2017-06-04 20:38:34 +00:00
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2019-09-14 14:04:46 +00:00
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setFlag(F(), NF);
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clearFlag(F(), ZF, result.word);
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setFlag(F(), CF, subtraction & Bit16);
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adjustHalfCarrySub(F(), operand.high, value.high, result.high);
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adjustXY<Z80>(F(), result.high);
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2017-06-04 20:38:34 +00:00
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2019-09-14 14:04:46 +00:00
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const auto beforeNegative = operand.high & SF;
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const auto valueNegative = value.high & SF;
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const auto afterNegative = result.high & SF;
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2017-06-04 20:38:34 +00:00
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2018-06-10 23:50:46 +00:00
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setFlag(F(), SF, afterNegative);
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adjustOverflowSub(F(), beforeNegative, valueNegative, afterNegative);
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2017-07-03 20:42:18 +00:00
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2019-09-14 14:04:46 +00:00
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MEMPTR() = operand + 1;
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2019-09-14 14:04:46 +00:00
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EightBit::register16_t EightBit::Z80::adc(const register16_t operand, const register16_t value) {
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2017-06-18 17:14:39 +00:00
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2019-09-14 14:04:46 +00:00
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const auto result = add(operand, value, F() & CF);
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clearFlag(F(), ZF, result.word);
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2017-06-04 20:38:34 +00:00
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2019-09-14 14:04:46 +00:00
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const auto beforeNegative = operand.high & SF;
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2017-06-26 22:22:32 +00:00
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const auto valueNegative = value.high & SF;
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2019-09-14 14:04:46 +00:00
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const auto afterNegative = result.high & SF;
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2017-06-04 20:38:34 +00:00
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2018-06-10 23:50:46 +00:00
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setFlag(F(), SF, afterNegative);
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adjustOverflowAdd(F(), beforeNegative, valueNegative, afterNegative);
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2017-07-03 20:42:18 +00:00
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2019-09-14 14:04:46 +00:00
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2019-09-14 14:04:46 +00:00
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EightBit::register16_t EightBit::Z80::add(const register16_t operand, const register16_t value, int carry) {
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2017-06-18 17:14:39 +00:00
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2019-09-14 14:04:46 +00:00
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const int addition = operand.word + value.word + carry;
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const register16_t result = addition;
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2017-06-04 20:38:34 +00:00
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2018-06-10 23:50:46 +00:00
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clearFlag(F(), NF);
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2019-09-14 14:04:46 +00:00
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setFlag(F(), CF, addition & Bit16);
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adjustHalfCarryAdd(F(), operand.high, value.high, result.high);
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adjustXY<Z80>(F(), result.high);
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2017-07-03 20:42:18 +00:00
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2019-09-14 14:04:46 +00:00
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MEMPTR() = operand + 1;
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2019-09-14 14:04:46 +00:00
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uint8_t EightBit::Z80::add(const uint8_t operand, const uint8_t value, const int carry) {
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2017-06-18 17:14:39 +00:00
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2019-09-14 14:04:46 +00:00
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const register16_t addition = operand + value + carry;
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const auto result = addition.low;
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2017-06-04 20:38:34 +00:00
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2019-09-14 14:04:46 +00:00
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adjustHalfCarryAdd(F(), operand, value, result);
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adjustOverflowAdd(F(), operand, value, result);
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2017-06-04 20:38:34 +00:00
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2018-06-10 23:50:46 +00:00
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clearFlag(F(), NF);
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2019-09-14 14:04:46 +00:00
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setFlag(F(), CF, addition.high & CF);
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adjustSZXY<Z80>(F(), result);
|
|
|
|
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-09-14 14:04:46 +00:00
|
|
|
uint8_t EightBit::Z80::adc(const uint8_t operand, const uint8_t value) {
|
|
|
|
return add(operand, value, F() & CF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::subtract(const uint8_t operand, const uint8_t value, const int carry) {
|
2017-06-18 17:14:39 +00:00
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
const register16_t subtraction = operand - value - carry;
|
|
|
|
const auto result = subtraction.low;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
adjustHalfCarrySub(F(), operand, value, result);
|
|
|
|
adjustOverflowSub(F(), operand, value, result);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
setFlag(F(), NF);
|
2018-11-29 00:09:40 +00:00
|
|
|
setFlag(F(), CF, subtraction.high & CF);
|
|
|
|
adjustSZ<Z80>(F(), result);
|
|
|
|
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-09-14 14:04:46 +00:00
|
|
|
uint8_t EightBit::Z80::sub(const uint8_t operand, const uint8_t value, const int carry) {
|
|
|
|
const auto subtraction = subtract(operand, value, carry);
|
|
|
|
adjustXY<Z80>(F(), subtraction);
|
|
|
|
return subtraction;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-09-14 14:04:46 +00:00
|
|
|
uint8_t EightBit::Z80::sbc(const uint8_t operand, const uint8_t value) {
|
|
|
|
return sub(operand, value, F() & CF);
|
2017-06-26 22:22:32 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::andr(const uint8_t value) {
|
|
|
|
setFlag(F(), HC);
|
|
|
|
clearFlag(F(), CF | NF);
|
|
|
|
adjustSZPXY<Z80>(F(), A() &= value);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::xorr(const uint8_t value) {
|
|
|
|
clearFlag(F(), HC | CF | NF);
|
|
|
|
adjustSZPXY<Z80>(F(), A() ^= value);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::orr(const uint8_t value) {
|
|
|
|
clearFlag(F(), HC | CF | NF);
|
|
|
|
adjustSZPXY<Z80>(F(), A() |= value);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::compare(const uint8_t value) {
|
2018-11-29 00:09:40 +00:00
|
|
|
subtract(A(), value);
|
2018-06-10 23:50:46 +00:00
|
|
|
adjustXY<Z80>(F(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::rlc(const uint8_t operand) {
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
2017-10-29 20:15:49 +00:00
|
|
|
const auto carry = operand & Bit7;
|
2018-06-10 23:50:46 +00:00
|
|
|
setFlag(F(), CF, carry);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand << 1) | (carry >> 7);
|
|
|
|
adjustXY<Z80>(F(), result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::rrc(const uint8_t operand) {
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
2017-10-29 20:15:49 +00:00
|
|
|
const auto carry = operand & Bit0;
|
2018-06-10 23:50:46 +00:00
|
|
|
setFlag(F(), CF, carry);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand >> 1) | (carry << 7);
|
|
|
|
adjustXY<Z80>(F(), result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::rl(const uint8_t operand) {
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
|
|
|
const auto carry = F() & CF;
|
|
|
|
setFlag(F(), CF, operand & Bit7);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand << 1) | carry;
|
|
|
|
adjustXY<Z80>(F(), result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::rr(const uint8_t operand) {
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
|
|
|
const auto carry = F() & CF;
|
|
|
|
setFlag(F(), CF, operand & Bit0);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand >> 1) | (carry << 7);
|
|
|
|
adjustXY<Z80>(F(), result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::sla(const uint8_t operand) {
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
|
|
|
setFlag(F(), CF, operand & Bit7);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = operand << 1;
|
|
|
|
adjustXY<Z80>(F(), result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::sra(const uint8_t operand) {
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
|
|
|
setFlag(F(), CF, operand & Bit0);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand >> 1) | (operand & Bit7);
|
|
|
|
adjustXY<Z80>(F(), result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::sll(const uint8_t operand) {
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
|
|
|
setFlag(F(), CF, operand & Bit7);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand << 1) | Bit0;
|
|
|
|
adjustXY<Z80>(F(), result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
uint8_t EightBit::Z80::srl(const uint8_t operand) {
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
|
|
|
setFlag(F(), CF, operand & Bit0);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand >> 1) & ~Bit7;
|
|
|
|
adjustXY<Z80>(F(), result);
|
|
|
|
setFlag(F(), ZF, result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-12-01 13:01:33 +00:00
|
|
|
void EightBit::Z80::bit(const int n, const uint8_t operand) {
|
2018-03-10 01:53:57 +00:00
|
|
|
ASSUME(n >= 0);
|
|
|
|
ASSUME(n <= 7);
|
2018-06-10 23:50:46 +00:00
|
|
|
setFlag(F(), HC);
|
|
|
|
clearFlag(F(), NF);
|
2017-07-02 16:38:19 +00:00
|
|
|
const auto discarded = operand & (1 << n);
|
2018-12-01 13:01:33 +00:00
|
|
|
adjustSZ<Z80>(F(), discarded);
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), PF, discarded);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-04-14 08:39:06 +00:00
|
|
|
uint8_t EightBit::Z80::res(const int n, const uint8_t operand) {
|
2018-03-10 01:53:57 +00:00
|
|
|
ASSUME(n >= 0);
|
|
|
|
ASSUME(n <= 7);
|
2017-08-06 16:06:48 +00:00
|
|
|
return operand & ~(1 << n);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-04-14 08:39:06 +00:00
|
|
|
uint8_t EightBit::Z80::set(const int n, const uint8_t operand) {
|
2018-03-10 01:53:57 +00:00
|
|
|
ASSUME(n >= 0);
|
|
|
|
ASSUME(n <= 7);
|
2017-08-06 16:06:48 +00:00
|
|
|
return operand | (1 << n);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::neg() {
|
2017-06-28 14:39:31 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
setFlag(F(), PF, A() == Bit7);
|
|
|
|
setFlag(F(), CF, A());
|
|
|
|
setFlag(F(), NF);
|
2017-06-28 14:39:31 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
const auto original = A();
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
A() = (~A() + 1); // two's complement
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
adjustHalfCarrySub(F(), 0U, original, A());
|
|
|
|
adjustOverflowSub(F(), 0U, original, A());
|
2017-06-28 14:39:31 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
adjustSZXY<Z80>(F(), A());
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::daa() {
|
2017-06-18 17:14:39 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
auto updated = A();
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
const auto lowAdjust = (F() & HC) || (lowNibble(A()) > 9);
|
|
|
|
const auto highAdjust = (F() & CF) || (A() > 0x99);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
if (F() & NF) {
|
2017-06-04 20:38:34 +00:00
|
|
|
if (lowAdjust)
|
2017-06-28 14:39:31 +00:00
|
|
|
updated -= 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
if (highAdjust)
|
2017-06-28 14:39:31 +00:00
|
|
|
updated -= 0x60;
|
2017-06-04 20:38:34 +00:00
|
|
|
} else {
|
|
|
|
if (lowAdjust)
|
2017-06-28 14:39:31 +00:00
|
|
|
updated += 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
if (highAdjust)
|
2017-06-28 14:39:31 +00:00
|
|
|
updated += 0x60;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
F() = (F() & (CF | NF)) | (A() > 0x99 ? CF : 0) | ((A() ^ updated) & HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
adjustSZPXY<Z80>(F(), A() = updated);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::cpl() {
|
|
|
|
setFlag(F(), HC | NF);
|
|
|
|
adjustXY<Z80>(F(), A() = ~A());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::scf() {
|
|
|
|
setFlag(F(), CF);
|
|
|
|
clearFlag(F(), HC | NF);
|
|
|
|
adjustXY<Z80>(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::ccf() {
|
|
|
|
clearFlag(F(), NF);
|
|
|
|
const auto carry = F() & CF;
|
|
|
|
setFlag(F(), HC, carry);
|
|
|
|
clearFlag(F(), CF, carry);
|
|
|
|
adjustXY<Z80>(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-08-16 20:56:48 +00:00
|
|
|
void EightBit::Z80::xhtl(register16_t& exchange) {
|
2019-03-02 21:58:34 +00:00
|
|
|
MEMPTR().low = busRead(SP());
|
2018-08-11 20:19:19 +00:00
|
|
|
++BUS().ADDRESS();
|
2019-03-02 21:58:34 +00:00
|
|
|
MEMPTR().high = busRead();
|
2019-08-16 20:56:48 +00:00
|
|
|
busWrite(exchange.high);
|
|
|
|
exchange.high = MEMPTR().high;
|
|
|
|
--BUS().ADDRESS();
|
|
|
|
busWrite(exchange.low);
|
|
|
|
exchange.low = MEMPTR().low;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-09-20 23:16:00 +00:00
|
|
|
void EightBit::Z80::blockCompare(const register16_t source, register16_t& counter) {
|
2017-06-18 17:14:39 +00:00
|
|
|
|
2019-03-02 21:58:34 +00:00
|
|
|
const auto value = busRead(source);
|
2018-06-10 23:50:46 +00:00
|
|
|
uint8_t result = A() - value;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-08-11 20:19:19 +00:00
|
|
|
setFlag(F(), PF, --counter.word);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
adjustSZ<Z80>(F(), result);
|
|
|
|
adjustHalfCarrySub(F(), A(), value, result);
|
|
|
|
setFlag(F(), NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
result -= ((F() & HC) >> 4);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
setFlag(F(), YF, result & Bit1);
|
|
|
|
setFlag(F(), XF, result & Bit3);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::cpi() {
|
2018-08-11 20:19:19 +00:00
|
|
|
blockCompare(HL()++, BC());
|
|
|
|
++MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::cpd() {
|
2018-08-11 20:19:19 +00:00
|
|
|
blockCompare(HL()--, BC());
|
|
|
|
--MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::cpir() {
|
|
|
|
cpi();
|
|
|
|
return (F() & PF) && !(F() & ZF); // See CPI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::cpdr() {
|
|
|
|
cpd();
|
|
|
|
return (F() & PF) && !(F() & ZF); // See CPD
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-08-11 20:19:19 +00:00
|
|
|
void EightBit::Z80::blockLoad(const register16_t source, const register16_t destination, register16_t& counter) {
|
2019-03-02 21:58:34 +00:00
|
|
|
const auto value = busRead(source);
|
|
|
|
busWrite(destination, value);
|
2018-06-10 23:50:46 +00:00
|
|
|
const auto xy = A() + value;
|
2018-11-28 21:27:14 +00:00
|
|
|
setFlag(F(), XF, xy & Bit3);
|
|
|
|
setFlag(F(), YF, xy & Bit1);
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
2018-08-11 20:19:19 +00:00
|
|
|
setFlag(F(), PF, --counter.word);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::ldd() {
|
2018-08-11 20:19:19 +00:00
|
|
|
blockLoad(HL()--, DE()--, BC());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::ldi() {
|
2018-08-11 20:19:19 +00:00
|
|
|
blockLoad(HL()++, DE()++, BC());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::ldir() {
|
|
|
|
ldi();
|
|
|
|
return !!(F() & PF); // See LDI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::lddr() {
|
|
|
|
ldd();
|
|
|
|
return !!(F() & PF); // See LDD
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-09-20 23:16:00 +00:00
|
|
|
void EightBit::Z80::blockIn(register16_t& source, const register16_t destination) {
|
2018-08-12 15:25:30 +00:00
|
|
|
MEMPTR() = BUS().ADDRESS() = source;
|
2018-06-10 23:50:46 +00:00
|
|
|
const auto value = readPort();
|
2019-03-02 21:58:34 +00:00
|
|
|
busWrite(destination, value);
|
2018-11-29 00:09:40 +00:00
|
|
|
source.high = decrement(source.high);
|
2018-06-10 23:50:46 +00:00
|
|
|
setFlag(F(), NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-08-12 15:25:30 +00:00
|
|
|
void EightBit::Z80::ini() {
|
|
|
|
blockIn(BC(), HL()++);
|
|
|
|
++MEMPTR();
|
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::ind() {
|
2018-08-12 15:25:30 +00:00
|
|
|
blockIn(BC(), HL()--);
|
2018-08-11 20:19:19 +00:00
|
|
|
--MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::inir() {
|
|
|
|
ini();
|
|
|
|
return !(F() & ZF); // See INI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::indr() {
|
|
|
|
ind();
|
|
|
|
return !(F() & ZF); // See IND
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-08-12 15:25:30 +00:00
|
|
|
void EightBit::Z80::blockOut(const register16_t source, register16_t& destination) {
|
2019-03-02 21:58:34 +00:00
|
|
|
const auto value = busRead(source);
|
2019-08-16 20:56:48 +00:00
|
|
|
destination.high = decrement(destination.high);
|
2018-08-12 15:25:30 +00:00
|
|
|
BUS().ADDRESS() = destination;
|
2017-06-04 20:38:34 +00:00
|
|
|
writePort();
|
2018-08-12 15:25:30 +00:00
|
|
|
MEMPTR() = destination;
|
2018-06-10 23:50:46 +00:00
|
|
|
setFlag(F(), NF, value & Bit7);
|
|
|
|
setFlag(F(), HC | CF, (L() + value) > 0xff);
|
2018-11-28 21:27:14 +00:00
|
|
|
adjustParity<Z80>(F(), ((value + L()) & Mask3) ^ B());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::outi() {
|
2018-08-12 15:25:30 +00:00
|
|
|
blockOut(HL()++, BC());
|
|
|
|
++MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::outd() {
|
2018-08-12 15:25:30 +00:00
|
|
|
blockOut(HL()--, BC());
|
|
|
|
--MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::otir() {
|
|
|
|
outi();
|
|
|
|
return !(F() & ZF); // See OUTI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::otdr() {
|
|
|
|
outd();
|
|
|
|
return !(F() & ZF); // See OUTD
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::rrd() {
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = HL())++;
|
2019-03-02 21:58:34 +00:00
|
|
|
const auto memory = busRead();
|
|
|
|
busWrite(promoteNibble(A()) | highNibble(memory));
|
2018-06-10 23:50:46 +00:00
|
|
|
A() = higherNibble(A()) | lowerNibble(memory);
|
|
|
|
adjustSZPXY<Z80>(F(), A());
|
|
|
|
clearFlag(F(), NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::rld() {
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = HL())++;
|
2019-03-02 21:58:34 +00:00
|
|
|
const auto memory = busRead();
|
|
|
|
busWrite(promoteNibble(memory) | lowNibble(A()));
|
2018-06-10 23:50:46 +00:00
|
|
|
A() = higherNibble(A()) | highNibble(memory);
|
|
|
|
adjustSZPXY<Z80>(F(), A());
|
|
|
|
clearFlag(F(), NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::writePort(const uint8_t port) {
|
2019-01-06 11:27:43 +00:00
|
|
|
MEMPTR() = BUS().ADDRESS() = register16_t(port, A());
|
2018-06-10 23:50:46 +00:00
|
|
|
BUS().DATA() = A();
|
2017-06-28 14:39:31 +00:00
|
|
|
writePort();
|
2018-03-10 01:53:57 +00:00
|
|
|
++MEMPTR().low;
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void EightBit::Z80::writePort() {
|
2017-09-07 00:04:09 +00:00
|
|
|
m_ports.write(BUS().ADDRESS().low, BUS().DATA());
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
uint8_t EightBit::Z80::readPort(const uint8_t port) {
|
2019-01-06 11:27:43 +00:00
|
|
|
MEMPTR() = BUS().ADDRESS() = register16_t(port, A());
|
2018-03-10 01:53:57 +00:00
|
|
|
++MEMPTR().low;
|
2018-06-10 23:50:46 +00:00
|
|
|
return readPort();
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
uint8_t EightBit::Z80::readPort() {
|
|
|
|
return BUS().DATA() = m_ports.read(BUS().ADDRESS().low);
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
int EightBit::Z80::step() {
|
2017-11-03 22:05:01 +00:00
|
|
|
resetCycles();
|
2018-10-28 19:29:14 +00:00
|
|
|
ExecutingInstruction.fire(*this);
|
2017-12-03 00:57:47 +00:00
|
|
|
if (LIKELY(powered())) {
|
2018-10-28 19:29:14 +00:00
|
|
|
m_displaced = m_prefixCB = m_prefixDD = m_prefixED = m_prefixFD = false;
|
2019-09-08 15:28:19 +00:00
|
|
|
bool handled = false;
|
|
|
|
if (lowered(RESET())) {
|
2018-08-25 00:34:30 +00:00
|
|
|
handleRESET();
|
2019-09-08 15:28:19 +00:00
|
|
|
handled = true;
|
|
|
|
} else if (lowered(NMI())) {
|
2018-08-25 00:34:30 +00:00
|
|
|
handleNMI();
|
2019-09-08 15:28:19 +00:00
|
|
|
handled = true;
|
|
|
|
} else if (lowered(INT())) {
|
|
|
|
raiseHALT();
|
|
|
|
if (IFF1()) {
|
|
|
|
handleINT();
|
|
|
|
handled = true;
|
|
|
|
}
|
|
|
|
} else if (lowered(HALT())) {
|
2019-08-31 07:45:04 +00:00
|
|
|
execute(0); // NOP
|
2019-09-08 15:28:19 +00:00
|
|
|
handled = true;
|
2017-12-03 00:57:47 +00:00
|
|
|
}
|
2019-09-14 14:04:46 +00:00
|
|
|
if (!handled) {
|
|
|
|
lowerM1();
|
2019-09-08 15:28:19 +00:00
|
|
|
execute(fetchByte());
|
2019-09-14 14:04:46 +00:00
|
|
|
}
|
2017-12-03 00:57:47 +00:00
|
|
|
}
|
2018-08-25 00:34:30 +00:00
|
|
|
ExecutedInstruction.fire(*this);
|
2017-12-03 00:57:47 +00:00
|
|
|
return cycles();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-12-29 19:17:36 +00:00
|
|
|
int EightBit::Z80::execute() {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-09-14 14:04:46 +00:00
|
|
|
raiseM1();
|
2017-06-29 11:19:22 +00:00
|
|
|
|
2018-12-29 19:17:36 +00:00
|
|
|
const auto& decoded = getDecodedOpcode(opcode());
|
2017-06-26 22:22:32 +00:00
|
|
|
|
2017-11-18 14:29:30 +00:00
|
|
|
const auto x = decoded.x;
|
|
|
|
const auto y = decoded.y;
|
|
|
|
const auto z = decoded.z;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-11-18 14:29:30 +00:00
|
|
|
const auto p = decoded.p;
|
|
|
|
const auto q = decoded.q;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_prefixCB)
|
|
|
|
executeCB(x, y, z);
|
|
|
|
else if (m_prefixED)
|
|
|
|
executeED(x, y, z, p, q);
|
|
|
|
else
|
2018-06-10 23:50:46 +00:00
|
|
|
executeOther(x, y, z, p, q);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-03-10 01:53:57 +00:00
|
|
|
ASSUME(cycles() > 0);
|
2017-11-03 22:05:01 +00:00
|
|
|
return cycles();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::executeCB(const int x, const int y, const int z) {
|
2018-11-25 10:38:30 +00:00
|
|
|
const bool memoryY = y == 6;
|
|
|
|
const bool memoryZ = z == 6;
|
2018-12-01 13:01:33 +00:00
|
|
|
const bool indirect = (!m_displaced && memoryZ) || m_displaced;
|
2019-09-14 14:04:46 +00:00
|
|
|
auto operand = m_displaced ? busRead(displacedAddress()) : R(z);
|
2018-12-01 13:01:33 +00:00
|
|
|
const bool update = x != 1; // BIT does not update
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
2017-08-06 16:06:48 +00:00
|
|
|
case 0: { // rot[y] r[z]
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2018-11-29 00:09:40 +00:00
|
|
|
operand = rlc(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2018-11-29 00:09:40 +00:00
|
|
|
operand = rrc(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2018-11-29 00:09:40 +00:00
|
|
|
operand = rl(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
2018-11-29 00:09:40 +00:00
|
|
|
operand = rr(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2018-11-29 00:09:40 +00:00
|
|
|
operand = sla(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2018-11-29 00:09:40 +00:00
|
|
|
operand = sra(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6:
|
2018-11-29 00:09:40 +00:00
|
|
|
operand = sll(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7:
|
2018-11-29 00:09:40 +00:00
|
|
|
operand = srl(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-08-08 12:38:27 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2018-06-10 23:50:46 +00:00
|
|
|
adjustSZP<Z80>(F(), operand);
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(8);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-08-06 16:06:48 +00:00
|
|
|
} case 1: // BIT y, r[z]
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(8);
|
2018-12-01 13:01:33 +00:00
|
|
|
bit(y, operand);
|
2019-09-14 14:04:46 +00:00
|
|
|
if (indirect) {
|
2018-11-25 10:38:30 +00:00
|
|
|
adjustXY<Z80>(F(), MEMPTR().high);
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2019-09-14 14:04:46 +00:00
|
|
|
} else {
|
|
|
|
adjustXY<Z80>(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // RES y, r[z]
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(8);
|
2018-12-01 13:01:33 +00:00
|
|
|
operand = res(y, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SET y, r[z]
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(8);
|
2018-12-01 13:01:33 +00:00
|
|
|
operand = set(y, operand);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE;
|
|
|
|
}
|
2019-09-14 14:04:46 +00:00
|
|
|
if (update) {
|
|
|
|
if (m_displaced) {
|
2019-03-02 21:58:34 +00:00
|
|
|
busWrite(operand);
|
2019-09-14 14:04:46 +00:00
|
|
|
if (!memoryZ)
|
2019-08-16 20:56:48 +00:00
|
|
|
R2(z, operand);
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(15);
|
2019-09-14 14:04:46 +00:00
|
|
|
} else {
|
|
|
|
R(z, operand);
|
|
|
|
if (memoryZ)
|
|
|
|
tick(7);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::executeED(const int x, const int y, const int z, const int p, const int q) {
|
2018-11-25 10:38:30 +00:00
|
|
|
const bool memoryY = y == 6;
|
|
|
|
const bool memoryZ = z == 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0:
|
|
|
|
case 3: // Invalid instruction, equivalent to NONI followed by NOP
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(8);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Input from port with 16-bit address
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = BC())++;
|
2017-06-04 20:38:34 +00:00
|
|
|
readPort();
|
2019-09-14 14:04:46 +00:00
|
|
|
if (y != 6) // IN r[y],(C)
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, BUS().DATA());
|
|
|
|
adjustSZPXY<Z80>(F(), BUS().DATA());
|
|
|
|
clearFlag(F(), NF | HC);
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(12);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // Output to port with 16-bit address
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = BC())++;
|
2019-09-14 14:04:46 +00:00
|
|
|
if (y == 6) // OUT (C),0
|
2018-11-25 10:38:30 +00:00
|
|
|
BUS().DATA() = 0;
|
2019-09-14 14:04:46 +00:00
|
|
|
else // OUT (C),r[y]
|
|
|
|
BUS().DATA() = R(y);
|
2017-06-04 20:38:34 +00:00
|
|
|
writePort();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(12);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // 16-bit add/subtract with carry
|
|
|
|
switch (q) {
|
|
|
|
case 0: // SBC HL, rp[p]
|
2019-09-14 14:04:46 +00:00
|
|
|
HL2() = sbc(HL2(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC HL, rp[p]
|
2019-09-14 14:04:46 +00:00
|
|
|
HL2() = adc(HL2(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(15);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // Retrieve/store register pair from/to immediate address
|
2018-08-17 12:59:59 +00:00
|
|
|
BUS().ADDRESS() = fetchWord();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (q) {
|
2018-03-18 22:40:23 +00:00
|
|
|
case 0: // LD (nn), rp[p]
|
2018-01-10 23:08:14 +00:00
|
|
|
setWord(RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD rp[p], (nn)
|
2018-02-25 19:48:01 +00:00
|
|
|
RP(p) = getWord();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(20);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // Negate accumulator
|
2018-06-10 23:50:46 +00:00
|
|
|
neg();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(8);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // Return from interrupt
|
|
|
|
switch (y) {
|
|
|
|
case 1:
|
|
|
|
reti(); // RETI
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
retn(); // RETN
|
|
|
|
break;
|
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(14);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // Set interrupt mode
|
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2018-12-01 13:01:33 +00:00
|
|
|
case 1:
|
2017-06-04 20:38:34 +00:00
|
|
|
case 4:
|
2018-12-01 13:01:33 +00:00
|
|
|
case 5:
|
2017-06-04 20:38:34 +00:00
|
|
|
IM() = 0;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
case 6:
|
|
|
|
IM() = 1;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
case 7:
|
|
|
|
IM() = 2;
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(8);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // Assorted ops
|
|
|
|
switch (y) {
|
|
|
|
case 0: // LD I,A
|
2018-06-10 23:50:46 +00:00
|
|
|
IV() = A();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(9);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD R,A
|
2018-06-10 23:50:46 +00:00
|
|
|
REFRESH() = A();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(9);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // LD A,I
|
2018-06-16 09:09:28 +00:00
|
|
|
adjustSZXY<Z80>(F(), A() = IV());
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
|
|
|
setFlag(F(), PF, IFF2());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(9);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // LD A,R
|
2018-06-16 09:09:28 +00:00
|
|
|
adjustSZXY<Z80>(F(), A() = REFRESH());
|
2018-06-10 23:50:46 +00:00
|
|
|
clearFlag(F(), NF | HC);
|
|
|
|
setFlag(F(), PF, IFF2());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(9);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // RRD
|
2018-06-10 23:50:46 +00:00
|
|
|
rrd();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(18);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // RLD
|
2018-06-10 23:50:46 +00:00
|
|
|
rld();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(18);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // NOP
|
|
|
|
case 7: // NOP
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // LD
|
|
|
|
switch (y) {
|
|
|
|
case 4: // LDI
|
2018-06-10 23:50:46 +00:00
|
|
|
ldi();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // LDD
|
2018-06-10 23:50:46 +00:00
|
|
|
ldd();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // LDIR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (ldir()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
MEMPTR() = --PC();
|
|
|
|
--PC();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // LDDR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (lddr()) {
|
2018-08-17 12:59:59 +00:00
|
|
|
MEMPTR() = --PC();
|
2018-08-11 20:19:19 +00:00
|
|
|
--PC();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // CP
|
|
|
|
switch (y) {
|
|
|
|
case 4: // CPI
|
2018-06-10 23:50:46 +00:00
|
|
|
cpi();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // CPD
|
2018-06-10 23:50:46 +00:00
|
|
|
cpd();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // CPIR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (cpir()) {
|
2018-08-17 12:59:59 +00:00
|
|
|
MEMPTR() = --PC();
|
2018-08-11 20:19:19 +00:00
|
|
|
--PC();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CPDR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (cpdr()) {
|
2018-08-17 12:59:59 +00:00
|
|
|
MEMPTR() = --PC();
|
2018-08-11 20:19:19 +00:00
|
|
|
--PC();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2018-04-11 22:53:26 +00:00
|
|
|
} else {
|
2018-08-11 20:19:19 +00:00
|
|
|
MEMPTR() = PC() - 2;
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // IN
|
|
|
|
switch (y) {
|
|
|
|
case 4: // INI
|
2018-06-10 23:50:46 +00:00
|
|
|
ini();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // IND
|
2018-06-10 23:50:46 +00:00
|
|
|
ind();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // INIR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (inir()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
PC() -= 2;
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // INDR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (indr()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
PC() -= 2;
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // OUT
|
|
|
|
switch (y) {
|
|
|
|
case 4: // OUTI
|
2018-06-10 23:50:46 +00:00
|
|
|
outi();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // OUTD
|
2018-06-10 23:50:46 +00:00
|
|
|
outd();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OTIR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (otir()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
PC() -= 2;
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // OTDR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (otdr()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
PC() -= 2;
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(16);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::executeOther(const int x, const int y, const int z, const int p, const int q) {
|
2018-11-25 10:38:30 +00:00
|
|
|
const bool memoryY = y == 6;
|
|
|
|
const bool memoryZ = z == 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Relative jumps and assorted ops
|
|
|
|
switch (y) {
|
|
|
|
case 0: // NOP
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // EX AF AF'
|
|
|
|
exxAF();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // DJNZ d
|
2019-09-14 14:04:46 +00:00
|
|
|
if (jrConditional(--B()))
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
|
|
|
tick(8);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // JR d
|
2017-06-11 20:08:40 +00:00
|
|
|
jr(fetchByte());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(12);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-07-19 12:59:28 +00:00
|
|
|
case 4: // JR cc,d
|
|
|
|
case 5:
|
|
|
|
case 6:
|
|
|
|
case 7:
|
2019-09-14 14:04:46 +00:00
|
|
|
if (jrConditionalFlag(y - 4))
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
|
|
|
tick(5);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-07-19 12:59:28 +00:00
|
|
|
default:
|
2017-10-29 19:48:47 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // 16-bit load immediate/add
|
|
|
|
switch (q) {
|
2017-06-07 21:54:55 +00:00
|
|
|
case 0: // LD rp,nn
|
2018-02-25 19:48:01 +00:00
|
|
|
RP(p) = fetchWord();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(10);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADD HL,rp
|
2019-09-14 14:04:46 +00:00
|
|
|
HL2() = add(HL2(), RP(p));
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(11);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // Indirect loading
|
|
|
|
switch (q) {
|
|
|
|
case 0:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // LD (BC),A
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = BC())++;
|
2018-06-10 23:50:46 +00:00
|
|
|
MEMPTR().high = BUS().DATA() = A();
|
2019-03-02 21:58:34 +00:00
|
|
|
busWrite();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(7);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD (DE),A
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = DE())++;
|
2018-06-10 23:50:46 +00:00
|
|
|
MEMPTR().high = BUS().DATA() = A();
|
2019-03-02 21:58:34 +00:00
|
|
|
busWrite();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(7);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // LD (nn),HL
|
2018-08-17 12:59:59 +00:00
|
|
|
BUS().ADDRESS() = fetchWord();
|
2018-01-10 23:08:14 +00:00
|
|
|
setWord(HL2());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(16);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // LD (nn),A
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = fetchWord())++;
|
2018-06-10 23:50:46 +00:00
|
|
|
MEMPTR().high = BUS().DATA() = A();
|
2019-03-02 21:58:34 +00:00
|
|
|
busWrite();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(13);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // LD A,(BC)
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = BC())++;
|
2019-03-02 21:58:34 +00:00
|
|
|
A() = busRead();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(7);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD A,(DE)
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = DE())++;
|
2019-03-02 21:58:34 +00:00
|
|
|
A() = busRead();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(7);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // LD HL,(nn)
|
2018-08-17 12:59:59 +00:00
|
|
|
BUS().ADDRESS() = fetchWord();
|
2018-02-25 19:48:01 +00:00
|
|
|
HL2() = getWord();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(16);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // LD A,(nn)
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = fetchWord())++;
|
2019-03-02 21:58:34 +00:00
|
|
|
A() = busRead();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(13);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // 16-bit INC/DEC
|
|
|
|
switch (q) {
|
|
|
|
case 0: // INC rp
|
2018-08-11 20:19:19 +00:00
|
|
|
++RP(p);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // DEC rp
|
2018-08-11 20:19:19 +00:00
|
|
|
--RP(p);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(6);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2018-11-29 00:09:40 +00:00
|
|
|
case 4: // 8-bit INC
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_displaced && memoryY)
|
2017-08-06 16:06:48 +00:00
|
|
|
fetchDisplacement();
|
2018-11-29 00:09:40 +00:00
|
|
|
R(y, increment(R(y)));
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2018-11-29 00:09:40 +00:00
|
|
|
case 5: // 8-bit DEC
|
2019-09-14 14:04:46 +00:00
|
|
|
if (memoryY) {
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(7);
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_displaced)
|
2018-04-14 08:39:06 +00:00
|
|
|
fetchDisplacement();
|
|
|
|
}
|
2018-11-29 00:09:40 +00:00
|
|
|
R(y, decrement(R(y)));
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2018-11-29 00:09:40 +00:00
|
|
|
case 6: // 8-bit load immediate
|
2019-09-14 14:04:46 +00:00
|
|
|
if (memoryY) {
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(3);
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_displaced)
|
2018-04-14 08:39:06 +00:00
|
|
|
fetchDisplacement();
|
|
|
|
}
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, fetchByte()); // LD r,n
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(7);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-08-06 16:06:48 +00:00
|
|
|
case 7: // Assorted operations on accumulator/flags
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2018-11-29 00:09:40 +00:00
|
|
|
A() = rlc(A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2018-11-29 00:09:40 +00:00
|
|
|
A() = rrc(A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2018-11-29 00:09:40 +00:00
|
|
|
A() = rl(A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
2018-11-29 00:09:40 +00:00
|
|
|
A() = rr(A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2018-06-10 23:50:46 +00:00
|
|
|
daa();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2018-06-10 23:50:46 +00:00
|
|
|
cpl();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6:
|
2018-06-10 23:50:46 +00:00
|
|
|
scf();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7:
|
2018-06-10 23:50:46 +00:00
|
|
|
ccf();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // 8-bit loading
|
2019-09-14 14:04:46 +00:00
|
|
|
if ((memoryZ && memoryY)) { // Exception (replaces LD (HL), (HL))
|
|
|
|
lowerHALT();
|
|
|
|
} else {
|
2017-06-04 20:38:34 +00:00
|
|
|
bool normal = true;
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_displaced) {
|
|
|
|
if (memoryZ || memoryY)
|
2017-08-06 16:06:48 +00:00
|
|
|
fetchDisplacement();
|
2018-11-25 10:38:30 +00:00
|
|
|
if (memoryZ) {
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 4:
|
2018-06-10 23:50:46 +00:00
|
|
|
H() = R(z);
|
2017-06-04 20:38:34 +00:00
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
case 5:
|
2018-06-10 23:50:46 +00:00
|
|
|
L() = R(z);
|
2017-06-04 20:38:34 +00:00
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2018-11-25 10:38:30 +00:00
|
|
|
if (memoryY) {
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (z) {
|
|
|
|
case 4:
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, H());
|
2017-06-04 20:38:34 +00:00
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
case 5:
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, L());
|
2017-06-04 20:38:34 +00:00
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-09-14 14:04:46 +00:00
|
|
|
if (normal)
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, R(z));
|
2019-09-14 14:04:46 +00:00
|
|
|
if (memoryY || memoryZ) // M operations
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(3);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2018-06-16 09:09:28 +00:00
|
|
|
case 2: { // Operate on accumulator and register/memory location
|
2019-09-14 14:04:46 +00:00
|
|
|
if (memoryZ) {
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(3);
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_displaced)
|
2018-04-14 08:39:06 +00:00
|
|
|
fetchDisplacement();
|
|
|
|
}
|
2018-06-16 09:09:28 +00:00
|
|
|
const auto value = R(z);
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0: // ADD A,r
|
2019-09-14 14:04:46 +00:00
|
|
|
A() = add(A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC A,r
|
2019-09-14 14:04:46 +00:00
|
|
|
A() = adc(A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // SUB r
|
2019-09-14 14:04:46 +00:00
|
|
|
A() = sub(A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SBC A,r
|
2019-09-14 14:04:46 +00:00
|
|
|
A() = sbc(A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // AND r
|
2018-06-16 09:09:28 +00:00
|
|
|
andr(value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // XOR r
|
2018-06-16 09:09:28 +00:00
|
|
|
xorr(value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OR r
|
2018-06-16 09:09:28 +00:00
|
|
|
orr(value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CP r
|
2018-06-16 09:09:28 +00:00
|
|
|
compare(value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2018-06-16 09:09:28 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
case 3:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Conditional return
|
2019-09-14 14:04:46 +00:00
|
|
|
if (returnConditionalFlag(y))
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(6);
|
|
|
|
tick(5);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // POP & various ops
|
|
|
|
switch (q) {
|
|
|
|
case 0: // POP rp2[p]
|
2018-02-25 19:48:01 +00:00
|
|
|
RP2(p) = popWord();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(10);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // RET
|
|
|
|
ret();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(10);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // EXX
|
|
|
|
exx();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2019-09-08 20:27:35 +00:00
|
|
|
case 2: // JP (HL)
|
2018-04-11 22:53:26 +00:00
|
|
|
jump(HL2());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // LD SP,HL
|
2017-06-19 12:53:00 +00:00
|
|
|
SP() = HL2();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2017-06-29 20:25:58 +00:00
|
|
|
break;
|
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // Conditional jump
|
2018-06-10 23:50:46 +00:00
|
|
|
jumpConditionalFlag(y);
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(10);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // Assorted operations
|
|
|
|
switch (y) {
|
|
|
|
case 0: // JP nn
|
2018-03-18 22:40:23 +00:00
|
|
|
jump(MEMPTR() = fetchWord());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(10);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // CB prefix
|
|
|
|
m_prefixCB = true;
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_displaced)
|
2017-08-06 16:06:48 +00:00
|
|
|
fetchDisplacement();
|
2019-09-14 14:04:46 +00:00
|
|
|
else
|
|
|
|
lowerM1();
|
2019-08-31 07:45:04 +00:00
|
|
|
execute(fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // OUT (n),A
|
2018-06-10 23:50:46 +00:00
|
|
|
writePort(fetchByte());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(11);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // IN A,(n)
|
2018-06-10 23:50:46 +00:00
|
|
|
A() = readPort(fetchByte());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(11);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // EX (SP),HL
|
2019-08-16 20:56:48 +00:00
|
|
|
xhtl(HL2());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(19);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // EX DE,HL
|
|
|
|
std::swap(DE(), HL());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // DI
|
2017-06-11 20:08:40 +00:00
|
|
|
di();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // EI
|
2017-06-11 20:08:40 +00:00
|
|
|
ei();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 4: // Conditional call: CALL cc[y], nn
|
2019-09-14 14:04:46 +00:00
|
|
|
if (callConditionalFlag(y))
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(7);
|
|
|
|
tick(10);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // PUSH & various ops
|
|
|
|
switch (q) {
|
|
|
|
case 0: // PUSH rp2[p]
|
|
|
|
pushWord(RP2(p));
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(11);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // CALL nn
|
2018-03-18 22:40:23 +00:00
|
|
|
call(MEMPTR() = fetchWord());
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(17);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // DD prefix
|
2017-06-15 21:21:26 +00:00
|
|
|
m_displaced = m_prefixDD = true;
|
2019-01-14 02:10:17 +00:00
|
|
|
lowerM1();
|
2019-08-31 07:45:04 +00:00
|
|
|
execute(fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // ED prefix
|
|
|
|
m_prefixED = true;
|
2019-01-14 02:10:17 +00:00
|
|
|
lowerM1();
|
2019-08-31 07:45:04 +00:00
|
|
|
execute(fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // FD prefix
|
2017-06-15 21:21:26 +00:00
|
|
|
m_displaced = m_prefixFD = true;
|
2019-01-14 02:10:17 +00:00
|
|
|
lowerM1();
|
2019-08-31 07:45:04 +00:00
|
|
|
execute(fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2017-06-29 20:25:58 +00:00
|
|
|
break;
|
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2018-06-16 09:09:28 +00:00
|
|
|
case 6: { // Operate on accumulator and immediate operand: alu[y] n
|
|
|
|
const auto operand = fetchByte();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0: // ADD A,n
|
2019-09-14 14:04:46 +00:00
|
|
|
A() = add(A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC A,n
|
2019-09-14 14:04:46 +00:00
|
|
|
A() = adc(A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // SUB n
|
2019-09-14 14:04:46 +00:00
|
|
|
A() = sub(A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SBC A,n
|
2019-09-14 14:04:46 +00:00
|
|
|
A() = sbc(A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // AND n
|
2018-06-16 09:09:28 +00:00
|
|
|
andr(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // XOR n
|
2018-06-16 09:09:28 +00:00
|
|
|
xorr(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OR n
|
2018-06-16 09:09:28 +00:00
|
|
|
orr(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CP n
|
2018-06-16 09:09:28 +00:00
|
|
|
compare(operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(7);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2018-06-16 09:09:28 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
case 7: // Restart: RST y * 8
|
|
|
|
restart(y << 3);
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(11);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2017-08-30 22:17:34 +00:00
|
|
|
}
|