2017-06-04 20:38:34 +00:00
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#include "stdafx.h"
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#include "LR35902.h"
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// based on http://www.z80.info/decoding.htm
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// Half carry flag help from https://github.com/oubiwann/z80
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2017-06-09 10:42:32 +00:00
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EightBit::LR35902::LR35902(Bus& memory)
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2017-06-11 08:45:34 +00:00
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: IntelProcessor(memory),
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2017-07-17 23:13:41 +00:00
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m_bus(memory),
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2017-06-04 20:38:34 +00:00
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m_ime(false),
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m_prefixCB(false) {
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}
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2017-06-09 10:42:32 +00:00
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void EightBit::LR35902::reset() {
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2017-06-11 20:08:40 +00:00
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IntelProcessor::reset();
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2017-06-19 12:53:00 +00:00
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SP().word = 0xfffe;
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2017-06-04 20:38:34 +00:00
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di();
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}
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2017-06-09 10:42:32 +00:00
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void EightBit::LR35902::initialise() {
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2017-06-04 20:38:34 +00:00
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2017-06-11 20:08:40 +00:00
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IntelProcessor::initialise();
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2017-06-04 20:38:34 +00:00
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AF().word = 0xffff;
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2017-06-11 22:56:11 +00:00
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2017-06-04 20:38:34 +00:00
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BC().word = 0xffff;
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DE().word = 0xffff;
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HL().word = 0xffff;
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m_prefixCB = false;
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}
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2017-06-09 10:42:32 +00:00
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#pragma region Interrupt routines
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void EightBit::LR35902::di() {
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2017-06-04 20:38:34 +00:00
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IME() = false;
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}
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2017-06-09 10:42:32 +00:00
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void EightBit::LR35902::ei() {
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2017-06-04 20:38:34 +00:00
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IME() = true;
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}
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2017-06-09 10:42:32 +00:00
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int EightBit::LR35902::interrupt(uint8_t value) {
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cycles = 0;
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2017-06-04 20:38:34 +00:00
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di();
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restart(value);
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return 4;
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}
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2017-06-09 10:42:32 +00:00
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#pragma endregion Interrupt routines
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#pragma region Flag manipulation helpers
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2017-06-18 17:14:39 +00:00
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void EightBit::LR35902::postIncrement(uint8_t& f, uint8_t value) {
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, value);
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2017-06-18 17:14:39 +00:00
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clearFlag(f, NF);
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clearFlag(f, HC, lowNibble(value));
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2017-06-04 20:38:34 +00:00
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}
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2017-06-18 17:14:39 +00:00
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void EightBit::LR35902::postDecrement(uint8_t& f, uint8_t value) {
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, value);
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2017-06-18 17:14:39 +00:00
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setFlag(f, NF);
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clearFlag(f, HC, lowNibble(value + 1));
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2017-06-04 20:38:34 +00:00
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}
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2017-06-09 10:42:32 +00:00
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#pragma endregion Flag manipulation helpers
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#pragma region PC manipulation: call/ret/jp/jr
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2017-07-19 12:59:28 +00:00
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bool EightBit::LR35902::jrConditionalFlag(uint8_t& f, int flag) {
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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case 0: // NZ
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2017-07-19 12:59:28 +00:00
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return jrConditional(!(f & ZF));
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2017-06-04 20:38:34 +00:00
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case 1: // Z
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2017-07-19 12:59:28 +00:00
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return jrConditional(f & ZF);
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2017-06-04 20:38:34 +00:00
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case 2: // NC
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2017-07-19 12:59:28 +00:00
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return jrConditional(!(f & CF));
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2017-06-04 20:38:34 +00:00
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case 3: // C
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2017-07-19 12:59:28 +00:00
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return jrConditional(f & CF);
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2017-06-04 20:38:34 +00:00
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}
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2017-06-11 20:08:40 +00:00
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throw std::logic_error("Unhandled JR conditional");
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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bool EightBit::LR35902::jumpConditionalFlag(uint8_t& f, int flag) {
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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case 0: // NZ
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2017-07-19 12:59:28 +00:00
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return jumpConditional(!(f & ZF));
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2017-06-04 20:38:34 +00:00
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case 1: // Z
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2017-07-19 12:59:28 +00:00
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return jumpConditional(f & ZF);
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2017-06-04 20:38:34 +00:00
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case 2: // NC
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2017-07-19 12:59:28 +00:00
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return jumpConditional(!(f & CF));
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2017-06-04 20:38:34 +00:00
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case 3: // C
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2017-07-19 12:59:28 +00:00
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return jumpConditional(f & CF);
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2017-06-04 20:38:34 +00:00
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}
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2017-06-11 20:08:40 +00:00
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throw std::logic_error("Unhandled JP conditional");
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2017-06-04 20:38:34 +00:00
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}
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2017-06-09 10:42:32 +00:00
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void EightBit::LR35902::reti() {
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2017-06-04 20:38:34 +00:00
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ret();
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ei();
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}
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2017-07-19 12:59:28 +00:00
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bool EightBit::LR35902::returnConditionalFlag(uint8_t& f, int flag) {
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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case 0: // NZ
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2017-07-19 12:59:28 +00:00
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return returnConditional(!(f & ZF));
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2017-06-04 20:38:34 +00:00
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case 1: // Z
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2017-07-19 12:59:28 +00:00
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return returnConditional(f & ZF);
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2017-06-04 20:38:34 +00:00
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case 2: // NC
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2017-07-19 12:59:28 +00:00
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return returnConditional(!(f & CF));
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2017-06-04 20:38:34 +00:00
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case 3: // C
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2017-07-19 12:59:28 +00:00
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return returnConditional(f & CF);
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2017-06-04 20:38:34 +00:00
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}
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2017-06-11 20:08:40 +00:00
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throw std::logic_error("Unhandled RET conditional");
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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bool EightBit::LR35902::callConditionalFlag(uint8_t& f, int flag) {
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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case 0: // NZ
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2017-07-19 12:59:28 +00:00
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return callConditional(!(f & ZF));
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2017-06-04 20:38:34 +00:00
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case 1: // Z
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2017-07-19 12:59:28 +00:00
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return callConditional(f & ZF);
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2017-06-04 20:38:34 +00:00
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case 2: // NC
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2017-07-19 12:59:28 +00:00
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return callConditional(!(f & CF));
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2017-06-04 20:38:34 +00:00
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case 3: // C
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2017-07-19 12:59:28 +00:00
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return callConditional(f & CF);
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2017-06-04 20:38:34 +00:00
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}
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2017-06-11 20:08:40 +00:00
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throw std::logic_error("Unhandled CALL conditional");
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2017-06-04 20:38:34 +00:00
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}
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2017-06-09 10:42:32 +00:00
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#pragma endregion PC manipulation: call/ret/jp/jr
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#pragma region 16-bit arithmetic
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::sbc(uint8_t& f, register16_t& operand, register16_t value) {
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2017-06-04 20:38:34 +00:00
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2017-06-09 15:01:12 +00:00
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auto before = operand;
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2017-06-04 20:38:34 +00:00
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2017-07-19 22:16:17 +00:00
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auto carry = (f & CF) >> 4;
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auto result = before.word - value.word - carry;
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2017-06-09 15:01:12 +00:00
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operand.word = result;
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2017-06-04 20:38:34 +00:00
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2017-06-18 17:14:39 +00:00
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clearFlag(f, ZF, operand.word);
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adjustHalfCarrySub(f, before.high, value.high, operand.high);
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setFlag(f, NF);
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setFlag(f, CF, result & Bit16);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::adc(uint8_t& f, register16_t& operand, register16_t value) {
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2017-06-04 20:38:34 +00:00
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2017-06-09 15:01:12 +00:00
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auto before = operand;
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2017-06-04 20:38:34 +00:00
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2017-07-19 22:16:17 +00:00
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auto carry = (f & CF) >> 4;
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auto result = before.word + value.word + carry;
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2017-06-09 15:01:12 +00:00
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operand.word = result;
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2017-06-04 20:38:34 +00:00
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2017-06-18 17:14:39 +00:00
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clearFlag(f, ZF, result);
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adjustHalfCarryAdd(f, before.high, value.high, operand.high);
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clearFlag(f, NF);
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setFlag(f, CF, result & Bit16);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::add(uint8_t& f, register16_t& operand, register16_t value) {
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2017-06-04 20:38:34 +00:00
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2017-06-09 15:01:12 +00:00
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auto before = operand;
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2017-06-04 20:38:34 +00:00
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2017-06-09 15:01:12 +00:00
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auto result = before.word + value.word;
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2017-06-04 20:38:34 +00:00
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2017-06-09 15:01:12 +00:00
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operand.word = result;
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2017-06-04 20:38:34 +00:00
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2017-06-18 17:14:39 +00:00
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clearFlag(f, NF);
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setFlag(f, CF, result & Bit16);
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adjustHalfCarryAdd(f, before.high, value.high, operand.high);
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2017-06-04 20:38:34 +00:00
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}
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2017-06-09 10:42:32 +00:00
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#pragma endregion 16-bit arithmetic
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#pragma region ALU
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::add(uint8_t& f, uint8_t& operand, uint8_t value, int carry) {
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2017-06-18 17:14:39 +00:00
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2017-06-09 15:01:12 +00:00
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register16_t result;
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result.word = operand + value + carry;
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2017-06-04 20:38:34 +00:00
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2017-06-18 17:14:39 +00:00
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adjustHalfCarryAdd(f, operand, value, result.low);
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2017-06-04 20:38:34 +00:00
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2017-06-09 15:01:12 +00:00
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operand = result.low;
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2017-06-04 20:38:34 +00:00
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2017-06-18 17:14:39 +00:00
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clearFlag(f, NF);
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setFlag(f, CF, result.word & Bit8);
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, operand);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::adc(uint8_t& f, uint8_t& operand, uint8_t value) {
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2017-07-19 22:16:17 +00:00
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add(operand, value, (f & CF) >> 4);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::subtract(uint8_t& f, uint8_t& operand, uint8_t value, int carry) {
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2017-06-18 17:14:39 +00:00
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2017-06-09 15:01:12 +00:00
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register16_t result;
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result.word = operand - value - carry;
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2017-06-04 20:38:34 +00:00
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2017-06-18 17:14:39 +00:00
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adjustHalfCarrySub(f, operand, value, result.low);
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2017-06-04 20:38:34 +00:00
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2017-06-09 15:01:12 +00:00
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operand = result.low;
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2017-06-04 20:38:34 +00:00
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2017-06-18 17:14:39 +00:00
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setFlag(f, NF);
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setFlag(f, CF, result.word & Bit8);
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, operand);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::sbc(uint8_t& f, uint8_t& operand, uint8_t value) {
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2017-07-19 22:16:17 +00:00
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subtract(operand, value, (f & CF) >> 4);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::andr(uint8_t& f, uint8_t& operand, uint8_t value) {
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2017-06-09 15:01:12 +00:00
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operand &= value;
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2017-06-18 17:14:39 +00:00
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setFlag(f, HC);
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clearFlag(f, CF | NF);
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, operand);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::xorr(uint8_t& f, uint8_t& operand, uint8_t value) {
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2017-06-09 15:01:12 +00:00
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operand ^= value;
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2017-06-18 17:14:39 +00:00
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clearFlag(f, HC | CF | NF);
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, operand);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::orr(uint8_t& f, uint8_t& operand, uint8_t value) {
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2017-06-09 15:01:12 +00:00
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operand |= value;
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2017-06-18 17:14:39 +00:00
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clearFlag(f, HC | CF | NF);
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, operand);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::compare(uint8_t& f, uint8_t check, uint8_t value) {
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subtract(f, check, value);
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2017-06-04 20:38:34 +00:00
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}
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2017-06-09 10:42:32 +00:00
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#pragma endregion ALU
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#pragma region Shift and rotate
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2017-06-04 20:38:34 +00:00
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::rlc(uint8_t& f, uint8_t& operand) {
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2017-06-18 17:14:39 +00:00
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clearFlag(f, NF | HC);
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2017-07-19 12:59:28 +00:00
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setFlag(f, CF, operand & Bit7);
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operand = _rotl8(operand, 1);
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, operand);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::rrc(uint8_t& f, uint8_t& operand) {
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2017-06-18 17:14:39 +00:00
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clearFlag(f, NF | HC);
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2017-07-19 12:59:28 +00:00
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setFlag(f, CF, operand & Bit0);
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operand = _rotr8(operand, 1);
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2017-06-22 18:00:53 +00:00
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adjustZero<LR35902>(f, operand);
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2017-06-04 20:38:34 +00:00
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}
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2017-07-19 12:59:28 +00:00
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void EightBit::LR35902::rl(uint8_t& f, uint8_t& operand) {
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2017-06-18 17:14:39 +00:00
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clearFlag(f, NF | HC);
|
2017-07-19 22:16:17 +00:00
|
|
|
const auto carry = (f & CF) >> 4;
|
2017-07-19 12:59:28 +00:00
|
|
|
setFlag(f, CF, operand & Bit7);
|
|
|
|
operand = (operand << 1) | carry;
|
2017-06-22 18:00:53 +00:00
|
|
|
adjustZero<LR35902>(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::rr(uint8_t& f, uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, NF | HC);
|
2017-07-19 22:16:17 +00:00
|
|
|
const auto carry = (f & CF) >> 4;
|
2017-07-19 12:59:28 +00:00
|
|
|
setFlag(f, CF, operand & Bit0);
|
|
|
|
operand = (operand >> 1) | (carry << 7);
|
2017-06-22 18:00:53 +00:00
|
|
|
adjustZero<LR35902>(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::sla(uint8_t& f, uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, NF | HC);
|
2017-07-19 12:59:28 +00:00
|
|
|
setFlag(f, CF, operand & Bit7);
|
|
|
|
operand <<= 1;
|
2017-06-22 18:00:53 +00:00
|
|
|
adjustZero<LR35902>(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::sra(uint8_t& f, uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, NF | HC);
|
2017-07-19 12:59:28 +00:00
|
|
|
setFlag(f, CF, operand & Bit0);
|
|
|
|
operand = (operand >> 1) | operand & Bit7;
|
2017-06-22 18:00:53 +00:00
|
|
|
adjustZero<LR35902>(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::srl(uint8_t& f, uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, NF | HC);
|
2017-07-19 12:59:28 +00:00
|
|
|
setFlag(f, CF, operand & Bit0);
|
|
|
|
operand = (operand >> 1) & ~Bit7;
|
2017-06-22 18:00:53 +00:00
|
|
|
adjustZero<LR35902>(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
#pragma endregion Shift and rotate
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
#pragma region BIT/SET/RES
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::bit(uint8_t& f, int n, uint8_t& operand) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto carry = f & CF;
|
2017-06-04 20:38:34 +00:00
|
|
|
uint8_t discarded = operand;
|
2017-07-19 12:59:28 +00:00
|
|
|
andr(f, discarded, 1 << n);
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF, carry);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
void EightBit::LR35902::res(int n, uint8_t& operand) {
|
2017-06-04 20:38:34 +00:00
|
|
|
auto bit = 1 << n;
|
|
|
|
operand &= ~bit;
|
|
|
|
}
|
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
void EightBit::LR35902::set(int n, uint8_t& operand) {
|
2017-06-04 20:38:34 +00:00
|
|
|
auto bit = 1 << n;
|
|
|
|
operand |= bit;
|
|
|
|
}
|
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
#pragma endregion BIT/SET/RES
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
#pragma region Miscellaneous instructions
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::daa(uint8_t& a, uint8_t& f) {
|
2017-06-18 17:14:39 +00:00
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
auto updated = a;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
auto lowAdjust = (f & HC) | (lowNibble(a) > 9);
|
|
|
|
auto highAdjust = (f & CF) | (a > 0x99);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
if (f & NF) {
|
2017-06-04 20:38:34 +00:00
|
|
|
if (lowAdjust)
|
2017-07-19 12:59:28 +00:00
|
|
|
updated -= 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
if (highAdjust)
|
2017-07-19 12:59:28 +00:00
|
|
|
updated -= 0x60;
|
2017-06-04 20:38:34 +00:00
|
|
|
} else {
|
|
|
|
if (lowAdjust)
|
2017-07-19 12:59:28 +00:00
|
|
|
updated += 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
if (highAdjust)
|
2017-07-19 12:59:28 +00:00
|
|
|
updated += 0x60;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
f = (f & (CF | NF)) | (a > 0x99) | ((a ^ updated) & HC);
|
|
|
|
a = updated;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-06-22 18:00:53 +00:00
|
|
|
adjustZero<LR35902>(f, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::cpl(uint8_t& a, uint8_t& f) {
|
|
|
|
a = ~a;
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, HC | NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::scf(uint8_t& a, uint8_t& f) {
|
2017-06-18 17:14:39 +00:00
|
|
|
setFlag(f, CF);
|
|
|
|
clearFlag(f, HC | NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::ccf(uint8_t& a, uint8_t& f) {
|
2017-06-18 17:14:39 +00:00
|
|
|
auto carry = f & CF;
|
|
|
|
clearFlag(f, CF, carry);
|
|
|
|
clearFlag(f, NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-07-19 12:59:28 +00:00
|
|
|
void EightBit::LR35902::swap(uint8_t& f, uint8_t& operand) {
|
2017-06-04 20:38:34 +00:00
|
|
|
auto low = lowNibble(operand);
|
|
|
|
auto high = highNibble(operand);
|
|
|
|
operand = promoteNibble(low) | demoteNibble(high);
|
2017-06-22 18:00:53 +00:00
|
|
|
adjustZero<LR35902>(f, operand);
|
2017-06-18 17:14:39 +00:00
|
|
|
clearFlag(f, NF | HC | CF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
#pragma endregion Miscellaneous instructions
|
|
|
|
|
|
|
|
int EightBit::LR35902::step() {
|
2017-06-04 20:38:34 +00:00
|
|
|
ExecutingInstruction.fire(*this);
|
|
|
|
m_prefixCB = false;
|
2017-06-09 10:42:32 +00:00
|
|
|
cycles = 0;
|
2017-06-04 20:38:34 +00:00
|
|
|
return fetchExecute();
|
|
|
|
}
|
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
int EightBit::LR35902::execute(uint8_t opcode) {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
|
|
|
auto x = (opcode & 0b11000000) >> 6;
|
|
|
|
auto y = (opcode & 0b111000) >> 3;
|
|
|
|
auto z = (opcode & 0b111);
|
|
|
|
|
|
|
|
auto p = (y & 0b110) >> 1;
|
|
|
|
auto q = (y & 1);
|
|
|
|
|
|
|
|
if (m_prefixCB)
|
|
|
|
executeCB(x, y, z, p, q);
|
|
|
|
else
|
|
|
|
executeOther(x, y, z, p, q);
|
|
|
|
|
|
|
|
if (cycles == 0)
|
|
|
|
throw std::logic_error("Unhandled opcode");
|
|
|
|
|
|
|
|
return cycles * 4;
|
|
|
|
}
|
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
void EightBit::LR35902::executeCB(int x, int y, int z, int p, int q) {
|
2017-07-19 12:59:28 +00:00
|
|
|
auto& a = A();
|
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0: // rot[y] r[z]
|
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2017-07-19 12:59:28 +00:00
|
|
|
rlc(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2017-07-19 12:59:28 +00:00
|
|
|
rrc(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2017-07-19 12:59:28 +00:00
|
|
|
rl(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
2017-07-19 12:59:28 +00:00
|
|
|
rr(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2017-07-19 12:59:28 +00:00
|
|
|
sla(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2017-07-19 12:59:28 +00:00
|
|
|
sra(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6:
|
2017-07-19 12:59:28 +00:00
|
|
|
swap(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7:
|
2017-07-19 12:59:28 +00:00
|
|
|
srl(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
2017-07-19 12:59:28 +00:00
|
|
|
adjustZero<LR35902>(f, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-17 23:13:41 +00:00
|
|
|
if (z == 6) {
|
|
|
|
m_bus.fireWriteBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-17 23:13:41 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // BIT y, r[z]
|
2017-07-19 12:59:28 +00:00
|
|
|
bit(f, y, R(z, a));
|
2017-07-18 10:28:06 +00:00
|
|
|
cycles += 2;
|
|
|
|
if (z == 6) {
|
|
|
|
m_bus.fireReadBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-18 10:28:06 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // RES y, r[z]
|
2017-07-19 12:59:28 +00:00
|
|
|
res(y, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-17 23:13:41 +00:00
|
|
|
if (z == 6) {
|
|
|
|
m_bus.fireWriteBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-17 23:13:41 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SET y, r[z]
|
2017-07-19 12:59:28 +00:00
|
|
|
set(y, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-17 23:13:41 +00:00
|
|
|
if (z == 6) {
|
|
|
|
m_bus.fireWriteBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-17 23:13:41 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-06-09 10:42:32 +00:00
|
|
|
void EightBit::LR35902::executeOther(int x, int y, int z, int p, int q) {
|
2017-07-19 12:59:28 +00:00
|
|
|
auto& a = A();
|
|
|
|
auto& f = F();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Relative jumps and assorted ops
|
|
|
|
switch (y) {
|
|
|
|
case 0: // NOP
|
|
|
|
cycles++;
|
|
|
|
break;
|
|
|
|
case 1: // GB: LD (nn),SP
|
2017-06-09 15:01:12 +00:00
|
|
|
fetchWord();
|
2017-06-20 13:09:44 +00:00
|
|
|
setWordViaMemptr(SP());
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 5;
|
|
|
|
break;
|
|
|
|
case 2: // GB: STOP
|
|
|
|
stop();
|
|
|
|
cycles++;
|
|
|
|
break;
|
|
|
|
case 3: // JR d
|
2017-06-11 20:08:40 +00:00
|
|
|
jr(fetchByte());
|
|
|
|
cycles += 4;
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-07-19 12:59:28 +00:00
|
|
|
case 4: // JR cc,d
|
|
|
|
case 5:
|
|
|
|
case 6:
|
|
|
|
case 7:
|
|
|
|
if (jrConditionalFlag(f, y - 4))
|
|
|
|
cycles++;
|
|
|
|
cycles += 2;
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // 16-bit load immediate/add
|
|
|
|
switch (q) {
|
|
|
|
case 0: // LD rp,nn
|
2017-07-07 08:27:06 +00:00
|
|
|
fetchWord(RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 3;
|
|
|
|
break;
|
|
|
|
case 1: // ADD HL,rp
|
2017-07-19 12:59:28 +00:00
|
|
|
add(f, HL(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // Indirect loading
|
|
|
|
switch (q) {
|
|
|
|
case 0:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // LD (BC),A
|
2017-07-19 12:59:28 +00:00
|
|
|
m_memory.write(BC().word, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 1: // LD (DE),A
|
2017-07-19 12:59:28 +00:00
|
|
|
m_memory.write(DE().word, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 2: // GB: LDI (HL),A
|
2017-07-19 12:59:28 +00:00
|
|
|
m_memory.write(HL().word++, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 3: // GB: LDD (HL),A
|
2017-07-19 12:59:28 +00:00
|
|
|
m_memory.write(HL().word--, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // LD A,(BC)
|
2017-07-19 12:59:28 +00:00
|
|
|
a = m_memory.read(BC().word);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 1: // LD A,(DE)
|
2017-07-19 12:59:28 +00:00
|
|
|
a = m_memory.read(DE().word);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 2: // GB: LDI A,(HL)
|
2017-07-19 12:59:28 +00:00
|
|
|
a = m_memory.read(HL().word++);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 3: // GB: LDD A,(HL)
|
2017-07-19 12:59:28 +00:00
|
|
|
a = m_memory.read(HL().word--);
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // 16-bit INC/DEC
|
|
|
|
switch (q) {
|
|
|
|
case 0: // INC rp
|
2017-06-09 09:23:51 +00:00
|
|
|
++RP(p).word;
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // DEC rp
|
2017-06-09 09:23:51 +00:00
|
|
|
--RP(p).word;
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 4: // 8-bit INC
|
2017-07-19 12:59:28 +00:00
|
|
|
postIncrement(f, ++R(y, a)); // INC r
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles++;
|
2017-07-17 23:13:41 +00:00
|
|
|
if (y == 6) {
|
|
|
|
m_bus.fireWriteBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-17 23:13:41 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // 8-bit DEC
|
2017-07-19 12:59:28 +00:00
|
|
|
postDecrement(f, --R(y, a)); // DEC r
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles++;
|
2017-07-17 23:13:41 +00:00
|
|
|
if (y == 6) {
|
|
|
|
m_bus.fireWriteBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
2017-07-17 23:13:41 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // 8-bit load immediate
|
2017-07-19 12:59:28 +00:00
|
|
|
R(y, a) = fetchByte();
|
2017-07-17 23:13:41 +00:00
|
|
|
if (y == 6)
|
|
|
|
m_bus.fireWriteBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 7: // Assorted operations on accumulator/flags
|
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2017-07-19 12:59:28 +00:00
|
|
|
rlc(f, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2017-07-19 12:59:28 +00:00
|
|
|
rrc(f, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2017-07-19 12:59:28 +00:00
|
|
|
rl(f, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
2017-07-19 12:59:28 +00:00
|
|
|
rr(f, a);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2017-07-19 12:59:28 +00:00
|
|
|
daa(a, f);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2017-07-19 12:59:28 +00:00
|
|
|
cpl(a, f);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6:
|
2017-07-19 12:59:28 +00:00
|
|
|
scf(a, f);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7:
|
2017-07-19 12:59:28 +00:00
|
|
|
ccf(a, f);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles++;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // 8-bit loading
|
|
|
|
if (z == 6 && y == 6) { // Exception (replaces LD (HL), (HL))
|
|
|
|
halt();
|
|
|
|
} else {
|
2017-07-19 12:59:28 +00:00
|
|
|
R(y, a) = R(z, a);
|
2017-07-17 23:13:41 +00:00
|
|
|
if ((y == 6) || (z == 6)) { // M operations
|
|
|
|
if (y == 6)
|
|
|
|
m_bus.fireWriteBusEvent();
|
|
|
|
else
|
|
|
|
m_bus.fireReadBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles++;
|
2017-07-17 23:13:41 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
cycles++;
|
|
|
|
break;
|
|
|
|
case 2: // Operate on accumulator and register/memory location
|
|
|
|
switch (y) {
|
|
|
|
case 0: // ADD A,r
|
2017-07-19 12:59:28 +00:00
|
|
|
add(f, a, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC A,r
|
2017-07-19 12:59:28 +00:00
|
|
|
adc(f, a, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // SUB r
|
2017-07-19 12:59:28 +00:00
|
|
|
subtract(f, a, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SBC A,r
|
2017-07-19 12:59:28 +00:00
|
|
|
sbc(f, a, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // AND r
|
2017-07-19 12:59:28 +00:00
|
|
|
andr(f, a, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // XOR r
|
2017-07-19 12:59:28 +00:00
|
|
|
xorr(f, a, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OR r
|
2017-07-19 12:59:28 +00:00
|
|
|
orr(f, a, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CP r
|
2017-07-19 12:59:28 +00:00
|
|
|
compare(f, a, R(z, a));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles++;
|
2017-07-17 23:13:41 +00:00
|
|
|
if (z == 6) {
|
|
|
|
m_bus.fireReadBusEvent();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles++;
|
2017-07-17 23:13:41 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Conditional return
|
2017-07-19 12:59:28 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0:
|
|
|
|
case 1:
|
|
|
|
case 2:
|
|
|
|
case 3:
|
|
|
|
if (returnConditionalFlag(f, y))
|
2017-06-11 20:08:40 +00:00
|
|
|
cycles += 3;
|
|
|
|
cycles += 2;
|
2017-07-19 12:59:28 +00:00
|
|
|
break;
|
|
|
|
case 4: // GB: LD (FF00 + n),A
|
|
|
|
m_bus.writeRegister(fetchByte(), a);
|
|
|
|
cycles += 3;
|
|
|
|
break;
|
|
|
|
case 5: { // GB: ADD SP,dd
|
|
|
|
auto before = SP();
|
|
|
|
auto value = fetchByte();
|
|
|
|
auto result = SP().word + (int8_t)value;
|
|
|
|
SP().word = result;
|
|
|
|
clearFlag(f, ZF | NF);
|
|
|
|
setFlag(f, CF, result & Bit16);
|
|
|
|
adjustHalfCarryAdd(f, before.high, value, SP().high);
|
|
|
|
}
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 6: // GB: LD A,(FF00 + n)
|
|
|
|
a = m_bus.readRegister(fetchByte());
|
|
|
|
cycles += 3;
|
|
|
|
break;
|
|
|
|
case 7: { // GB: LD HL,SP + dd
|
|
|
|
auto before = HL();
|
|
|
|
auto value = fetchByte();
|
|
|
|
auto result = SP().word + (int8_t)value;
|
|
|
|
HL().word = result;
|
|
|
|
clearFlag(f, ZF | NF);
|
|
|
|
setFlag(f, CF, result & Bit16);
|
|
|
|
adjustHalfCarryAdd(f, before.high, value, HL().high);
|
2017-06-11 20:08:40 +00:00
|
|
|
}
|
2017-07-19 12:59:28 +00:00
|
|
|
cycles += 3;
|
|
|
|
break;
|
2017-06-11 20:08:40 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // POP & various ops
|
|
|
|
switch (q) {
|
|
|
|
case 0: // POP rp2[p]
|
2017-06-09 09:23:51 +00:00
|
|
|
popWord(RP2(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 3;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // RET
|
|
|
|
ret();
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 1: // GB: RETI
|
|
|
|
reti();
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 2: // JP HL
|
2017-06-19 12:53:00 +00:00
|
|
|
PC() = HL();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 1;
|
|
|
|
break;
|
|
|
|
case 3: // LD SP,HL
|
2017-06-19 12:53:00 +00:00
|
|
|
SP() = HL();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // Conditional jump
|
2017-07-19 12:59:28 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0:
|
|
|
|
case 1:
|
|
|
|
case 2:
|
|
|
|
case 3:
|
|
|
|
jumpConditionalFlag(f, y);
|
2017-06-11 20:08:40 +00:00
|
|
|
cycles += 3;
|
2017-07-19 12:59:28 +00:00
|
|
|
break;
|
|
|
|
case 4: // GB: LD (FF00 + C),A
|
|
|
|
m_bus.writeRegister(C(), a);
|
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 5: // GB: LD (nn),A
|
|
|
|
fetchWord();
|
|
|
|
m_bus.write(MEMPTR().word, a);
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 6: // GB: LD A,(FF00 + C)
|
|
|
|
a = m_bus.readRegister(C());
|
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 7: // GB: LD A,(nn)
|
|
|
|
fetchWord();
|
|
|
|
a = m_bus.read(MEMPTR().word);
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
2017-06-11 20:08:40 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // Assorted operations
|
|
|
|
switch (y) {
|
|
|
|
case 0: // JP nn
|
2017-06-09 15:01:12 +00:00
|
|
|
fetchWord();
|
2017-06-11 21:07:48 +00:00
|
|
|
jump();
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 1: // CB prefix
|
|
|
|
m_prefixCB = true;
|
|
|
|
fetchExecute();
|
|
|
|
break;
|
|
|
|
case 6: // DI
|
|
|
|
di();
|
|
|
|
cycles++;
|
|
|
|
break;
|
|
|
|
case 7: // EI
|
|
|
|
ei();
|
|
|
|
cycles++;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 4: // Conditional call: CALL cc[y], nn
|
2017-07-19 12:59:28 +00:00
|
|
|
if (callConditionalFlag(f, y))
|
2017-06-11 21:07:48 +00:00
|
|
|
cycles += 3;
|
2017-06-04 20:38:34 +00:00
|
|
|
cycles += 3;
|
|
|
|
break;
|
|
|
|
case 5: // PUSH & various ops
|
|
|
|
switch (q) {
|
|
|
|
case 0: // PUSH rp2[p]
|
|
|
|
pushWord(RP2(p));
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // CALL nn
|
2017-06-09 15:01:12 +00:00
|
|
|
fetchWord();
|
2017-06-11 21:07:48 +00:00
|
|
|
call();
|
|
|
|
cycles += 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 6: // Operate on accumulator and immediate operand: alu[y] n
|
|
|
|
switch (y) {
|
|
|
|
case 0: // ADD A,n
|
2017-07-19 12:59:28 +00:00
|
|
|
add(f, a, fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC A,n
|
2017-07-19 12:59:28 +00:00
|
|
|
adc(f, a, fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // SUB n
|
2017-07-19 12:59:28 +00:00
|
|
|
subtract(f, a, fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SBC A,n
|
2017-07-19 12:59:28 +00:00
|
|
|
sbc(f, a, fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // AND n
|
2017-07-19 12:59:28 +00:00
|
|
|
andr(f, a, fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // XOR n
|
2017-07-19 12:59:28 +00:00
|
|
|
xorr(f, a, fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OR n
|
2017-07-19 12:59:28 +00:00
|
|
|
orr(f, a, fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CP n
|
2017-07-19 12:59:28 +00:00
|
|
|
compare(f, a, fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
cycles += 2;
|
|
|
|
break;
|
|
|
|
case 7: // Restart: RST y * 8
|
|
|
|
restart(y << 3);
|
|
|
|
cycles += 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|