2017-06-04 20:38:34 +00:00
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#pragma once
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#include <cstdint>
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2017-10-28 12:08:07 +00:00
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#include <cassert>
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2017-06-04 20:38:34 +00:00
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2017-09-01 15:41:50 +00:00
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#include <IntelProcessor.h>
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#include <Signal.h>
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2017-10-19 21:43:09 +00:00
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#include <Register.h>
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2017-06-04 20:38:34 +00:00
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2017-06-09 10:42:32 +00:00
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namespace EightBit {
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2017-09-07 00:15:28 +00:00
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namespace GameBoy {
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2017-10-19 21:43:09 +00:00
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class Bus;
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2017-12-10 21:41:48 +00:00
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class LR35902 final : public IntelProcessor {
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2017-09-07 00:15:28 +00:00
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public:
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enum StatusBits {
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ZF = Bit7,
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NF = Bit6,
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HC = Bit5,
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CF = Bit4,
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};
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LR35902(Bus& memory);
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Signal<LR35902> ExecutingInstruction;
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2017-09-23 21:56:11 +00:00
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Signal<LR35902> ExecutedInstruction;
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2018-10-27 18:23:02 +00:00
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auto clockCycles() const {
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2017-11-03 22:05:01 +00:00
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return cycles() * 4;
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2017-09-23 21:56:11 +00:00
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}
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2017-09-07 00:15:28 +00:00
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2018-11-25 19:02:11 +00:00
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virtual register16_t& AF() final;
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virtual register16_t& BC() final;
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virtual register16_t& DE() final;
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virtual register16_t& HL() final;
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2017-09-07 00:15:28 +00:00
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protected:
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2018-12-29 19:17:36 +00:00
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virtual int execute() final;
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2017-12-10 21:41:48 +00:00
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virtual int step() final;
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2017-09-07 00:15:28 +00:00
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2018-08-25 12:35:53 +00:00
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virtual void handleRESET() final;
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virtual void handleINT() final;
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2018-08-25 00:57:22 +00:00
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2017-09-07 00:15:28 +00:00
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private:
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Bus& m_bus;
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2018-06-15 23:55:32 +00:00
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register16_t af = 0xffff;
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register16_t bc = 0xffff;
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register16_t de = 0xffff;
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register16_t hl = 0xffff;
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2017-09-07 00:15:28 +00:00
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2017-11-11 11:12:09 +00:00
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bool m_ime = false;
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bool m_stopped = false;
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2017-09-07 00:15:28 +00:00
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2017-11-11 11:12:09 +00:00
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bool m_prefixCB = false;
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2017-09-07 00:15:28 +00:00
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bool& IME() { return m_ime; }
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2018-10-27 18:23:02 +00:00
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auto R(const int r) {
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2018-06-23 15:43:05 +00:00
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ASSUME(r >= 0);
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ASSUME(r <= 7);
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2017-09-07 00:15:28 +00:00
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switch (r) {
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case 0:
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return B();
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case 1:
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return C();
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case 2:
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return D();
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case 3:
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return E();
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case 4:
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return H();
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case 5:
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return L();
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case 6:
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2019-03-02 21:58:34 +00:00
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return busRead(HL());
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2017-09-07 00:15:28 +00:00
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case 7:
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2018-06-23 15:43:05 +00:00
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return A();
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2017-12-10 21:41:48 +00:00
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default:
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UNREACHABLE;
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2017-09-07 00:15:28 +00:00
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}
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2017-06-09 10:42:32 +00:00
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}
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2017-09-07 00:15:28 +00:00
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2018-06-23 15:43:05 +00:00
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void R(const int r, const uint8_t value) {
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ASSUME(r >= 0);
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ASSUME(r <= 7);
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2017-09-07 00:15:28 +00:00
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switch (r) {
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case 0:
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B() = value;
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break;
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case 1:
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C() = value;
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break;
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case 2:
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D() = value;
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break;
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case 3:
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E() = value;
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break;
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case 4:
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H() = value;
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break;
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case 5:
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L() = value;
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break;
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case 6:
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2019-03-02 21:58:34 +00:00
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busWrite(HL(), value);
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2017-09-07 00:15:28 +00:00
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break;
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case 7:
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2018-06-23 15:43:05 +00:00
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A() = value;
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2017-09-07 00:15:28 +00:00
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break;
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2017-12-10 21:41:48 +00:00
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default:
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UNREACHABLE;
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2017-09-07 00:15:28 +00:00
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}
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2017-08-06 16:06:48 +00:00
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}
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2017-09-07 00:15:28 +00:00
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2018-10-27 18:23:02 +00:00
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auto& RP(const int rp) {
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2018-06-23 15:43:05 +00:00
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ASSUME(rp >= 0);
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ASSUME(rp <= 3);
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2017-09-07 00:15:28 +00:00
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switch (rp) {
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case 0b00:
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return BC();
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case 0b01:
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return DE();
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case 0b10:
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return HL();
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case 0b11:
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return SP();
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default:
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2017-10-02 15:47:05 +00:00
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UNREACHABLE;
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2017-09-07 00:15:28 +00:00
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}
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2017-06-09 10:42:32 +00:00
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}
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2017-09-07 00:15:28 +00:00
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2018-10-27 18:23:02 +00:00
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auto& RP2(const int rp) {
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2018-06-23 15:43:05 +00:00
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ASSUME(rp >= 0);
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ASSUME(rp <= 3);
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2017-09-07 00:15:28 +00:00
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switch (rp) {
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case 0b00:
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return BC();
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case 0b01:
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return DE();
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case 0b10:
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return HL();
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case 0b11:
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return AF();
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default:
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2017-10-02 15:47:05 +00:00
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UNREACHABLE;
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2017-09-07 00:15:28 +00:00
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}
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2017-06-09 10:42:32 +00:00
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}
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2017-06-04 20:38:34 +00:00
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2018-10-27 18:23:02 +00:00
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void adjustHalfCarryAdd(const uint8_t before, const uint8_t value, const int calculation) {
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2018-06-23 15:43:05 +00:00
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setFlag(F(), HC, calculateHalfCarryAdd(before, value, calculation));
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2017-09-07 00:15:28 +00:00
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}
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2017-06-04 20:38:34 +00:00
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2018-10-27 18:23:02 +00:00
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void adjustHalfCarrySub(const uint8_t before, const uint8_t value, const int calculation) {
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2018-06-23 15:43:05 +00:00
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setFlag(F(), HC, calculateHalfCarrySub(before, value, calculation));
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2017-09-07 00:15:28 +00:00
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}
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2017-06-04 20:38:34 +00:00
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2018-06-23 15:43:05 +00:00
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void subtract(uint8_t& operand, uint8_t value, int carry = 0);
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2017-07-19 12:59:28 +00:00
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2018-06-23 15:43:05 +00:00
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void executeCB(int x, int y, int z, int p, int q);
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void executeOther(int x, int y, int z, int p, int q);
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2017-06-04 20:38:34 +00:00
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2018-06-23 15:43:05 +00:00
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void increment(uint8_t& operand);
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void decrement(uint8_t& operand);
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2017-06-04 20:38:34 +00:00
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2017-09-07 00:15:28 +00:00
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void stop() { m_stopped = true; }
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void start() { m_stopped = false; }
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bool stopped() const { return m_stopped; }
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2017-08-30 22:17:34 +00:00
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2017-09-07 00:15:28 +00:00
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void di();
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void ei();
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2017-08-30 22:17:34 +00:00
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2017-09-07 00:15:28 +00:00
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void reti();
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2017-06-04 20:38:34 +00:00
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2018-06-23 15:43:05 +00:00
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bool jrConditionalFlag(int flag);
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bool returnConditionalFlag(int flag);
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bool jumpConditionalFlag(int flag);
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bool callConditionalFlag(int flag);
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void add(register16_t& operand, register16_t value);
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void add(uint8_t& operand, uint8_t value, int carry = 0);
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void adc(uint8_t& operand, uint8_t value);
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void sbc(uint8_t value);
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void andr(uint8_t& operand, uint8_t value);
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void xorr(uint8_t value);
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void orr(uint8_t value);
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void compare(uint8_t check, uint8_t value);
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uint8_t rlc(uint8_t operand);
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uint8_t rrc(uint8_t operand);
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uint8_t rl(uint8_t operand);
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uint8_t rr(uint8_t operand);
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uint8_t sla(uint8_t operand);
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uint8_t sra(uint8_t operand);
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uint8_t srl(uint8_t operand);
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2019-07-21 10:25:56 +00:00
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void bit(int n, uint8_t operand);
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2017-09-07 00:15:28 +00:00
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static uint8_t res(int n, uint8_t operand);
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static uint8_t set(int n, uint8_t operand);
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2017-07-19 12:59:28 +00:00
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2018-06-23 15:43:05 +00:00
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void daa();
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2017-07-19 12:59:28 +00:00
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2018-06-23 15:43:05 +00:00
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void scf();
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void ccf();
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void cpl();
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2017-07-19 12:59:28 +00:00
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2018-06-23 15:43:05 +00:00
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uint8_t swap(uint8_t operand);
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2017-09-07 00:15:28 +00:00
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};
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}
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2017-06-09 10:42:32 +00:00
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}
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