2017-06-04 20:38:34 +00:00
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#include "stdafx.h"
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#include "Z80.h"
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// based on http://www.z80.info/decoding.htm
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2017-08-30 22:17:34 +00:00
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2020-02-09 11:51:58 +00:00
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EightBit::Z80::Z80(Bus& bus)
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: IntelProcessor(bus) {
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2019-09-06 22:55:57 +00:00
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RaisedPOWER.connect([this](EventArgs) {
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2019-11-02 17:30:03 +00:00
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2019-09-06 22:55:57 +00:00
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raiseM1();
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2019-11-19 23:06:08 +00:00
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raiseRFSH();
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2019-09-15 00:35:57 +00:00
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raiseIORQ();
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2019-11-09 18:58:23 +00:00
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raiseMREQ();
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2019-09-15 00:35:57 +00:00
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raiseRD();
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raiseWR();
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2019-09-06 22:55:57 +00:00
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di();
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IM() = 0;
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REFRESH() = 0;
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IV() = Mask8;
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exxAF();
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exx();
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2019-11-02 17:30:03 +00:00
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AF() = IX() = IY() = BC() = DE() = HL() = Mask16;
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2019-09-06 22:55:57 +00:00
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m_prefixCB = m_prefixDD = m_prefixED = m_prefixFD = false;
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});
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2019-09-14 14:04:46 +00:00
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2019-11-16 23:37:57 +00:00
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RaisedM1.connect([this](EventArgs) {
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2019-09-14 14:04:46 +00:00
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++REFRESH();
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});
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2017-06-04 20:38:34 +00:00
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}
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2019-01-14 23:17:54 +00:00
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DEFINE_PIN_LEVEL_CHANGERS(NMI, Z80);
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DEFINE_PIN_LEVEL_CHANGERS(M1, Z80);
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2019-11-16 23:37:57 +00:00
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DEFINE_PIN_LEVEL_CHANGERS(RFSH, Z80);
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2019-11-02 17:38:20 +00:00
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DEFINE_PIN_LEVEL_CHANGERS(MREQ, Z80);
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2019-09-14 22:38:47 +00:00
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DEFINE_PIN_LEVEL_CHANGERS(IORQ, Z80);
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2019-09-15 00:35:57 +00:00
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DEFINE_PIN_LEVEL_CHANGERS(RD, Z80);
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DEFINE_PIN_LEVEL_CHANGERS(WR, Z80);
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2019-01-14 23:17:54 +00:00
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2020-05-03 19:45:01 +00:00
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void EightBit::Z80::memoryWrite() {
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2017-11-05 14:48:15 +00:00
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2020-05-03 19:45:01 +00:00
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class _Writer final {
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Z80& m_parent;
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public:
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_Writer(Z80& parent) : m_parent(parent) {
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m_parent.WritingMemory.fire(EventArgs::empty());
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m_parent.tick(2);
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m_parent.lowerMREQ();
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}
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2017-11-05 14:48:15 +00:00
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2020-05-03 19:45:01 +00:00
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~_Writer() {
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m_parent.raiseMREQ();
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m_parent.WrittenMemory.fire(EventArgs::empty());
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}
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};
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2017-11-05 14:48:15 +00:00
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2020-05-03 19:45:01 +00:00
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_Writer writer(*this);
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2020-02-09 11:51:58 +00:00
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IntelProcessor::memoryWrite();
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}
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uint8_t EightBit::Z80::memoryRead() {
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2020-05-03 19:45:01 +00:00
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class _Reader final {
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Z80& m_parent;
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public:
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_Reader(Z80& parent) : m_parent(parent) {
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m_parent.ReadingMemory.fire(EventArgs::empty());
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m_parent.tick(2);
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m_parent.lowerMREQ();
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}
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~_Reader() {
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m_parent.raiseMREQ();
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m_parent.ReadMemory.fire(EventArgs::empty());
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}
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};
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_Reader reader(*this);
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return IntelProcessor::memoryRead();
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2020-02-09 11:51:58 +00:00
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}
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void EightBit::Z80::busWrite() {
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tick();
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2020-05-03 19:45:01 +00:00
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_ActivateWR writer(*this);
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2019-09-15 00:35:57 +00:00
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IntelProcessor::busWrite();
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}
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uint8_t EightBit::Z80::busRead() {
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2020-02-09 11:51:58 +00:00
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tick();
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2020-05-03 19:45:01 +00:00
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_ActivateRD reader(*this);
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return IntelProcessor::busRead();
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2019-09-15 00:35:57 +00:00
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}
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2018-08-25 00:34:30 +00:00
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void EightBit::Z80::handleRESET() {
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2018-10-27 17:41:55 +00:00
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IntelProcessor::handleRESET();
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2018-08-25 00:34:30 +00:00
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di();
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2019-12-29 01:18:54 +00:00
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IV() = REFRESH() = 0;
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SP().word = AF().word = Mask16;
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2019-01-09 23:24:33 +00:00
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tick(3);
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2018-08-25 00:34:30 +00:00
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}
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void EightBit::Z80::handleNMI() {
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2019-01-14 02:10:17 +00:00
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raiseNMI();
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2019-08-29 07:51:15 +00:00
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raiseHALT();
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2019-12-29 01:18:54 +00:00
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IFF2() = IFF1();
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2018-08-25 00:34:30 +00:00
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IFF1() = false;
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2020-05-03 19:45:01 +00:00
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readBusDataM1();
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2018-08-25 00:34:30 +00:00
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restart(0x66);
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}
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void EightBit::Z80::handleINT() {
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2018-10-27 17:41:55 +00:00
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IntelProcessor::handleINT();
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2020-05-03 19:45:01 +00:00
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uint8_t data;
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{
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_ActivateIORQ iorq(*this);
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data = readBusDataM1();
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}
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2019-09-08 15:28:19 +00:00
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di();
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2019-12-29 01:18:54 +00:00
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tick(5);
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2019-09-08 15:28:19 +00:00
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switch (IM()) {
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case 0: // i8080 equivalent
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2020-02-09 11:51:58 +00:00
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IntelProcessor::execute(data);
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2019-09-08 15:28:19 +00:00
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break;
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case 1:
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2019-12-29 01:18:54 +00:00
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tick();
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2019-09-08 15:28:19 +00:00
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restart(7 << 3);
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break;
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case 2:
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2019-12-29 01:18:54 +00:00
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tick(7);
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call(MEMPTR() = { data, IV() });
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2019-09-08 15:28:19 +00:00
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break;
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default:
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UNREACHABLE;
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2018-08-25 00:34:30 +00:00
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}
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}
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2017-06-11 20:08:40 +00:00
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void EightBit::Z80::di() {
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2017-06-04 20:38:34 +00:00
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IFF1() = IFF2() = false;
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}
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2017-06-11 20:08:40 +00:00
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void EightBit::Z80::ei() {
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2017-06-04 20:38:34 +00:00
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IFF1() = IFF2() = true;
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}
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2019-11-09 18:58:23 +00:00
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uint8_t EightBit::Z80::increment(uint8_t& f, const uint8_t operand) {
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f = clearBit(f, NF);
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2018-11-29 00:09:40 +00:00
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const uint8_t result = operand + 1;
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2019-11-09 18:58:23 +00:00
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f = adjustSZXY<Z80>(f, result);
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f = setBit(f, VF, result == Bit7);
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f = clearBit(f, HC, lowNibble(result));
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2018-11-29 00:09:40 +00:00
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2019-11-09 18:58:23 +00:00
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uint8_t EightBit::Z80::decrement(uint8_t& f, const uint8_t operand) {
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f = setBit(f, NF);
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f = clearBit(f, HC, lowNibble(operand));
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2018-11-29 00:09:40 +00:00
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const uint8_t result = operand - 1;
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2019-11-09 18:58:23 +00:00
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f = adjustSZXY<Z80>(f, result);
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f = setBit(f, VF, result == Mask7);
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2018-11-29 00:09:40 +00:00
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2019-12-29 01:18:54 +00:00
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bool EightBit::Z80::convertCondition(const uint8_t f, int flag) {
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2018-03-10 01:53:57 +00:00
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ASSUME(flag >= 0);
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2019-12-29 01:18:54 +00:00
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ASSUME(flag <= 7);
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2017-06-04 20:38:34 +00:00
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switch (flag) {
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2019-12-29 01:18:54 +00:00
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case 0:
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return !(f & ZF);
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case 1:
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return f & ZF;
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case 2:
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return !(f & CF);
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case 3:
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return f & CF;
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case 4:
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return !(f & PF);
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case 5:
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return f & PF;
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case 6:
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return !(f & SF);
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case 7:
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return f & SF;
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2017-07-02 16:38:19 +00:00
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default:
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2017-10-29 18:47:23 +00:00
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UNREACHABLE;
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2017-06-04 20:38:34 +00:00
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}
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}
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2019-12-29 01:18:54 +00:00
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void EightBit::Z80::returnConditionalFlag(const uint8_t f, const int flag) {
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2020-02-22 08:32:29 +00:00
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tick();
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if (convertCondition(f, flag))
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2019-12-29 01:18:54 +00:00
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ret();
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2017-06-04 20:38:34 +00:00
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}
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2019-12-29 01:18:54 +00:00
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void EightBit::Z80::jrConditionalFlag(const uint8_t f, const int flag) {
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jrConditional(convertCondition(f, flag));
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}
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void EightBit::Z80::jumpConditionalFlag(const uint8_t f, const int flag) {
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jumpConditional(convertCondition(f, flag));
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}
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void EightBit::Z80::callConditionalFlag(const uint8_t f, const int flag) {
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callConditional(convertCondition(f, flag));
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}
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2017-06-05 21:39:15 +00:00
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void EightBit::Z80::retn() {
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2017-06-04 20:38:34 +00:00
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ret();
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IFF1() = IFF2();
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}
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2017-06-05 21:39:15 +00:00
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void EightBit::Z80::reti() {
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2017-06-04 20:38:34 +00:00
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retn();
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}
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2019-11-09 18:58:23 +00:00
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EightBit::register16_t EightBit::Z80::sbc(uint8_t& f, const register16_t operand, const register16_t value) {
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2017-06-18 17:14:39 +00:00
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2019-11-09 18:58:23 +00:00
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const auto subtraction = operand.word - value.word - (f & CF);
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2019-09-14 14:04:46 +00:00
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const register16_t result = subtraction;
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2017-06-04 20:38:34 +00:00
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2019-11-09 18:58:23 +00:00
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f = setBit(f, NF);
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f = clearBit(f, ZF, result.word);
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f = setBit(f, CF, subtraction & Bit16);
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2019-11-10 11:15:07 +00:00
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f = adjustHalfCarrySub(f, operand.high, value.high, result.high);
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2019-11-09 18:58:23 +00:00
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f = adjustXY<Z80>(f, result.high);
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2017-06-04 20:38:34 +00:00
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2019-09-14 14:04:46 +00:00
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const auto beforeNegative = operand.high & SF;
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const auto valueNegative = value.high & SF;
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const auto afterNegative = result.high & SF;
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2017-06-04 20:38:34 +00:00
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2019-11-09 18:58:23 +00:00
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f = setBit(f, SF, afterNegative);
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2019-11-10 11:15:07 +00:00
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f = adjustOverflowSub(f, beforeNegative, valueNegative, afterNegative);
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2017-07-03 20:42:18 +00:00
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2019-09-14 14:04:46 +00:00
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MEMPTR() = operand + 1;
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2020-02-23 09:37:03 +00:00
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tick(7);
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2019-09-14 14:04:46 +00:00
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2019-11-09 18:58:23 +00:00
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EightBit::register16_t EightBit::Z80::adc(uint8_t& f, const register16_t operand, const register16_t value) {
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2017-06-18 17:14:39 +00:00
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2019-11-09 18:58:23 +00:00
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const auto result = add(f, operand, value, f & CF);
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f = clearBit(f, ZF, result.word);
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2017-06-04 20:38:34 +00:00
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2019-09-14 14:04:46 +00:00
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const auto beforeNegative = operand.high & SF;
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2017-06-26 22:22:32 +00:00
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const auto valueNegative = value.high & SF;
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2019-09-14 14:04:46 +00:00
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const auto afterNegative = result.high & SF;
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2017-06-04 20:38:34 +00:00
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2019-11-09 18:58:23 +00:00
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f = setBit(f, SF, afterNegative);
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2019-11-10 11:15:07 +00:00
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f = adjustOverflowAdd(f, beforeNegative, valueNegative, afterNegative);
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2017-07-03 20:42:18 +00:00
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2019-09-14 14:04:46 +00:00
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2019-11-09 18:58:23 +00:00
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EightBit::register16_t EightBit::Z80::add(uint8_t& f, const register16_t operand, const register16_t value, int carry) {
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2017-06-18 17:14:39 +00:00
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2019-09-14 14:04:46 +00:00
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const int addition = operand.word + value.word + carry;
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const register16_t result = addition;
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2017-06-04 20:38:34 +00:00
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2019-11-09 18:58:23 +00:00
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f = clearBit(f, NF);
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f = setBit(f, CF, addition & Bit16);
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f = adjustHalfCarryAdd(f, operand.high, value.high, result.high);
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f = adjustXY<Z80>(f, result.high);
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2017-07-03 20:42:18 +00:00
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2019-09-14 14:04:46 +00:00
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MEMPTR() = operand + 1;
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2020-02-23 09:37:03 +00:00
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tick(7);
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2019-09-14 14:04:46 +00:00
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return result;
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2017-06-04 20:38:34 +00:00
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}
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2019-11-09 18:58:23 +00:00
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uint8_t EightBit::Z80::add(uint8_t& f, const uint8_t operand, const uint8_t value, const int carry) {
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2017-06-18 17:14:39 +00:00
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2019-09-14 14:04:46 +00:00
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const register16_t addition = operand + value + carry;
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const auto result = addition.low;
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2017-06-04 20:38:34 +00:00
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2019-11-09 18:58:23 +00:00
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f = adjustHalfCarryAdd(f, operand, value, result);
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2019-11-10 11:15:07 +00:00
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f = adjustOverflowAdd(f, operand, value, result);
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2017-06-04 20:38:34 +00:00
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2019-11-09 18:58:23 +00:00
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f = clearBit(f, NF);
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f = setBit(f, CF, addition.high & CF);
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f = adjustSZXY<Z80>(f, result);
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2019-09-14 14:04:46 +00:00
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return result;
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2017-06-04 20:38:34 +00:00
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}
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|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::adc(uint8_t& f, const uint8_t operand, const uint8_t value) {
|
|
|
|
return add(f, operand, value, f & CF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::subtract(uint8_t& f, const uint8_t operand, const uint8_t value, const int carry) {
|
2017-06-18 17:14:39 +00:00
|
|
|
|
2018-11-29 00:09:40 +00:00
|
|
|
const register16_t subtraction = operand - value - carry;
|
|
|
|
const auto result = subtraction.low;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-10 11:15:07 +00:00
|
|
|
f = adjustHalfCarrySub(f, operand, value, result);
|
|
|
|
f = adjustOverflowSub(f, operand, value, result);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
f = setBit(f, NF);
|
|
|
|
f = setBit(f, CF, subtraction.high & CF);
|
|
|
|
f = adjustSZ<Z80>(f, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::sub(uint8_t& f, const uint8_t operand, const uint8_t value, const int carry) {
|
|
|
|
const auto subtraction = subtract(f, operand, value, carry);
|
|
|
|
f = adjustXY<Z80>(f, subtraction);
|
2019-09-14 14:04:46 +00:00
|
|
|
return subtraction;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::sbc(uint8_t& f, const uint8_t operand, const uint8_t value) {
|
|
|
|
return sub(f, operand, value, f & CF);
|
2017-06-26 22:22:32 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::andr(uint8_t& f, const uint8_t operand, const uint8_t value) {
|
|
|
|
f = setBit(f, HC);
|
|
|
|
f = clearBit(f, CF | NF);
|
|
|
|
const uint8_t result = operand & value;
|
|
|
|
f = adjustSZPXY<Z80>(f, result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::xorr(uint8_t& f, const uint8_t operand, const uint8_t value) {
|
|
|
|
f = clearBit(f, HC | CF | NF);
|
|
|
|
const uint8_t result = operand ^ value;
|
|
|
|
f = adjustSZPXY<Z80>(f, result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::orr(uint8_t& f, const uint8_t operand, const uint8_t value) {
|
|
|
|
f = clearBit(f, HC | CF | NF);
|
|
|
|
const uint8_t result = operand | value;
|
|
|
|
f = adjustSZPXY<Z80>(f, result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::compare(uint8_t& f, uint8_t operand, const uint8_t value) {
|
|
|
|
subtract(f, operand, value);
|
|
|
|
f = adjustXY<Z80>(f, value);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::rlc(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF | HC);
|
2017-10-29 20:15:49 +00:00
|
|
|
const auto carry = operand & Bit7;
|
2019-11-09 18:58:23 +00:00
|
|
|
f = setBit(f, CF, carry);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand << 1) | (carry >> 7);
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustXY<Z80>(f, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::rrc(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF | HC);
|
2017-10-29 20:15:49 +00:00
|
|
|
const auto carry = operand & Bit0;
|
2019-11-09 18:58:23 +00:00
|
|
|
f = setBit(f, CF, carry);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand >> 1) | (carry << 7);
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustXY<Z80>(f, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::rl(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF | HC);
|
|
|
|
const auto carry = f & CF;
|
|
|
|
f = setBit(f, CF, operand & Bit7);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand << 1) | carry;
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustXY<Z80>(f, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::rr(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF | HC);
|
|
|
|
const auto carry = f & CF;
|
|
|
|
f = setBit(f, CF, operand & Bit0);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand >> 1) | (carry << 7);
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustXY<Z80>(f, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::sla(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF | HC);
|
|
|
|
f = setBit(f, CF, operand & Bit7);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = operand << 1;
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustXY<Z80>(f, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::sra(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF | HC);
|
|
|
|
f = setBit(f, CF, operand & Bit0);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand >> 1) | (operand & Bit7);
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustXY<Z80>(f, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::sll(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF | HC);
|
|
|
|
f = setBit(f, CF, operand & Bit7);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand << 1) | Bit0;
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustXY<Z80>(f, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::srl(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF | HC);
|
|
|
|
f = setBit(f, CF, operand & Bit0);
|
2018-11-29 00:09:40 +00:00
|
|
|
const uint8_t result = (operand >> 1) & ~Bit7;
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustXY<Z80>(f, result);
|
|
|
|
f = setBit(f, ZF, result);
|
2018-11-29 00:09:40 +00:00
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::bit(uint8_t& f, const int n, const uint8_t operand) {
|
2018-03-10 01:53:57 +00:00
|
|
|
ASSUME(n >= 0);
|
|
|
|
ASSUME(n <= 7);
|
2019-11-09 18:58:23 +00:00
|
|
|
f = setBit(f, HC);
|
|
|
|
f = clearBit(f, NF);
|
2019-11-03 09:23:28 +00:00
|
|
|
const auto discarded = operand & Chip::bit(n);
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustSZ<Z80>(f, discarded);
|
|
|
|
f = clearBit(f, PF, discarded);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-04-14 08:39:06 +00:00
|
|
|
uint8_t EightBit::Z80::res(const int n, const uint8_t operand) {
|
2018-03-10 01:53:57 +00:00
|
|
|
ASSUME(n >= 0);
|
|
|
|
ASSUME(n <= 7);
|
2019-11-10 11:15:07 +00:00
|
|
|
return clearBit(operand, Chip::bit(n));
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-04-14 08:39:06 +00:00
|
|
|
uint8_t EightBit::Z80::set(const int n, const uint8_t operand) {
|
2018-03-10 01:53:57 +00:00
|
|
|
ASSUME(n >= 0);
|
|
|
|
ASSUME(n <= 7);
|
2019-11-10 11:15:07 +00:00
|
|
|
return setBit(operand, Chip::bit(n));
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::neg(uint8_t& f, uint8_t operand) {
|
2017-06-28 14:39:31 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
f = setBit(f, PF, operand == Bit7);
|
|
|
|
f = setBit(f, CF, operand);
|
|
|
|
f = setBit(f, NF);
|
2017-06-28 14:39:31 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
const uint8_t result = (~operand + 1); // two's complement
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-10 11:15:07 +00:00
|
|
|
f = adjustHalfCarrySub(f, 0U, operand, result);
|
|
|
|
f = adjustOverflowSub(f, 0U, operand, result);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustSZXY<Z80>(f, result);
|
2017-06-28 14:39:31 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
return result;
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::daa(uint8_t& f, uint8_t operand) {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
const auto lowAdjust = (f & HC) || (lowNibble(operand) > 9);
|
|
|
|
const auto highAdjust = (f & CF) || (operand > 0x99);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
auto updated = operand;
|
|
|
|
if (f & NF) {
|
2017-06-04 20:38:34 +00:00
|
|
|
if (lowAdjust)
|
2017-06-28 14:39:31 +00:00
|
|
|
updated -= 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
if (highAdjust)
|
2017-06-28 14:39:31 +00:00
|
|
|
updated -= 0x60;
|
2017-06-04 20:38:34 +00:00
|
|
|
} else {
|
|
|
|
if (lowAdjust)
|
2017-06-28 14:39:31 +00:00
|
|
|
updated += 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
if (highAdjust)
|
2017-06-28 14:39:31 +00:00
|
|
|
updated += 0x60;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
f = (f & (CF | NF)) | (operand > 0x99 ? CF : 0) | ((operand ^ updated) & HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustSZPXY<Z80>(f, updated);
|
|
|
|
|
|
|
|
return updated;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t EightBit::Z80::cpl(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = setBit(f, HC | NF);
|
|
|
|
const uint8_t result = ~operand;
|
|
|
|
f = adjustXY<Z80>(f, result);
|
|
|
|
return result;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::scf(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = setBit(f, CF);
|
|
|
|
f = clearBit(f, HC | NF);
|
|
|
|
f = adjustXY<Z80>(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::ccf(uint8_t& f, const uint8_t operand) {
|
|
|
|
f = clearBit(f, NF);
|
|
|
|
const auto carry = f & CF;
|
|
|
|
f = setBit(f, HC, carry);
|
|
|
|
f = clearBit(f, CF, carry);
|
|
|
|
f = adjustXY<Z80>(f, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-08-16 20:56:48 +00:00
|
|
|
void EightBit::Z80::xhtl(register16_t& exchange) {
|
2020-02-09 11:51:58 +00:00
|
|
|
MEMPTR().low = IntelProcessor::memoryRead(SP());
|
2018-08-11 20:19:19 +00:00
|
|
|
++BUS().ADDRESS();
|
2020-02-09 11:51:58 +00:00
|
|
|
MEMPTR().high = memoryRead();
|
2019-12-29 01:18:54 +00:00
|
|
|
tick();
|
2020-02-09 11:51:58 +00:00
|
|
|
IntelProcessor::memoryWrite(exchange.high);
|
2019-08-16 20:56:48 +00:00
|
|
|
exchange.high = MEMPTR().high;
|
|
|
|
--BUS().ADDRESS();
|
2020-02-09 11:51:58 +00:00
|
|
|
IntelProcessor::memoryWrite(exchange.low);
|
2019-08-16 20:56:48 +00:00
|
|
|
exchange.low = MEMPTR().low;
|
2020-02-22 08:32:29 +00:00
|
|
|
tick(2);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::blockCompare(uint8_t& f, const uint8_t value, const register16_t source, register16_t& counter) {
|
2017-06-18 17:14:39 +00:00
|
|
|
|
2020-02-09 11:51:58 +00:00
|
|
|
const auto contents = IntelProcessor::memoryRead(source);
|
2019-11-09 18:58:23 +00:00
|
|
|
uint8_t result = value - contents;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
f = setBit(f, PF, --counter.word);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
f = adjustSZ<Z80>(f, result);
|
2019-11-10 11:15:07 +00:00
|
|
|
f = adjustHalfCarrySub(f, value, contents, result);
|
2019-11-09 18:58:23 +00:00
|
|
|
f = setBit(f, NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
result -= ((f & HC) >> 4);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
f = setBit(f, YF, result & Bit1);
|
|
|
|
f = setBit(f, XF, result & Bit3);
|
2020-02-22 08:32:29 +00:00
|
|
|
|
|
|
|
tick(5);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::cpi(uint8_t& f, uint8_t value) {
|
|
|
|
blockCompare(f, value, HL()++, BC());
|
2018-08-11 20:19:19 +00:00
|
|
|
++MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::cpd(uint8_t& f, uint8_t value) {
|
|
|
|
blockCompare(f, value, HL()--, BC());
|
2018-08-11 20:19:19 +00:00
|
|
|
--MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
bool EightBit::Z80::cpir(uint8_t& f, uint8_t value) {
|
|
|
|
cpi(f, value);
|
|
|
|
return (f & PF) && !(f & ZF); // See CPI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
bool EightBit::Z80::cpdr(uint8_t& f, uint8_t value) {
|
|
|
|
cpd(f, value);
|
|
|
|
return (f & PF) && !(f & ZF); // See CPD
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::blockLoad(uint8_t& f, const uint8_t a, const register16_t source, const register16_t destination, register16_t& counter) {
|
2020-02-09 11:51:58 +00:00
|
|
|
const auto value = IntelProcessor::memoryRead(source);
|
|
|
|
IntelProcessor::memoryWrite(destination, value);
|
2019-11-09 18:58:23 +00:00
|
|
|
const auto xy = a + value;
|
|
|
|
f = setBit(f, XF, xy & Bit3);
|
|
|
|
f = setBit(f, YF, xy & Bit1);
|
|
|
|
f = clearBit(f, NF | HC);
|
|
|
|
f = setBit(f, PF, --counter.word);
|
2020-02-22 08:32:29 +00:00
|
|
|
tick(2);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::ldd(uint8_t& f, const uint8_t a) {
|
|
|
|
blockLoad(f, a, HL()--, DE()--, BC());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::ldi(uint8_t& f, const uint8_t a) {
|
|
|
|
blockLoad(f, a, HL()++, DE()++, BC());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
bool EightBit::Z80::ldir(uint8_t& f, const uint8_t a) {
|
|
|
|
ldi(f, a);
|
|
|
|
return !!(f & PF); // See LDI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
bool EightBit::Z80::lddr(uint8_t& f, const uint8_t a) {
|
|
|
|
ldd(f, a);
|
|
|
|
return !!(f & PF); // See LDD
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-09-20 23:16:00 +00:00
|
|
|
void EightBit::Z80::blockIn(register16_t& source, const register16_t destination) {
|
2018-08-12 15:25:30 +00:00
|
|
|
MEMPTR() = BUS().ADDRESS() = source;
|
2019-12-29 01:18:54 +00:00
|
|
|
tick();
|
2020-02-09 11:51:58 +00:00
|
|
|
const auto value = portRead();
|
|
|
|
IntelProcessor::memoryWrite(destination, value);
|
2019-11-09 18:58:23 +00:00
|
|
|
source.high = decrement(F(), source.high);
|
|
|
|
F() = setBit(F(), NF);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-08-12 15:25:30 +00:00
|
|
|
void EightBit::Z80::ini() {
|
|
|
|
blockIn(BC(), HL()++);
|
|
|
|
++MEMPTR();
|
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::ind() {
|
2018-08-12 15:25:30 +00:00
|
|
|
blockIn(BC(), HL()--);
|
2018-08-11 20:19:19 +00:00
|
|
|
--MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::inir() {
|
|
|
|
ini();
|
|
|
|
return !(F() & ZF); // See INI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::indr() {
|
|
|
|
ind();
|
|
|
|
return !(F() & ZF); // See IND
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-08-12 15:25:30 +00:00
|
|
|
void EightBit::Z80::blockOut(const register16_t source, register16_t& destination) {
|
2019-12-29 01:18:54 +00:00
|
|
|
tick();
|
2020-02-09 11:51:58 +00:00
|
|
|
const auto value = IntelProcessor::memoryRead(source);
|
2019-11-09 18:58:23 +00:00
|
|
|
destination.high = decrement(F(), destination.high);
|
2018-08-12 15:25:30 +00:00
|
|
|
BUS().ADDRESS() = destination;
|
2020-02-09 11:51:58 +00:00
|
|
|
portWrite();
|
2018-08-12 15:25:30 +00:00
|
|
|
MEMPTR() = destination;
|
2019-11-09 18:58:23 +00:00
|
|
|
F() = setBit(F(), NF, value & Bit7);
|
|
|
|
F() = setBit(F(), HC | CF, (L() + value) > 0xff);
|
|
|
|
F() = adjustParity<Z80>(F(), ((value + L()) & Mask3) ^ B());
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::outi() {
|
2018-08-12 15:25:30 +00:00
|
|
|
blockOut(HL()++, BC());
|
|
|
|
++MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::outd() {
|
2018-08-12 15:25:30 +00:00
|
|
|
blockOut(HL()--, BC());
|
|
|
|
--MEMPTR();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::otir() {
|
|
|
|
outi();
|
|
|
|
return !(F() & ZF); // See OUTI
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
bool EightBit::Z80::otdr() {
|
|
|
|
outd();
|
|
|
|
return !(F() & ZF); // See OUTD
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::rrd(uint8_t& f, register16_t address, uint8_t& update) {
|
|
|
|
(MEMPTR() = BUS().ADDRESS() = address)++;
|
2020-02-09 11:51:58 +00:00
|
|
|
const auto memory = memoryRead();
|
2019-12-29 01:18:54 +00:00
|
|
|
tick(4);
|
2020-02-09 11:51:58 +00:00
|
|
|
IntelProcessor::memoryWrite(promoteNibble(update) | highNibble(memory));
|
2019-11-09 18:58:23 +00:00
|
|
|
update = higherNibble(update) | lowerNibble(memory);
|
|
|
|
f = adjustSZPXY<Z80>(f, update);
|
|
|
|
f = clearBit(f, NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2019-11-09 18:58:23 +00:00
|
|
|
void EightBit::Z80::rld(uint8_t& f, register16_t address, uint8_t& update) {
|
|
|
|
(MEMPTR() = BUS().ADDRESS() = address)++;
|
2020-02-09 11:51:58 +00:00
|
|
|
const auto memory = memoryRead();
|
2019-12-29 01:18:54 +00:00
|
|
|
tick(4);
|
2020-02-09 11:51:58 +00:00
|
|
|
IntelProcessor::memoryWrite(promoteNibble(memory) | lowNibble(update));
|
2019-11-09 18:58:23 +00:00
|
|
|
update = higherNibble(update) | highNibble(memory);
|
|
|
|
f = adjustSZPXY<Z80>(f, update);
|
|
|
|
f = clearBit(f, NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2020-02-09 11:51:58 +00:00
|
|
|
void EightBit::Z80::portWrite(const uint8_t port) {
|
2019-12-29 01:18:54 +00:00
|
|
|
MEMPTR() = BUS().ADDRESS() = { port, A() };
|
2018-06-10 23:50:46 +00:00
|
|
|
BUS().DATA() = A();
|
2020-02-09 11:51:58 +00:00
|
|
|
portWrite();
|
2018-03-10 01:53:57 +00:00
|
|
|
++MEMPTR().low;
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2020-02-09 11:51:58 +00:00
|
|
|
void EightBit::Z80::portWrite() {
|
2020-05-03 19:45:01 +00:00
|
|
|
|
|
|
|
class _Writer final {
|
|
|
|
Z80& m_parent;
|
|
|
|
public:
|
|
|
|
_Writer(Z80& parent) : m_parent(parent) {
|
|
|
|
m_parent.WritingIO.fire(EventArgs::empty());
|
|
|
|
}
|
|
|
|
|
|
|
|
~_Writer() {
|
|
|
|
m_parent.WrittenIO.fire(EventArgs::empty());
|
|
|
|
m_parent.tick(3);
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
_Writer writer(*this);
|
|
|
|
_ActivateIORQ iorq(*this);
|
2020-02-09 11:51:58 +00:00
|
|
|
busWrite();
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2020-02-09 11:51:58 +00:00
|
|
|
uint8_t EightBit::Z80::portRead(const uint8_t port) {
|
2019-12-29 01:18:54 +00:00
|
|
|
MEMPTR() = BUS().ADDRESS() = { port, A() };
|
2018-03-10 01:53:57 +00:00
|
|
|
++MEMPTR().low;
|
2020-02-09 11:51:58 +00:00
|
|
|
return portRead();
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2020-02-09 11:51:58 +00:00
|
|
|
uint8_t EightBit::Z80::portRead() {
|
2020-05-03 19:45:01 +00:00
|
|
|
|
|
|
|
class _Reader final {
|
|
|
|
Z80& m_parent;
|
|
|
|
public:
|
|
|
|
_Reader(Z80& parent) : m_parent(parent) {
|
|
|
|
m_parent.ReadingIO.fire(EventArgs::empty());
|
|
|
|
}
|
|
|
|
|
|
|
|
~_Reader() {
|
|
|
|
m_parent.ReadIO.fire(EventArgs::empty());
|
|
|
|
m_parent.tick(3);
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
_Reader reader(*this);
|
|
|
|
_ActivateIORQ iorq(*this);
|
|
|
|
return busRead();
|
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
|
|
|
|
uint16_t EightBit::Z80::displacedAddress() {
|
|
|
|
assert(m_displaced);
|
|
|
|
return MEMPTR().word = (m_prefixDD ? IX() : IY()).word + m_displacement;
|
|
|
|
}
|
|
|
|
|
|
|
|
void EightBit::Z80::fetchDisplacement() {
|
|
|
|
m_displacement = fetchByte();
|
|
|
|
}
|
|
|
|
|
|
|
|
// ** From the Z80 CPU User Manual
|
|
|
|
|
|
|
|
// Figure 5 depicts the timing during an M1 (op code fetch) cycle. The Program Counter is
|
|
|
|
// placed on the address bus at the beginning of the M1 cycle. One half clock cycle later, the
|
|
|
|
// MREQ signal goes active. At this time, the address to memory has had time to stabilize so
|
|
|
|
// that the falling edge of MREQ can be used directly as a chip enable clock to dynamic
|
|
|
|
// memories. The RD line also goes active to indicate that the memory read data should be
|
|
|
|
// enabled onto the CPU data bus. The CPU samples the data from the memory space on the
|
|
|
|
// data bus with the rising edge of the clock of state T3, and this same edge is used by the
|
|
|
|
// CPU to turn off the RD and MREQ signals. As a result, the data is sampled by the CPU
|
|
|
|
// before the RD signal becomes inactive. Clock states T3 and T4 of a fetch cycle are used to
|
|
|
|
// refresh dynamic memories. The CPU uses this time to decode and execute the fetched
|
|
|
|
// instruction so that no other concurrent operation can be performed.
|
|
|
|
|
|
|
|
// When a software HALT instruction is executed, the CPU executes NOPs until an interrupt
|
|
|
|
// is received(either a nonmaskable or a maskable interrupt while the interrupt flip-flop is
|
|
|
|
// enabled). The two interrupt lines are sampled with the rising clock edge during each T4
|
|
|
|
// state as depicted in Figure 11.If a nonmaskable interrupt is received or a maskable interrupt
|
|
|
|
// is received and the interrupt enable flip-flop is set, then the HALT state is exited on
|
|
|
|
// the next rising clock edge.The following cycle is an interrupt acknowledge cycle corresponding
|
|
|
|
// to the type of interrupt that was received.If both are received at this time, then
|
|
|
|
// the nonmaskable interrupt is acknowledged because it is the highest priority.The purpose
|
|
|
|
// of executing NOP instructions while in the HALT state is to keep the memory refresh signals
|
|
|
|
// active.Each cycle in the HALT state is a normal M1(fetch) cycle except that the data
|
|
|
|
// received from the memory is ignored and an NOP instruction is forced internally to the
|
|
|
|
// CPU.The HALT acknowledge signal is active during this time indicating that the processor
|
|
|
|
// is in the HALT state
|
|
|
|
uint8_t EightBit::Z80::fetchOpCode() {
|
|
|
|
tick();
|
|
|
|
uint8_t returned;
|
|
|
|
{
|
|
|
|
_ActivateM1 m1(*this);
|
|
|
|
const auto halted = lowered(HALT());
|
|
|
|
returned = IntelProcessor::memoryRead(PC());
|
|
|
|
if (UNLIKELY(halted))
|
|
|
|
returned = 0; // NOP
|
|
|
|
else
|
|
|
|
PC()++;
|
|
|
|
}
|
|
|
|
BUS().ADDRESS() = { REFRESH(), IV() };
|
|
|
|
{
|
|
|
|
_ActivateRFSH rfsh(*this);
|
|
|
|
_ActivateMREQ mreq(*this);
|
|
|
|
}
|
2019-09-15 00:35:57 +00:00
|
|
|
return returned;
|
2017-06-28 14:39:31 +00:00
|
|
|
}
|
|
|
|
|
2017-06-05 21:39:15 +00:00
|
|
|
int EightBit::Z80::step() {
|
2017-11-03 22:05:01 +00:00
|
|
|
resetCycles();
|
2018-10-28 19:29:14 +00:00
|
|
|
ExecutingInstruction.fire(*this);
|
2017-12-03 00:57:47 +00:00
|
|
|
if (LIKELY(powered())) {
|
2018-10-28 19:29:14 +00:00
|
|
|
m_displaced = m_prefixCB = m_prefixDD = m_prefixED = m_prefixFD = false;
|
2019-09-08 15:28:19 +00:00
|
|
|
bool handled = false;
|
|
|
|
if (lowered(RESET())) {
|
2018-08-25 00:34:30 +00:00
|
|
|
handleRESET();
|
2019-09-08 15:28:19 +00:00
|
|
|
handled = true;
|
|
|
|
} else if (lowered(NMI())) {
|
2018-08-25 00:34:30 +00:00
|
|
|
handleNMI();
|
2019-09-08 15:28:19 +00:00
|
|
|
handled = true;
|
|
|
|
} else if (lowered(INT())) {
|
2019-11-16 23:37:57 +00:00
|
|
|
raiseINT();
|
2019-09-08 15:28:19 +00:00
|
|
|
raiseHALT();
|
|
|
|
if (IFF1()) {
|
|
|
|
handleINT();
|
|
|
|
handled = true;
|
|
|
|
}
|
2017-12-03 00:57:47 +00:00
|
|
|
}
|
2019-11-09 18:58:23 +00:00
|
|
|
if (!handled)
|
2020-05-03 19:45:01 +00:00
|
|
|
IntelProcessor::execute(fetchOpCode());
|
2017-12-03 00:57:47 +00:00
|
|
|
}
|
2018-08-25 00:34:30 +00:00
|
|
|
ExecutedInstruction.fire(*this);
|
2017-12-03 00:57:47 +00:00
|
|
|
return cycles();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-12-29 19:17:36 +00:00
|
|
|
int EightBit::Z80::execute() {
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-12-29 19:17:36 +00:00
|
|
|
const auto& decoded = getDecodedOpcode(opcode());
|
2017-06-26 22:22:32 +00:00
|
|
|
|
2017-11-18 14:29:30 +00:00
|
|
|
const auto x = decoded.x;
|
|
|
|
const auto y = decoded.y;
|
|
|
|
const auto z = decoded.z;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2017-11-18 14:29:30 +00:00
|
|
|
const auto p = decoded.p;
|
|
|
|
const auto q = decoded.q;
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_prefixCB)
|
|
|
|
executeCB(x, y, z);
|
|
|
|
else if (m_prefixED)
|
|
|
|
executeED(x, y, z, p, q);
|
|
|
|
else
|
2018-06-10 23:50:46 +00:00
|
|
|
executeOther(x, y, z, p, q);
|
2017-06-04 20:38:34 +00:00
|
|
|
|
2018-03-10 01:53:57 +00:00
|
|
|
ASSUME(cycles() > 0);
|
2017-11-03 22:05:01 +00:00
|
|
|
return cycles();
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::executeCB(const int x, const int y, const int z) {
|
2019-12-29 01:18:54 +00:00
|
|
|
|
2018-11-25 10:38:30 +00:00
|
|
|
const bool memoryZ = z == 6;
|
2018-12-01 13:01:33 +00:00
|
|
|
const bool indirect = (!m_displaced && memoryZ) || m_displaced;
|
2019-12-29 01:18:54 +00:00
|
|
|
const bool direct = !indirect;
|
|
|
|
|
|
|
|
uint8_t operand;
|
|
|
|
if (m_displaced) {
|
|
|
|
tick(2);
|
2020-02-09 11:51:58 +00:00
|
|
|
operand = IntelProcessor::memoryRead(displacedAddress());
|
2019-12-29 01:18:54 +00:00
|
|
|
} else {
|
|
|
|
operand = R(z);
|
|
|
|
}
|
|
|
|
|
2018-12-01 13:01:33 +00:00
|
|
|
const bool update = x != 1; // BIT does not update
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
2017-08-06 16:06:48 +00:00
|
|
|
case 0: { // rot[y] r[z]
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2019-11-09 18:58:23 +00:00
|
|
|
operand = rlc(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2019-11-09 18:58:23 +00:00
|
|
|
operand = rrc(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2019-11-09 18:58:23 +00:00
|
|
|
operand = rl(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
2019-11-09 18:58:23 +00:00
|
|
|
operand = rr(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2019-11-09 18:58:23 +00:00
|
|
|
operand = sla(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2019-11-09 18:58:23 +00:00
|
|
|
operand = sra(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6:
|
2019-11-09 18:58:23 +00:00
|
|
|
operand = sll(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7:
|
2019-11-09 18:58:23 +00:00
|
|
|
operand = srl(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-08-08 12:38:27 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2019-11-09 18:58:23 +00:00
|
|
|
F() = adjustSZP<Z80>(F(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-08-06 16:06:48 +00:00
|
|
|
} case 1: // BIT y, r[z]
|
2019-11-09 18:58:23 +00:00
|
|
|
bit(F(), y, operand);
|
2019-12-29 01:18:54 +00:00
|
|
|
F() = adjustXY<Z80>(F(), direct ? operand : MEMPTR().high);
|
2020-02-22 08:32:29 +00:00
|
|
|
if (memoryZ)
|
|
|
|
tick();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // RES y, r[z]
|
2018-12-01 13:01:33 +00:00
|
|
|
operand = res(y, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SET y, r[z]
|
2018-12-01 13:01:33 +00:00
|
|
|
operand = set(y, operand);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE;
|
|
|
|
}
|
2019-09-14 14:04:46 +00:00
|
|
|
if (update) {
|
2019-12-29 01:18:54 +00:00
|
|
|
tick();
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_displaced) {
|
2020-02-09 11:51:58 +00:00
|
|
|
IntelProcessor::memoryWrite(operand);
|
2019-09-14 14:04:46 +00:00
|
|
|
if (!memoryZ)
|
2019-08-16 20:56:48 +00:00
|
|
|
R2(z, operand);
|
2019-09-14 14:04:46 +00:00
|
|
|
} else {
|
|
|
|
R(z, operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::executeED(const int x, const int y, const int z, const int p, const int q) {
|
2019-12-29 01:18:54 +00:00
|
|
|
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0:
|
|
|
|
case 3: // Invalid instruction, equivalent to NONI followed by NOP
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Input from port with 16-bit address
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = BC())++;
|
2020-02-09 11:51:58 +00:00
|
|
|
portRead();
|
2019-09-14 14:04:46 +00:00
|
|
|
if (y != 6) // IN r[y],(C)
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, BUS().DATA());
|
2019-11-09 18:58:23 +00:00
|
|
|
F() = adjustSZPXY<Z80>(F(), BUS().DATA());
|
|
|
|
F() = clearBit(F(), NF | HC);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // Output to port with 16-bit address
|
2018-10-28 13:33:36 +00:00
|
|
|
(MEMPTR() = BUS().ADDRESS() = BC())++;
|
2019-12-29 01:18:54 +00:00
|
|
|
BUS().DATA() = y == 6 ? 0 : R(y);
|
2020-02-09 11:51:58 +00:00
|
|
|
portWrite();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // 16-bit add/subtract with carry
|
|
|
|
switch (q) {
|
|
|
|
case 0: // SBC HL, rp[p]
|
2019-11-09 18:58:23 +00:00
|
|
|
HL2() = sbc(F(), HL2(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC HL, rp[p]
|
2019-11-09 18:58:23 +00:00
|
|
|
HL2() = adc(F(), HL2(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // Retrieve/store register pair from/to immediate address
|
2018-08-17 12:59:59 +00:00
|
|
|
BUS().ADDRESS() = fetchWord();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (q) {
|
2018-03-18 22:40:23 +00:00
|
|
|
case 0: // LD (nn), rp[p]
|
2018-01-10 23:08:14 +00:00
|
|
|
setWord(RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD rp[p], (nn)
|
2018-02-25 19:48:01 +00:00
|
|
|
RP(p) = getWord();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 4: // Negate accumulator
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = neg(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // Return from interrupt
|
|
|
|
switch (y) {
|
|
|
|
case 1:
|
|
|
|
reti(); // RETI
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
retn(); // RETN
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 6: // Set interrupt mode
|
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2018-12-01 13:01:33 +00:00
|
|
|
case 1:
|
2017-06-04 20:38:34 +00:00
|
|
|
case 4:
|
2018-12-01 13:01:33 +00:00
|
|
|
case 5:
|
2017-06-04 20:38:34 +00:00
|
|
|
IM() = 0;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
case 6:
|
|
|
|
IM() = 1;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
case 7:
|
|
|
|
IM() = 2;
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 7: // Assorted ops
|
|
|
|
switch (y) {
|
|
|
|
case 0: // LD I,A
|
2018-06-10 23:50:46 +00:00
|
|
|
IV() = A();
|
2020-02-22 08:32:29 +00:00
|
|
|
tick();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD R,A
|
2018-06-10 23:50:46 +00:00
|
|
|
REFRESH() = A();
|
2020-02-22 08:32:29 +00:00
|
|
|
tick();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // LD A,I
|
2020-05-03 19:45:01 +00:00
|
|
|
readInternalRegister([this]() { return IV(); });
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // LD A,R
|
2020-05-03 19:45:01 +00:00
|
|
|
readInternalRegister([this]() { return REFRESH(); });
|
2020-02-22 08:32:29 +00:00
|
|
|
tick();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // RRD
|
2019-11-09 18:58:23 +00:00
|
|
|
rrd(F(), HL(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // RLD
|
2019-11-09 18:58:23 +00:00
|
|
|
rld(F(), HL(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // NOP
|
|
|
|
case 7: // NOP
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // LD
|
|
|
|
switch (y) {
|
|
|
|
case 4: // LDI
|
2019-11-09 18:58:23 +00:00
|
|
|
ldi(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // LDD
|
2019-11-09 18:58:23 +00:00
|
|
|
ldd(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // LDIR
|
2019-11-09 18:58:23 +00:00
|
|
|
if (ldir(F(), A())) {
|
2018-08-11 20:19:19 +00:00
|
|
|
MEMPTR() = --PC();
|
|
|
|
--PC();
|
2020-02-22 08:32:29 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // LDDR
|
2019-11-09 18:58:23 +00:00
|
|
|
if (lddr(F(), A())) {
|
2018-08-17 12:59:59 +00:00
|
|
|
MEMPTR() = --PC();
|
2018-08-11 20:19:19 +00:00
|
|
|
--PC();
|
2020-02-22 08:32:29 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // CP
|
|
|
|
switch (y) {
|
|
|
|
case 4: // CPI
|
2019-11-09 18:58:23 +00:00
|
|
|
cpi(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // CPD
|
2019-11-09 18:58:23 +00:00
|
|
|
cpd(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // CPIR
|
2019-11-09 18:58:23 +00:00
|
|
|
if (cpir(F(), A())) {
|
2018-08-17 12:59:59 +00:00
|
|
|
MEMPTR() = --PC();
|
2018-08-11 20:19:19 +00:00
|
|
|
--PC();
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CPDR
|
2019-11-09 18:58:23 +00:00
|
|
|
if (cpdr(F(), A())) {
|
2020-11-09 11:48:59 +00:00
|
|
|
MEMPTR() = PC() - 2;
|
|
|
|
//MEMPTR() = --PC();
|
|
|
|
//--PC();
|
2020-02-22 08:32:29 +00:00
|
|
|
tick(5);
|
2018-04-11 22:53:26 +00:00
|
|
|
} else {
|
2018-08-11 20:19:19 +00:00
|
|
|
MEMPTR() = PC() - 2;
|
2020-02-22 08:32:29 +00:00
|
|
|
tick(2);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // IN
|
|
|
|
switch (y) {
|
|
|
|
case 4: // INI
|
2018-06-10 23:50:46 +00:00
|
|
|
ini();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // IND
|
2018-06-10 23:50:46 +00:00
|
|
|
ind();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // INIR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (inir()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
PC() -= 2;
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // INDR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (indr()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
PC() -= 2;
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // OUT
|
|
|
|
switch (y) {
|
|
|
|
case 4: // OUTI
|
2018-06-10 23:50:46 +00:00
|
|
|
outi();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // OUTD
|
2018-06-10 23:50:46 +00:00
|
|
|
outd();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OTIR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (otir()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
PC() -= 2;
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // OTDR
|
2019-09-14 14:04:46 +00:00
|
|
|
if (otdr()) {
|
2018-08-11 20:19:19 +00:00
|
|
|
PC() -= 2;
|
2019-01-09 23:24:33 +00:00
|
|
|
tick(5);
|
2017-06-14 21:33:02 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-10 23:50:46 +00:00
|
|
|
void EightBit::Z80::executeOther(const int x, const int y, const int z, const int p, const int q) {
|
2018-11-25 10:38:30 +00:00
|
|
|
const bool memoryY = y == 6;
|
|
|
|
const bool memoryZ = z == 6;
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (x) {
|
|
|
|
case 0:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Relative jumps and assorted ops
|
|
|
|
switch (y) {
|
|
|
|
case 0: // NOP
|
|
|
|
break;
|
|
|
|
case 1: // EX AF AF'
|
|
|
|
exxAF();
|
|
|
|
break;
|
|
|
|
case 2: // DJNZ d
|
2019-12-29 01:18:54 +00:00
|
|
|
tick();
|
2020-02-16 09:18:34 +00:00
|
|
|
jrConditional(--B());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // JR d
|
2017-06-11 20:08:40 +00:00
|
|
|
jr(fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-07-19 12:59:28 +00:00
|
|
|
case 4: // JR cc,d
|
|
|
|
case 5:
|
|
|
|
case 6:
|
|
|
|
case 7:
|
2019-12-29 01:18:54 +00:00
|
|
|
jrConditionalFlag(F(), y - 4);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-07-19 12:59:28 +00:00
|
|
|
default:
|
2017-10-29 19:48:47 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // 16-bit load immediate/add
|
|
|
|
switch (q) {
|
2017-06-07 21:54:55 +00:00
|
|
|
case 0: // LD rp,nn
|
2018-02-25 19:48:01 +00:00
|
|
|
RP(p) = fetchWord();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADD HL,rp
|
2019-11-09 18:58:23 +00:00
|
|
|
HL2() = add(F(), HL2(), RP(p));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // Indirect loading
|
|
|
|
switch (q) {
|
|
|
|
case 0:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // LD (BC),A
|
2020-05-03 19:45:01 +00:00
|
|
|
storeAccumulatorIndirect([this]() { return BC(); });
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD (DE),A
|
2020-05-03 19:45:01 +00:00
|
|
|
storeAccumulatorIndirect([this]() { return DE(); });
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // LD (nn),HL
|
2018-08-17 12:59:59 +00:00
|
|
|
BUS().ADDRESS() = fetchWord();
|
2018-01-10 23:08:14 +00:00
|
|
|
setWord(HL2());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // LD (nn),A
|
2020-05-03 19:45:01 +00:00
|
|
|
storeAccumulatorIndirect([this]() { return fetchWord(); });
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // LD A,(BC)
|
2020-05-03 19:45:01 +00:00
|
|
|
loadAccumulatorIndirect([this]() { return BC(); });
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // LD A,(DE)
|
2020-05-03 19:45:01 +00:00
|
|
|
loadAccumulatorIndirect([this]() { return DE(); });
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // LD HL,(nn)
|
2018-08-17 12:59:59 +00:00
|
|
|
BUS().ADDRESS() = fetchWord();
|
2018-02-25 19:48:01 +00:00
|
|
|
HL2() = getWord();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // LD A,(nn)
|
2020-05-03 19:45:01 +00:00
|
|
|
loadAccumulatorIndirect([this]() { return fetchWord(); });
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // 16-bit INC/DEC
|
|
|
|
switch (q) {
|
|
|
|
case 0: // INC rp
|
2018-08-11 20:19:19 +00:00
|
|
|
++RP(p);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // DEC rp
|
2018-08-11 20:19:19 +00:00
|
|
|
--RP(p);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2020-02-16 09:18:34 +00:00
|
|
|
tick(2);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2019-12-29 01:18:54 +00:00
|
|
|
case 4: { // 8-bit INC
|
|
|
|
if (memoryY && m_displaced) {
|
2017-08-06 16:06:48 +00:00
|
|
|
fetchDisplacement();
|
2019-12-29 01:18:54 +00:00
|
|
|
tick(5);
|
2018-04-14 08:39:06 +00:00
|
|
|
}
|
2019-12-29 01:18:54 +00:00
|
|
|
const auto original = R(y);
|
2020-02-16 09:18:34 +00:00
|
|
|
if (memoryY)
|
|
|
|
tick();
|
2019-12-29 01:18:54 +00:00
|
|
|
R(y, increment(F(), original));
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2019-12-29 01:18:54 +00:00
|
|
|
}
|
|
|
|
case 5: { // 8-bit DEC
|
|
|
|
if (memoryY && m_displaced) {
|
|
|
|
fetchDisplacement();
|
|
|
|
tick(5);
|
2018-04-14 08:39:06 +00:00
|
|
|
}
|
2019-12-29 01:18:54 +00:00
|
|
|
const auto original = R(y);
|
2020-02-16 09:18:34 +00:00
|
|
|
if (memoryY)
|
|
|
|
tick();
|
2019-12-29 01:18:54 +00:00
|
|
|
R(y, decrement(F(), original));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 6: { // 8-bit load immediate
|
|
|
|
if (memoryY && m_displaced)
|
|
|
|
fetchDisplacement();
|
|
|
|
const auto value = fetchByte();
|
|
|
|
if (m_displaced)
|
|
|
|
tick(2);
|
|
|
|
R(y, value); // LD r,n
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2019-12-29 01:18:54 +00:00
|
|
|
}
|
2017-08-06 16:06:48 +00:00
|
|
|
case 7: // Assorted operations on accumulator/flags
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0:
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = rlc(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = rrc(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = rl(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = rr(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = daa(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = cpl(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6:
|
2019-11-09 18:58:23 +00:00
|
|
|
scf(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7:
|
2019-11-09 18:58:23 +00:00
|
|
|
ccf(F(), A());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // 8-bit loading
|
2019-09-14 14:04:46 +00:00
|
|
|
if ((memoryZ && memoryY)) { // Exception (replaces LD (HL), (HL))
|
|
|
|
lowerHALT();
|
|
|
|
} else {
|
2017-06-04 20:38:34 +00:00
|
|
|
bool normal = true;
|
2019-09-14 14:04:46 +00:00
|
|
|
if (m_displaced) {
|
|
|
|
if (memoryZ || memoryY)
|
2017-08-06 16:06:48 +00:00
|
|
|
fetchDisplacement();
|
2018-11-25 10:38:30 +00:00
|
|
|
if (memoryZ) {
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 4:
|
2019-12-29 01:18:54 +00:00
|
|
|
if (m_displaced)
|
|
|
|
tick(5);
|
2018-06-10 23:50:46 +00:00
|
|
|
H() = R(z);
|
2017-06-04 20:38:34 +00:00
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
case 5:
|
2019-12-29 01:18:54 +00:00
|
|
|
if (m_displaced)
|
|
|
|
tick(5);
|
2018-06-10 23:50:46 +00:00
|
|
|
L() = R(z);
|
2017-06-04 20:38:34 +00:00
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2018-11-25 10:38:30 +00:00
|
|
|
if (memoryY) {
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (z) {
|
|
|
|
case 4:
|
2019-12-29 01:18:54 +00:00
|
|
|
if (m_displaced)
|
|
|
|
tick(5);
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, H());
|
2017-06-04 20:38:34 +00:00
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
case 5:
|
2019-12-29 01:18:54 +00:00
|
|
|
if (m_displaced)
|
|
|
|
tick(5);
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, L());
|
2017-06-04 20:38:34 +00:00
|
|
|
normal = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-12-29 01:18:54 +00:00
|
|
|
if (normal) {
|
|
|
|
if (m_displaced)
|
|
|
|
tick(5);
|
2018-06-10 23:50:46 +00:00
|
|
|
R(y, R(z));
|
2019-12-29 01:18:54 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2018-06-16 09:09:28 +00:00
|
|
|
case 2: { // Operate on accumulator and register/memory location
|
2019-12-29 01:18:54 +00:00
|
|
|
if (memoryZ && m_displaced) {
|
|
|
|
fetchDisplacement();
|
|
|
|
tick(5);
|
2018-04-14 08:39:06 +00:00
|
|
|
}
|
2018-06-16 09:09:28 +00:00
|
|
|
const auto value = R(z);
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0: // ADD A,r
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = add(F(), A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC A,r
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = adc(F(), A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // SUB r
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = sub(F(), A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SBC A,r
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = sbc(F(), A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // AND r
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = andr(F(), A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // XOR r
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = xorr(F(), A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OR r
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = orr(F(), A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CP r
|
2019-11-09 18:58:23 +00:00
|
|
|
compare(F(), A(), value);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2018-06-16 09:09:28 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
case 3:
|
|
|
|
switch (z) {
|
|
|
|
case 0: // Conditional return
|
2019-12-29 01:18:54 +00:00
|
|
|
returnConditionalFlag(F(), y);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // POP & various ops
|
|
|
|
switch (q) {
|
|
|
|
case 0: // POP rp2[p]
|
2018-02-25 19:48:01 +00:00
|
|
|
RP2(p) = popWord();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // RET
|
|
|
|
ret();
|
|
|
|
break;
|
|
|
|
case 1: // EXX
|
|
|
|
exx();
|
|
|
|
break;
|
2019-09-08 20:27:35 +00:00
|
|
|
case 2: // JP (HL)
|
2018-04-11 22:53:26 +00:00
|
|
|
jump(HL2());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // LD SP,HL
|
2017-06-19 12:53:00 +00:00
|
|
|
SP() = HL2();
|
2020-02-22 08:32:29 +00:00
|
|
|
tick(2);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2017-06-29 20:25:58 +00:00
|
|
|
break;
|
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2: // Conditional jump
|
2019-11-09 18:58:23 +00:00
|
|
|
jumpConditionalFlag(F(), y);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // Assorted operations
|
|
|
|
switch (y) {
|
|
|
|
case 0: // JP nn
|
2018-03-18 22:40:23 +00:00
|
|
|
jump(MEMPTR() = fetchWord());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // CB prefix
|
|
|
|
m_prefixCB = true;
|
2019-11-09 18:58:23 +00:00
|
|
|
if (m_displaced) {
|
2017-08-06 16:06:48 +00:00
|
|
|
fetchDisplacement();
|
2020-02-09 11:51:58 +00:00
|
|
|
IntelProcessor::execute(fetchByte());
|
2019-11-09 18:58:23 +00:00
|
|
|
} else {
|
2020-05-03 19:45:01 +00:00
|
|
|
IntelProcessor::execute(fetchOpCode());
|
2019-11-09 18:58:23 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // OUT (n),A
|
2020-02-09 11:51:58 +00:00
|
|
|
portWrite(fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // IN A,(n)
|
2020-02-09 11:51:58 +00:00
|
|
|
A() = portRead(fetchByte());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // EX (SP),HL
|
2019-08-16 20:56:48 +00:00
|
|
|
xhtl(HL2());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // EX DE,HL
|
|
|
|
std::swap(DE(), HL());
|
|
|
|
break;
|
|
|
|
case 6: // DI
|
2017-06-11 20:08:40 +00:00
|
|
|
di();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // EI
|
2017-06-11 20:08:40 +00:00
|
|
|
ei();
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 4: // Conditional call: CALL cc[y], nn
|
2019-12-29 01:18:54 +00:00
|
|
|
callConditionalFlag(F(), y);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // PUSH & various ops
|
|
|
|
switch (q) {
|
|
|
|
case 0: // PUSH rp2[p]
|
|
|
|
pushWord(RP2(p));
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
switch (p) {
|
|
|
|
case 0: // CALL nn
|
2018-03-18 22:40:23 +00:00
|
|
|
call(MEMPTR() = fetchWord());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // DD prefix
|
2017-06-15 21:21:26 +00:00
|
|
|
m_displaced = m_prefixDD = true;
|
2020-05-03 19:45:01 +00:00
|
|
|
IntelProcessor::execute(fetchOpCode());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // ED prefix
|
|
|
|
m_prefixED = true;
|
2020-05-03 19:45:01 +00:00
|
|
|
IntelProcessor::execute(fetchOpCode());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // FD prefix
|
2017-06-15 21:21:26 +00:00
|
|
|
m_displaced = m_prefixFD = true;
|
2020-05-03 19:45:01 +00:00
|
|
|
IntelProcessor::execute(fetchOpCode());
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
2017-06-29 20:25:58 +00:00
|
|
|
break;
|
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2018-06-16 09:09:28 +00:00
|
|
|
case 6: { // Operate on accumulator and immediate operand: alu[y] n
|
|
|
|
const auto operand = fetchByte();
|
2017-06-04 20:38:34 +00:00
|
|
|
switch (y) {
|
|
|
|
case 0: // ADD A,n
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = add(F(), A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 1: // ADC A,n
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = adc(F(), A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 2: // SUB n
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = sub(F(), A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 3: // SBC A,n
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = sbc(F(), A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 4: // AND n
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = andr(F(), A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 5: // XOR n
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = xorr(F(), A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 6: // OR n
|
2019-11-09 18:58:23 +00:00
|
|
|
A() = orr(F(), A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
|
|
|
case 7: // CP n
|
2019-11-09 18:58:23 +00:00
|
|
|
compare(F(), A(), operand);
|
2017-06-04 20:38:34 +00:00
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
2018-06-16 09:09:28 +00:00
|
|
|
}
|
2017-06-04 20:38:34 +00:00
|
|
|
case 7: // Restart: RST y * 8
|
|
|
|
restart(y << 3);
|
|
|
|
break;
|
2017-06-28 14:39:31 +00:00
|
|
|
default:
|
2017-10-29 18:47:23 +00:00
|
|
|
UNREACHABLE;
|
2017-06-04 20:38:34 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2017-08-30 22:17:34 +00:00
|
|
|
}
|