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https://github.com/MoleskiCoder/EightBit.git
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More MC6809 disassembly corrections: tabs and pshu/s puls/u stack order.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon
parent
f6cd8a4277
commit
0c174afc02
@ -74,8 +74,11 @@ namespace EightBit {
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//
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std::string stackS(std::string mnemomic);
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std::string stackU(std::string mnemomic);
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std::string stackX(std::string mnemomic, std::string upon);
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std::string pulS();
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std::string pulU();
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std::string pshS();
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std::string pshU();
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std::string pulX(std::string mnemomic, std::string upon);
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std::string pshX(std::string mnemomic, std::string upon);
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};
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}
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@ -186,15 +186,15 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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// ASL/LSL
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case 0x08: output << Address_direct("ASL"); break; // ASL (direct)
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case 0x48: output << "\tASLA"; break; // ASL (ASLA inherent)
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case 0x58: output << "\tASLB"; break; // ASL (ASLB inherent)
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case 0x48: output << "\tASLA\t"; break; // ASL (ASLA inherent)
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case 0x58: output << "\tASLB\t"; break; // ASL (ASLB inherent)
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case 0x68: output << Address_indexed("ASL"); break; // ASL (indexed)
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case 0x78: output << Address_extended("ASL"); break; // ASL (extended)
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// ASR
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case 0x07: output << Address_direct("ASR"); break; // ASR (direct)
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case 0x47: output << "\tASRA"; break; // ASR (ASRA inherent)
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case 0x57: output << "\tASRB"; break; // ASR (ASRB inherent)
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case 0x47: output << "\tASRA\t"; break; // ASR (ASRA inherent)
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case 0x57: output << "\tASRB\t"; break; // ASR (ASRB inherent)
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case 0x67: output << Address_indexed("ASR"); break; // ASR (indexed)
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case 0x77: output << Address_extended("ASR"); break; // ASR (extended)
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@ -211,8 +211,8 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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// CLR
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case 0x0f: output << Address_direct("CLR"); break; // CLR (direct)
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case 0x4f: output << "\tCLRA"; break; // CLR (CLRA implied)
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case 0x5f: output << "\tCLRB"; break; // CLR (CLRB implied)
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case 0x4f: output << "\tCLRA\t"; break; // CLR (CLRA implied)
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case 0x5f: output << "\tCLRB\t"; break; // CLR (CLRB implied)
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case 0x6f: output << Address_indexed("CLR"); break; // CLR (indexed)
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case 0x7f: output << Address_extended("CLR"); break; // CLR (extended)
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@ -238,8 +238,8 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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// COM
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case 0x03: output << Address_direct("COM"); break; // COM (direct)
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case 0x43: output << "\tCOMA"; break; // COM (COMA inherent)
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case 0x53: output << "\tCOMB"; break; // COM (COMB inherent)
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case 0x43: output << "\tCOMA\t"; break; // COM (COMA inherent)
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case 0x53: output << "\tCOMB\t"; break; // COM (COMB inherent)
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case 0x63: output << Address_indexed("COM"); break; // COM (indexed)
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case 0x73: output << Address_extended("COM"); break; // COM (extended)
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@ -251,8 +251,8 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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// DEC
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case 0x0a: output << Address_direct("DEC"); break; // DEC (direct)
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case 0x4a: output << "\tDECA"; break; // DEC (DECA inherent)
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case 0x5a: output << "\tDECB"; break; // DEC (DECB inherent)
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case 0x4a: output << "\tDECA\t"; break; // DEC (DECA inherent)
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case 0x5a: output << "\tDECB\t"; break; // DEC (DECB inherent)
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case 0x6a: output << Address_indexed("DEC"); break; // DEC (indexed)
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case 0x7a: output << Address_extended("DEC"); break; // DEC (extended)
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@ -275,8 +275,8 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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// INC
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case 0x0c: output << Address_direct("INC"); break; // INC (direct)
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case 0x4c: output << "\tINCA";; break; // INC (INCA inherent)
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case 0x5c: output << "\tINCB";; break; // INC (INCB inherent)
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case 0x4c: output << "\tINCA\t";; break; // INC (INCA inherent)
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case 0x5c: output << "\tINCB\t";; break; // INC (INCB inherent)
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case 0x6c: output << Address_indexed("INC"); break; // INC (indexed)
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case 0x7c: output << Address_extended("INC"); break; // INC (extended)
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@ -330,23 +330,23 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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// LSR
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case 0x04: output << Address_direct("LSR"); break; // LSR (direct)
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case 0x44: output << "\tLSRA"; break; // LSR (LSRA inherent)
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case 0x54: output << "\tLSRB";; break; // LSR (LSRB inherent)
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case 0x44: output << "\tLSRA\t"; break; // LSR (LSRA inherent)
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case 0x54: output << "\tLSRB\t"; break; // LSR (LSRB inherent)
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case 0x64: output << Address_indexed("LSR"); break; // LSR (indexed)
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case 0x74: output << Address_extended("LSR"); break; // LSR (extended)
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// MUL
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case 0x3d: output << "\tMUL";; break; // MUL (inherent)
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case 0x3d: output << "\tMUL\t"; break; // MUL (inherent)
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// NEG
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case 0x00: output << Address_direct("NEG"); break; // NEG (direct)
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case 0x40: output << "\tNEGA"; break; // NEG (NEGA, inherent)
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case 0x50: output << "\tNEGB"; break; // NEG (NEGB, inherent)
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case 0x40: output << "\tNEGA\t"; break; // NEG (NEGA, inherent)
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case 0x50: output << "\tNEGB\t"; break; // NEG (NEGB, inherent)
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case 0x60: output << Address_indexed("NEG"); break; // NEG (indexed)
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case 0x70: output << Address_extended("NEG"); break; // NEG (extended)
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// NOP
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case 0x12: output << "\tNOP"; break; // NOP (inherent)
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case 0x12: output << "\tNOP\t"; break; // NOP (inherent)
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// OR
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@ -366,32 +366,32 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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case 0x1a: output << AM_immediate_byte("ORCC"); break; // OR (ORCC immediate)
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// PSH
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case 0x34: output << stackS("PSHS"); break; // PSH (PSHS immediate)
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case 0x36: output << stackU("PSHU"); break; // PSH (PSHU immediate)
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case 0x34: output << pshS(); break; // PSH (PSHS immediate)
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case 0x36: output << pshU(); break; // PSH (PSHU immediate)
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// PUL
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case 0x35: output << stackS("PULS"); break; // PUL (PULS immediate)
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case 0x37: output << stackU("PULU"); break; // PUL (PULU immediate)
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case 0x35: output << pulS(); break; // PUL (PULS immediate)
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case 0x37: output << pulU(); break; // PUL (PULU immediate)
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// ROL
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case 0x09: output << Address_direct("ROL"); break; // ROL (direct)
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case 0x49: output << "\tROLA"; break; // ROL (ROLA inherent)
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case 0x59: output << "\tROLB"; break; // ROL (ROLB inherent)
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case 0x49: output << "\tROLA\t"; break; // ROL (ROLA inherent)
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case 0x59: output << "\tROLB\t"; break; // ROL (ROLB inherent)
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case 0x69: output << Address_indexed("ROL"); break; // ROL (indexed)
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case 0x79: output << Address_extended("ROL"); break; // ROL (extended)
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// ROR
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case 0x06: output << Address_direct("ROR"); break; // ROR (direct)
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case 0x46: output << "\tRORA"; break; // ROR (RORA inherent)
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case 0x56: output << "\tRORB"; break; // ROR (RORB inherent)
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case 0x46: output << "\tRORA\t"; break; // ROR (RORA inherent)
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case 0x56: output << "\tRORB\t"; break; // ROR (RORB inherent)
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case 0x66: output << Address_indexed("ROR"); break; // ROR (indexed)
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case 0x76: output << Address_extended("ROR"); break; // ROR (extended)
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// RTI
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case 0x3B: output << "\tRTI"; break; // RTI (inherent)
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case 0x3B: output << "\tRTI\t"; break; // RTI (inherent)
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// RTS
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case 0x39: output << "\tRTS";; break; // RTS (inherent)
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case 0x39: output << "\tRTS\t"; break; // RTS (inherent)
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// SBC
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@ -408,7 +408,7 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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case 0xf2: output << Address_extended("SBCB"); break; // SBC (SBCB extended)
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// SEX
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case 0x1d: output << "\tSEX"; break; // SEX (inherent)
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case 0x1d: output << "\tSEX\t"; break; // SEX (inherent)
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// ST
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@ -458,18 +458,18 @@ std::string EightBit::Disassembly::disassembleUnprefixed() {
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case 0xb3: output << Address_extended("SUBD"); break; // SUB (SUBD extended)
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// SWI
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case 0x3f: output << "\tSWI"; break; // SWI (inherent)
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case 0x3f: output << "\tSWI\t"; break; // SWI (inherent)
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// SYNC
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case 0x13: output << "\tSYNC"; break; // SYNC (inherent)
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case 0x13: output << "\tSYNC\t"; break; // SYNC (inherent)
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// TFR
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case 0x1f: output << tfr("TFR"); break; // TFR (immediate)
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// TST
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case 0x0d: output << Address_direct("TST"); break; // TST (direct)
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case 0x4d: output << "\tTSTA"; break; // TST (TSTA inherent)
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case 0x5d: output << "\tTSTB"; break; // TST (TSTB inherent)
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case 0x4d: output << "\tTSTA\t"; break; // TST (TSTA inherent)
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case 0x5d: output << "\tTSTB\t"; break; // TST (TSTB inherent)
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case 0x6d: output << Address_indexed("TST"); break; // TST (indexed)
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case 0x7d: output << Address_extended("TST"); break; // TST (extended)
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@ -569,7 +569,7 @@ std::string EightBit::Disassembly::disassemble10() {
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case 0xbf: output << Address_extended("STY"); break; // ST (STY extended)
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// SWI
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case 0x3f: output << "\tSWI2";; break; // SWI (SWI2 inherent)
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case 0x3f: output << "\tSWI2\t"; break; // SWI (SWI2 inherent)
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default:
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UNREACHABLE;
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@ -604,7 +604,7 @@ std::string EightBit::Disassembly::disassemble11() {
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case 0xbc: output << Address_extended("CMPS"); break; // CMP (CMPS, extended)
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// SWI
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case 0x3f: output << "\tSWI3"; break; // SWI (SWI3 inherent)
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case 0x3f: output << "\tSWI3\t"; break; // SWI (SWI3 inherent)
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default:
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UNREACHABLE;
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@ -887,15 +887,23 @@ uint16_t EightBit::Disassembly::getWord(uint16_t address) {
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//
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std::string EightBit::Disassembly::stackS(std::string mnemomic) {
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return stackX(mnemomic, "U");
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std::string EightBit::Disassembly::pulS() {
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return pulX("PULS", "U");
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}
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std::string EightBit::Disassembly::stackU(std::string mnemomic) {
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return stackX(mnemomic, "S");
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std::string EightBit::Disassembly::pulU() {
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return pulX("PULU", "S");
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}
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std::string EightBit::Disassembly::stackX(std::string mnemomic, std::string upon) {
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std::string EightBit::Disassembly::pshS() {
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return pshX("PSHS", "U");
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}
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std::string EightBit::Disassembly::pshU() {
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return pshX("PSHU", "S");
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}
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std::string EightBit::Disassembly::pulX(std::string mnemomic, std::string upon) {
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const auto data = getByte(++m_address);
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std::ostringstream output;
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output
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@ -926,3 +934,35 @@ std::string EightBit::Disassembly::stackX(std::string mnemomic, std::string upon
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}
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return output.str();
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}
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std::string EightBit::Disassembly::pshX(std::string mnemomic, std::string upon) {
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const auto data = getByte(++m_address);
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std::ostringstream output;
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output
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<< dump_ByteValue(data)
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<< "\t" << mnemomic << "\t";
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std::vector<std::string> registers;
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if (data & Chip::Bit7)
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registers.push_back("PC");
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if (data & Chip::Bit6)
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registers.push_back(upon);
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if (data & Chip::Bit5)
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registers.push_back("Y");
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if (data & Chip::Bit4)
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registers.push_back("X");
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if (data & Chip::Bit3)
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registers.push_back("DP");
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if (data & Chip::Bit2)
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registers.push_back("B");
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if (data & Chip::Bit1)
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registers.push_back("A");
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if (data & Chip::Bit0)
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registers.push_back("CC");
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for (int i = 0; i < registers.size(); ++i) {
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const bool last = i == registers.size() - 1;
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output << registers[i];
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if (!last)
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output << ",";
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}
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return output.str();
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}
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