From 246e6431ab333dce2df48f3ad74840c06dd1407a Mon Sep 17 00:00:00 2001 From: "Adrian.Conlon" Date: Fri, 25 Aug 2017 10:33:22 +0100 Subject: [PATCH] Small correction to GB SP instructions passes a little more of the Blargg tests. Signed-off-by: Adrian.Conlon --- .../fusetest_LR35902/fuse-tests/tests.expected | 4 ++-- LR35902/src/LR35902.cpp | 18 ++++++++++-------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/LR35902/fusetest_LR35902/fuse-tests/tests.expected b/LR35902/fusetest_LR35902/fuse-tests/tests.expected index cc6c679..d9a270d 100644 --- a/LR35902/fusetest_LR35902/fuse-tests/tests.expected +++ b/LR35902/fusetest_LR35902/fuse-tests/tests.expected @@ -4949,7 +4949,7 @@ f8_1 0 MC 0000 4 MR 0000 f8 4 MC 0001 -0010 0000 0000 0000 fffe 0002 +0030 0000 0000 0000 fffe 0002 0 5 @@ -4957,7 +4957,7 @@ f8_2 0 MC 0000 4 MR 0000 f8 4 MC 0001 -0000 0000 0000 0fff 1000 0002 +0010 0000 0000 0fff 1000 0002 0 5 diff --git a/LR35902/src/LR35902.cpp b/LR35902/src/LR35902.cpp index da7e581..944cbfe 100644 --- a/LR35902/src/LR35902.cpp +++ b/LR35902/src/LR35902.cpp @@ -686,13 +686,14 @@ void EightBit::LR35902::executeOther(int x, int y, int z, int p, int q) { cycles += 3; break; case 5: { // GB: ADD SP,dd - auto before = SP(); + auto before = SP().word; auto value = fetchByte(); - auto result = SP().word + (int8_t)value; + auto result = before + (int8_t)value; SP().word = result; + auto carried = before ^ value ^ result; clearFlag(f, ZF | NF); - setFlag(f, CF, result & Bit16); - adjustHalfCarryAdd(f, before.high, value, SP().high); + setFlag(f, CF, carried & 0x100); + setFlag(f, HC, carried & 0x10); } cycles += 4; break; @@ -701,13 +702,14 @@ void EightBit::LR35902::executeOther(int x, int y, int z, int p, int q) { cycles += 3; break; case 7: { // GB: LD HL,SP + dd - auto before = HL(); + auto before = SP().word; auto value = fetchByte(); - auto result = SP().word + (int8_t)value; + auto result = before + (int8_t)value; HL().word = result; + auto carried = before ^ value ^ result; clearFlag(f, ZF | NF); - setFlag(f, CF, result & Bit16); - adjustHalfCarryAdd(f, before.high, value, HL().high); + setFlag(f, CF, carried & 0x100); + setFlag(f, HC, carried & 0x10); } cycles += 3; break;