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More M6532 documentation added/adjusted
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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Adrian Conlon
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@ -14,7 +14,7 @@
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VSS -| 1 40|- A6
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A5 -| 2 39|- 02
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A5 -| 2 39|- theta 2
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A4 -| 3 38|- CS1
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| | ___
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@ -58,7 +58,7 @@
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PA0-PA7 = port A
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PB0-PB7 = port B
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Vcc = ground
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02 = clock input
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theta 2 = clock input
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CS1 = chip select 1
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CS2 = chip select 2 (low)
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RS = RAM select (low)
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@ -118,6 +118,61 @@
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-- | REGISTER |
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| B |
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|_____________|
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Basic Elements of Interval Timer
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--------------------------------
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R/W PA7 A3 D7 D6 D5 D4 D3 D2 D1 D0 R/W A1 A0
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| | | | | | | | | | | | | |
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V V V V V V V V V V V | V V
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+---------------+ +-----------------------------------+ | +---------------+
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___ | | | |<---+----->| |<---- theta 2
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IRQ <---| Interrupt |<------| Programmable | | Divide |
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| Control | | Register | | Down |
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| | | |<----------| |
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+---------------+ +-----------------------------------+ +---------------+
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| | | | | | | | | |
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+-----------------------+ | | | | | | |
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| +-------------------+ | | | | | |
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V V V V V V V V
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D7 D6 D5 D4 D3 D2 D1 D0
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RAM—128 Bytes (1024 Bits)
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The 128 x 8 Read/Write memory acts as a conventional static RAM. Data can be written into the RAM from
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the microprocessor by selecting the chip (CS1 = 1, CS2 = 0) and by setting RS to a logic 0 (0.4v). Address
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lines AO through A6 are then used to select the desired byte of storage.
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Addressing Decode
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-----------------
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__
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RS R/W A4 A3 A2 A1 A0
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Write RAM 0 0 - - - - -
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Read RAM 0 1 - - - - -
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Write DDRA 1 0 - - 0 0 1
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Read DDRA 1 1 - - 0 0 1
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Write DDRB 1 0 - - 0 1 1
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Read DDRB 1 1 - - 0 1 1
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Write Output Reg A 1 0 - - 0 0 0
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Read Output Reg A 1 1 - - 0 0 0
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Write Output Reg B 1 0 - - 0 1 0
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Read Output Reg B 1 1 - - 0 1 0
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Write Timer
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+ 1T 1 0 1 (a) 1 0 0
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+ 8T 1 0 1 (a) 1 0 1
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+ 64T 1 0 1 (a) 1 1 0
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+ 1024T 1 0 1 (a) 1 1 1
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Read Timer 1 1 - (a) 1 — 0
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Read Interrupt Flag(s) 1 1 — — 1 — 1
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Write Edge Detect Control 1 0 0 — 1 (b) (c)
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(a) A3 = 0 to disable interrupt trom timer to IRQ
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A3 = 1 to enable interrupt from timer to IRQ
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(b) A1 = 0 to disable interrupt from PA7 to IRQ
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A1 = 1 to enable interrupt from PA7 to IRQ
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(c) A0 = 0 for negative edge-detect
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AO = 1 for positive edge-detect
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*/
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@ -127,48 +182,6 @@ namespace EightBit {
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M6532() noexcept;
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virtual ~M6532() = default;
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/*
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Address Lines (A0-A6)
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There are 7 address pins. In addition to these 7, there is 9 RAM SELECT pin. These pins, A0-A6 and RAM
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SELECT, are always used as addressing pins. There are two additional pins which are used as CHIP
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SELECTS. They are pins CS1 and CS2.
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*/
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uint8_t& address() { return m_address; }
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// RAM SELECT, active low
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PinLevel& RS() { return m_rs; }
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// CHIP SELECT 1, active high
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PinLevel& CS1() { return m_cs1; }
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// CHIP SELECT 2, active low
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PinLevel& CS2() { return m_cs2; }
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/*
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Data Bus (D0-D7)
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The 6532 has eight bi-directional data pins (D0-D7). These pins connect to the system's data lines and
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allow transfer of data to and from the microprocessor array. The output buffers remain in the off state except
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when a Read operation occurs and are capable of driving one standard TTL load and 130 pf.
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*/
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uint8_t& data() { return m_data; }
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/*
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Peripheral Data Ports
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The 6532 has 16 pins available for peripheral I/O operations. Each pin is individually software programmable
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to act as either an input or an output. The 16 pins are divided into 2 8-bit ports, PA0-PA7 and PB0-PB7.
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PA7 also has other uses which are discussed in later sections. The pins are set up as an input by writing a
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"0" into the corresponding bit of the data direction register. A "1" into the data direction register will cause
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its corresponding bit to be an output. When in the input mode, the peripheral output buffers are in the "1"
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state and pull-up device acts as less than one TTL load to the peripheral data lines. On a Read operation, the
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microprocessor unit reads the peripheral pin. When the peripheral device gets information from the 6532 it
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receives data stored in the data register. The microprocessor will read correct information if the peripheral
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lines are greater than 2.0 volts for a "1" and less than 0.8 volts for a "0" as the peripheral pins are all TTL
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compatible. Pins PB0-PB7 are also capable of sourcing 3 ma at 1.5v, thus making them capable of Darlington
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drive.
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*/
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uint8_t& PA() { return m_pa; }
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uint8_t& PB() { return m_pb; }
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/* ___
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Reset (RES)
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During system initialization a logic "0" on the RES input will cause a zeroing of all four I/O registers. This
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@ -196,6 +209,48 @@ namespace EightBit {
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*/
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PinLevel& IRQ() { return m_irq; }
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/*
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Data Bus (D0-D7)
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The 6532 has eight bi-directional data pins (D0-D7). These pins connect to the system's data lines and
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allow transfer of data to and from the microprocessor array. The output buffers remain in the off state except
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when a Read operation occurs and are capable of driving one standard TTL load and 130 pf.
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*/
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uint8_t& data() { return m_data; }
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/*
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Peripheral Data Ports
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The 6532 has 16 pins available for peripheral I/O operations. Each pin is individually software programmable
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to act as either an input or an output. The 16 pins are divided into 2 8-bit ports, PA0-PA7 and PB0-PB7.
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PA7 also has other uses which are discussed in later sections. The pins are set up as an input by writing a
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"0" into the corresponding bit of the data direction register. A "1" into the data direction register will cause
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its corresponding bit to be an output. When in the input mode, the peripheral output buffers are in the "1"
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state and pull-up device acts as less than one TTL load to the peripheral data lines. On a Read operation, the
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microprocessor unit reads the peripheral pin. When the peripheral device gets information from the 6532 it
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receives data stored in the data register. The microprocessor will read correct information if the peripheral
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lines are greater than 2.0 volts for a "1" and less than 0.8 volts for a "0" as the peripheral pins are all TTL
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compatible. Pins PB0-PB7 are also capable of sourcing 3 ma at 1.5v, thus making them capable of Darlington
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drive.
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*/
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uint8_t& PA() { return m_pa; }
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uint8_t& PB() { return m_pb; }
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/*
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Address Lines (A0-A6)
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There are 7 address pins. In addition to these 7, there is 9 RAM SELECT pin. These pins, A0-A6 and RAM
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SELECT, are always used as addressing pins. There are two additional pins which are used as CHIP
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SELECTS. They are pins CS1 and CS2.
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*/
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uint8_t& address() { return m_address; }
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// RAM SELECT, active low
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PinLevel& RS() { return m_rs; }
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// CHIP SELECT 1, active high
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PinLevel& CS1() { return m_cs1; }
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// CHIP SELECT 2, active low
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PinLevel& CS2() { return m_cs2; }
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void tick();
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virtual void initialise() final;
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@ -6,40 +6,6 @@
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EightBit::M6532::M6532() noexcept {
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}
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/*
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RAM—128 Bytes (1024 Bits)
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The 128 x 8 Read/Write memory acts as a conventional static RAM. Data can be written into the RAM from
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the microprocessor by selecting the chip (CS1 = 1, CS2 = 0) and by setting RS to a logic 0 (0.4v). Address
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lines AO through A6 are then used to select the desired byte of storage.
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*/
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/*
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__
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RS R/W A4 A3 A2 A1 A0
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Write RAM 0 0 - - - - -
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Read RAM 0 1 - - - - -
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Write DDRA 1 0 - - 0 0 1
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Read DDRA 1 1 - - 0 0 1
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Write DDRB 1 0 - - 0 1 1
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Read DDRB 1 1 - - 0 1 1
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Write Output Reg A 1 0 - - 0 0 0
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Read Output Reg A 1 1 - - 0 0 0
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Write Output Reg B 1 0 - - 0 1 0
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Read Output Reg B
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Write Timer
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1 1 0 1 0
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+ 1T 1 0 1 (a) 1 0 0
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+ 8T 1 0 1 (a) 1 0 1
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+ 64T t 0 1 (a) 1 1 0
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+ 1024T 1 0 1 (a) 1 1 1
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Read Timer 1 1 _ (a) 1 — 0
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Read Interrupt Flag(s) 1 1 — — 1 — 1
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Write Edge Detect Control 1 0 0 — 1 (b) (0)
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*/
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void EightBit::M6532::tick() {
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if (selected()) {
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