mirror of
https://github.com/MoleskiCoder/EightBit.git
synced 2024-12-12 19:30:10 +00:00
Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
parent
c6eb68ba13
commit
45dc274167
@ -62,7 +62,7 @@ namespace EightBit {
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case 0b101:
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return L();
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case 0b110:
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return getByte(HL());
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return BUS().read(HL());
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case 0b111:
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return a;
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default:
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@ -92,7 +92,7 @@ namespace EightBit {
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L() = value;
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break;
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case 0b110:
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setByte(HL(), value);
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BUS().write(HL(), value);
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break;
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case 0b111:
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a = value;
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@ -231,22 +231,20 @@ void EightBit::Intel8080::cmc(uint8_t& a, uint8_t& f) {
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}
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void EightBit::Intel8080::xhtl(register16_t& operand) {
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MEMPTR().low = getByte(SP());
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setByte(operand.low);
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MEMPTR().low = BUS().read(SP());
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BUS().write(operand.low);
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operand.low = MEMPTR().low;
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BUS().ADDRESS().word++;
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MEMPTR().high = getByte();
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setByte(operand.high);
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MEMPTR().high = BUS().read();
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BUS().write(operand.high);
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operand.high = MEMPTR().high;
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}
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void EightBit::Intel8080::writePort(uint8_t port, uint8_t data) {
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BUS().ADDRESS().low = port;
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BUS().ADDRESS().high = data;
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MEMPTR() = BUS().ADDRESS();
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BUS().placeDATA(data);
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writePort();
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MEMPTR().low++;
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}
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void EightBit::Intel8080::writePort() {
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@ -256,10 +254,8 @@ void EightBit::Intel8080::writePort() {
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void EightBit::Intel8080::readPort(uint8_t port, uint8_t& a) {
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BUS().ADDRESS().low = port;
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BUS().ADDRESS().high = a;
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MEMPTR() = BUS().ADDRESS();
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readPort();
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a = BUS().DATA();
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MEMPTR().low++;
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}
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void EightBit::Intel8080::readPort() {
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@ -302,9 +298,7 @@ int EightBit::Intel8080::execute(uint8_t opcode) {
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execute(a, f, x, y, z, p, q);
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if (UNLIKELY(cycles() == 0))
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throw std::logic_error("Unhandled opcode");
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ASSUME(cycles() > 0);
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return cycles();
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}
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@ -338,11 +332,11 @@ void EightBit::Intel8080::execute(uint8_t& a, uint8_t& f, int x, int y, int z, i
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case 0:
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switch (p) {
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case 0: // LD (BC),A
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setByte(BC(), a);
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BUS().write(BC(), a);
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addCycles(7);
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break;
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case 1: // LD (DE),A
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setByte(DE(), a);
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BUS().write(DE(), a);
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addCycles(7);
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break;
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case 2: // LD (nn),HL
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@ -351,8 +345,8 @@ void EightBit::Intel8080::execute(uint8_t& a, uint8_t& f, int x, int y, int z, i
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addCycles(16);
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break;
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case 3: // LD (nn),A
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MEMPTR() = fetchWord();
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setByte(MEMPTR(), a);
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BUS().ADDRESS() = fetchWord();
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BUS().write(a);
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addCycles(13);
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break;
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default:
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@ -362,11 +356,11 @@ void EightBit::Intel8080::execute(uint8_t& a, uint8_t& f, int x, int y, int z, i
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case 1:
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switch (p) {
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case 0: // LD A,(BC)
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a = getByte(BC());
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a = BUS().read(BC());
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addCycles(7);
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break;
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case 1: // LD A,(DE)
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a = getByte(DE());
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a = BUS().read(DE());
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addCycles(7);
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break;
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case 2: // LD HL,(nn)
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@ -375,8 +369,8 @@ void EightBit::Intel8080::execute(uint8_t& a, uint8_t& f, int x, int y, int z, i
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addCycles(16);
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break;
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case 3: // LD A,(nn)
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MEMPTR() = fetchWord();
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a = getByte(MEMPTR());
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BUS().ADDRESS() = fetchWord();
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a = BUS().read();
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addCycles(13);
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break;
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default:
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@ -76,7 +76,7 @@ namespace EightBit {
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case 5:
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return L();
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case 6:
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return getByte(HL());
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return BUS().read(HL());
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case 7:
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return a;
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default:
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@ -106,7 +106,7 @@ namespace EightBit {
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L() = value;
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break;
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case 6:
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setByte(HL(), value);
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BUS().write(HL(), value);
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break;
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case 7:
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a = value;
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@ -467,19 +467,19 @@ void EightBit::GameBoy::LR35902::executeOther(uint8_t& a, uint8_t& f, int x, int
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case 0:
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switch (p) {
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case 0: // LD (BC),A
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setByte(BC(), a);
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BUS().write(BC(), a);
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addCycles(2);
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break;
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case 1: // LD (DE),A
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setByte(DE(), a);
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BUS().write(DE(), a);
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addCycles(2);
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break;
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case 2: // GB: LDI (HL),A
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setByte(HL().word++, a);
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BUS().write(HL().word++, a);
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addCycles(2);
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break;
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case 3: // GB: LDD (HL),A
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setByte(HL().word--, a);
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BUS().write(HL().word--, a);
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addCycles(2);
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break;
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default:
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@ -489,19 +489,19 @@ void EightBit::GameBoy::LR35902::executeOther(uint8_t& a, uint8_t& f, int x, int
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case 1:
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switch (p) {
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case 0: // LD A,(BC)
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a = getByte(BC());
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a = BUS().read(BC());
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addCycles(2);
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break;
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case 1: // LD A,(DE)
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a = getByte(DE());
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a = BUS().read(DE());
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addCycles(2);
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break;
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case 2: // GB: LDI A,(HL)
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a = getByte(HL().word++);
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a = BUS().read(HL().word++);
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addCycles(2);
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break;
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case 3: // GB: LDD A,(HL)
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a = getByte(HL().word--);
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a = BUS().read(HL().word--);
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addCycles(2);
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break;
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default:
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@ -718,7 +718,7 @@ void EightBit::GameBoy::LR35902::executeOther(uint8_t& a, uint8_t& f, int x, int
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break;
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case 5: // GB: LD (nn),A
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MEMPTR() = fetchWord();
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setByte(MEMPTR(), a);
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BUS().write(MEMPTR(), a);
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addCycles(4);
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break;
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case 6: // GB: LD A,(FF00 + C)
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@ -727,7 +727,7 @@ void EightBit::GameBoy::LR35902::executeOther(uint8_t& a, uint8_t& f, int x, int
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break;
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case 7: // GB: LD A,(nn)
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MEMPTR() = fetchWord();
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a = getByte(MEMPTR());
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a = BUS().read(MEMPTR());
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addCycles(4);
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break;
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default:
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@ -137,122 +137,122 @@ namespace EightBit {
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uint8_t AM_Absolute() {
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Address_Absolute();
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return getByte(MEMPTR());
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return BUS().read(MEMPTR());
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}
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uint8_t AM_ZeroPage() {
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Address_ZeroPage();
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return getByte(MEMPTR());
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return BUS().read(MEMPTR());
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}
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uint8_t AM_AbsoluteX() {
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if (UNLIKELY(Address_AbsoluteX()))
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addCycle();
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return getByte(MEMPTR());
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return BUS().read(MEMPTR());
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}
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uint8_t AM_AbsoluteY() {
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if (UNLIKELY(Address_AbsoluteY()))
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addCycle();
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return getByte(MEMPTR());
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return BUS().read(MEMPTR());
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}
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uint8_t AM_ZeroPageX() {
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Address_ZeroPageX();
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return getByte(MEMPTR());
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return BUS().read(MEMPTR());
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}
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uint8_t AM_ZeroPageY() {
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Address_ZeroPageY();
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return getByte(MEMPTR());
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return BUS().read(MEMPTR());
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}
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uint8_t AM_IndexedIndirectX() {
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Address_IndexedIndirectX();
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return getByte(MEMPTR());
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return BUS().read(MEMPTR());
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}
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uint8_t AM_IndirectIndexedY() {
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if (UNLIKELY(Address_IndirectIndexedY()))
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addCycle();
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return getByte(MEMPTR());
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return BUS().read(MEMPTR());
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}
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// Addressing modes, write
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void AM_Absolute(uint8_t value) {
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Address_Absolute();
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setByte(MEMPTR(), value);
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BUS().write(MEMPTR(), value);
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}
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void AM_ZeroPage(uint8_t value) {
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Address_ZeroPage();
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setByte(MEMPTR(), value);
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BUS().write(MEMPTR(), value);
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}
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void AM_AbsoluteX(uint8_t value) {
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Address_AbsoluteX();
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setByte(MEMPTR(), value);
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BUS().write(MEMPTR(), value);
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}
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void AM_AbsoluteY(uint8_t value) {
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Address_AbsoluteY();
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setByte(MEMPTR(), value);
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BUS().write(MEMPTR(), value);
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}
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void AM_ZeroPageX(uint8_t value) {
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Address_ZeroPageX();
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setByte(MEMPTR(), value);
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BUS().write(MEMPTR(), value);
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}
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void AM_ZeroPageY(uint8_t value) {
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Address_ZeroPageY();
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setByte(MEMPTR(), value);
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BUS().write(MEMPTR(), value);
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}
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void AM_IndexedIndirectX(uint8_t value) {
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Address_IndexedIndirectX();
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setByte(MEMPTR(), value);
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BUS().write(MEMPTR(), value);
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}
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void AM_IndirectIndexedY(uint8_t value) {
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Address_IndirectIndexedY();
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setByte(MEMPTR(), value);
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BUS().write(MEMPTR(), value);
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}
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// Operations
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void DCP(uint8_t value) {
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setByte(--value);
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BUS().write(--value);
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CMP(A(), value);
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}
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void ISB(uint8_t value) {
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setByte(++value);
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BUS().write(++value);
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A() = SBC(A(), value);
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}
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void SLO(uint8_t value) {
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const auto result = ASL(value);
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setByte(result);
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BUS().write(result);
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ORA(result);
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}
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void SRE(uint8_t value) {
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const auto result = LSR(value);
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setByte(result);
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BUS().write(result);
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EORA(result);
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}
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void RLA(uint8_t value) {
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const auto result = ROL(value);
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setByte(result);
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BUS().write(result);
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ANDA(result);
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}
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void RRA(uint8_t value) {
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const auto result = ROR(value);
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setByte(result);
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BUS().write(result);
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A() = ADC(A(), result);
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}
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@ -54,20 +54,20 @@ EightBit::register16_t EightBit::MOS6502::getWordPaged(uint8_t page, uint8_t off
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EightBit::register16_t returned;
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returned.low = getBytePaged(page, offset);
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BUS().ADDRESS().low++;
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returned.high = getByte();
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returned.high = BUS().read();
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return returned;
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}
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uint8_t EightBit::MOS6502::getBytePaged(uint8_t page, uint8_t offset) {
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BUS().ADDRESS().low = offset;
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BUS().ADDRESS().high = page;
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return getByte();
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return BUS().read();
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}
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void EightBit::MOS6502::setBytePaged(uint8_t page, uint8_t offset, uint8_t value) {
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BUS().ADDRESS().low = offset;
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BUS().ADDRESS().high = page;
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setByte(value);
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BUS().write(value);
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}
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void EightBit::MOS6502::interrupt(uint8_t vector) {
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@ -88,7 +88,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
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case 0x03: addCycles(8); SLO(AM_IndexedIndirectX()); break;
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case 0x04: addCycles(3); AM_ZeroPage(); break;
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case 0x05: addCycles(3); ORA(AM_ZeroPage()); break;
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case 0x06: addCycles(5); setByte(ASL(AM_ZeroPage())); break;
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case 0x06: addCycles(5); BUS().write(ASL(AM_ZeroPage())); break;
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case 0x07: addCycles(5); SLO(AM_ZeroPage()); break;
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case 0x08: addCycles(3); PHP(); break;
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case 0x09: addCycles(2); ORA(AM_Immediate()); break;
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@ -96,7 +96,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
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case 0x0b: addCycles(2); AAC(AM_Immediate()); break;
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case 0x0c: addCycles(4); AM_Absolute(); break;
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case 0x0d: addCycles(4); ORA(AM_Absolute()); break;
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case 0x0e: addCycles(6); setByte(ASL(AM_Absolute())); break;
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case 0x0e: addCycles(6); BUS().write(ASL(AM_Absolute())); break;
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case 0x0f: addCycles(6); SLO(AM_Absolute()); break;
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case 0x10: addCycles(2); Branch(!(P() & NF)); break;
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@ -105,7 +105,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
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case 0x13: addCycles(7); SLO(AM_IndirectIndexedY()); break;
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case 0x14: addCycles(4); AM_ZeroPageX(); break;
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case 0x15: addCycles(4); ORA(AM_ZeroPageX()); break;
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case 0x16: addCycles(6); setByte(ASL(AM_ZeroPageX())); break;
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case 0x16: addCycles(6); BUS().write(ASL(AM_ZeroPageX())); break;
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case 0x17: addCycles(6); SLO(AM_ZeroPageX()); break;
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case 0x18: addCycles(2); clearFlag(P(), CF); break;
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case 0x19: addCycles(4); ORA(AM_AbsoluteY()); break;
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@ -113,7 +113,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
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case 0x1b: addCycles(6); SLO(AM_AbsoluteY()); break;
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case 0x1c: addCycles(4); AM_AbsoluteX(); break;
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case 0x1d: addCycles(4); ORA(AM_AbsoluteX()); break;
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case 0x1e: addCycles(7); setByte(ASL(AM_AbsoluteX())); break;
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case 0x1e: addCycles(7); BUS().write(ASL(AM_AbsoluteX())); break;
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case 0x1f: addCycles(6); SLO(AM_AbsoluteX()); break;
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case 0x20: addCycles(6); JSR_abs(); break;
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@ -122,7 +122,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
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case 0x23: addCycles(8); RLA(AM_IndexedIndirectX()); break;
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case 0x24: addCycles(3); BIT(AM_ZeroPage()); break;
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case 0x25: addCycles(3); ANDA(AM_ZeroPage()); break;
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case 0x26: addCycles(5); setByte(ROL(AM_ZeroPage())); break;
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case 0x26: addCycles(5); BUS().write(ROL(AM_ZeroPage())); break;
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case 0x27: addCycles(5); RLA(AM_ZeroPage()); break;
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case 0x28: addCycles(4); PLP(); break;
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case 0x29: addCycles(2); ANDA(AM_Immediate()); break;
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@ -130,7 +130,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
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case 0x2b: addCycles(2); AAC(AM_Immediate()); break;
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case 0x2c: addCycles(4); BIT(AM_Absolute()); break;
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case 0x2d: addCycles(4); ANDA(AM_Absolute()); break;
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case 0x2e: addCycles(6); setByte(ROL(AM_Absolute())); break;
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case 0x2e: addCycles(6); BUS().write(ROL(AM_Absolute())); break;
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case 0x2f: addCycles(6); RLA(AM_Absolute()); break;
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case 0x30: addCycles(2); Branch(!!(P() & NF)); break;
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@ -139,7 +139,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
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case 0x33: addCycles(7); RLA(AM_IndirectIndexedY()); break;
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case 0x34: addCycles(4); AM_ZeroPageX(); break;
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case 0x35: addCycles(4); ANDA(AM_ZeroPageX()); break;
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case 0x36: addCycles(6); setByte(ROL(AM_ZeroPageX())); break;
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case 0x36: addCycles(6); BUS().write(ROL(AM_ZeroPageX())); break;
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case 0x37: addCycles(6); RLA(AM_ZeroPageX()); break;
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case 0x38: addCycles(2); setFlag(P(), CF); break;
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case 0x39: addCycles(4); ANDA(AM_AbsoluteY()); break;
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@ -147,7 +147,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
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case 0x3b: addCycles(6); RLA(AM_AbsoluteY()); break;
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case 0x3c: addCycles(4); AM_AbsoluteX(); break;
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case 0x3d: addCycles(4); ANDA(AM_AbsoluteX()); break;
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case 0x3e: addCycles(7); setByte(ROL(AM_AbsoluteX())); break;
|
||||
case 0x3e: addCycles(7); BUS().write(ROL(AM_AbsoluteX())); break;
|
||||
case 0x3f: addCycles(6); RLA(AM_AbsoluteX()); break;
|
||||
|
||||
case 0x40: addCycles(6); RTI(); break;
|
||||
@ -156,7 +156,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0x43: addCycles(8); SRE(AM_IndexedIndirectX()); break;
|
||||
case 0x44: addCycles(3); AM_ZeroPage(); break;
|
||||
case 0x45: addCycles(3); EORA(AM_ZeroPage()); break;
|
||||
case 0x46: addCycles(5); setByte(LSR(AM_ZeroPage())); break;
|
||||
case 0x46: addCycles(5); BUS().write(LSR(AM_ZeroPage())); break;
|
||||
case 0x47: addCycles(5); SRE(AM_ZeroPage()); break;
|
||||
case 0x48: addCycles(3); push(A()); break;
|
||||
case 0x49: addCycles(2); EORA(AM_Immediate()); break;
|
||||
@ -164,7 +164,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0x4b: addCycles(2); ASR(AM_Immediate()); break;
|
||||
case 0x4c: addCycles(3); JMP_abs(); break;
|
||||
case 0x4d: addCycles(4); EORA(AM_Absolute()); break;
|
||||
case 0x4e: addCycles(6); setByte(LSR(AM_Absolute())); break;
|
||||
case 0x4e: addCycles(6); BUS().write(LSR(AM_Absolute())); break;
|
||||
case 0x4f: addCycles(6); SRE(AM_Absolute()); break;
|
||||
|
||||
case 0x50: addCycles(2); Branch(!(P() & VF)); break;
|
||||
@ -173,7 +173,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0x53: addCycles(7); SRE(AM_IndirectIndexedY()); break;
|
||||
case 0x54: addCycles(4); AM_ZeroPage(); break;
|
||||
case 0x55: addCycles(4); EORA(AM_ZeroPageX()); break;
|
||||
case 0x56: addCycles(6); setByte(LSR(AM_ZeroPageX())); break;
|
||||
case 0x56: addCycles(6); BUS().write(LSR(AM_ZeroPageX())); break;
|
||||
case 0x57: addCycles(6); SRE(AM_ZeroPageX()); break;
|
||||
case 0x58: addCycles(2); clearFlag(P(), IF); break;
|
||||
case 0x59: addCycles(4); EORA(AM_AbsoluteY()); break;
|
||||
@ -181,7 +181,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0x5b: addCycles(6); SRE(AM_AbsoluteY()); break;
|
||||
case 0x5c: addCycles(4); AM_AbsoluteX(); break;
|
||||
case 0x5d: addCycles(4); EORA(AM_AbsoluteX()); break;
|
||||
case 0x5e: addCycles(7); setByte(LSR(AM_AbsoluteX())); break;
|
||||
case 0x5e: addCycles(7); BUS().write(LSR(AM_AbsoluteX())); break;
|
||||
case 0x5f: addCycles(6); SRE(AM_AbsoluteX()); break;
|
||||
|
||||
case 0x60: addCycles(6); RTS(); break;
|
||||
@ -190,7 +190,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0x63: addCycles(8); RRA(AM_IndexedIndirectX()); break;
|
||||
case 0x64: addCycles(3); AM_ZeroPage(); break;
|
||||
case 0x65: addCycles(3); A() = ADC(A(), AM_ZeroPage()); break;
|
||||
case 0x66: addCycles(5); setByte(ROR(AM_ZeroPage())); break;
|
||||
case 0x66: addCycles(5); BUS().write(ROR(AM_ZeroPage())); break;
|
||||
case 0x67: addCycles(5); RRA(AM_ZeroPage()); break;
|
||||
case 0x68: addCycles(4); adjustNZ(A() = pop()); break;
|
||||
case 0x69: addCycles(2); A() = ADC(A(), AM_Immediate()); break;
|
||||
@ -198,7 +198,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0x6b: addCycles(2); ARR(AM_Immediate()); break;
|
||||
case 0x6c: addCycles(5); JMP_ind(); break;
|
||||
case 0x6d: addCycles(4); A() = ADC(A(), AM_Absolute()); break;
|
||||
case 0x6e: addCycles(6); setByte(ROR(AM_Absolute())); break;
|
||||
case 0x6e: addCycles(6); BUS().write(ROR(AM_Absolute())); break;
|
||||
case 0x6f: addCycles(6); RRA(AM_Absolute()); break;
|
||||
|
||||
case 0x70: addCycles(2); Branch(!!(P() & VF)); break;
|
||||
@ -207,7 +207,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0x73: addCycles(7); RRA(AM_IndirectIndexedY()); break;
|
||||
case 0x74: addCycles(4); AM_ZeroPageX(); break;
|
||||
case 0x75: addCycles(4); A() = ADC(A(), AM_ZeroPageX()); break;
|
||||
case 0x76: addCycles(6); setByte(ROR(AM_ZeroPageX())); break;
|
||||
case 0x76: addCycles(6); BUS().write(ROR(AM_ZeroPageX())); break;
|
||||
case 0x77: addCycles(6); RRA(AM_ZeroPageX()); break;
|
||||
case 0x78: addCycles(2); setFlag(P(), IF); break;
|
||||
case 0x79: addCycles(4); A() = ADC(A(), AM_AbsoluteY()); break;
|
||||
@ -215,7 +215,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0x7b: addCycles(6); RRA(AM_AbsoluteY()); break;
|
||||
case 0x7c: addCycles(4); AM_AbsoluteX(); break;
|
||||
case 0x7d: addCycles(4); A() = ADC(A(), AM_AbsoluteX()); break;
|
||||
case 0x7e: addCycles(7); setByte(ROR(AM_AbsoluteX())); break;
|
||||
case 0x7e: addCycles(7); BUS().write(ROR(AM_AbsoluteX())); break;
|
||||
case 0x7f: addCycles(6); RRA(AM_AbsoluteX()); break;
|
||||
|
||||
case 0x80: addCycles(2); AM_Immediate(); break;
|
||||
@ -292,7 +292,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0xc3: addCycles(8); DCP(AM_IndexedIndirectX()); break;
|
||||
case 0xc4: addCycles(3); CMP(Y(), AM_ZeroPage()); break;
|
||||
case 0xc5: addCycles(3); CMP(A(), AM_ZeroPage()); break;
|
||||
case 0xc6: addCycles(5); setByte(DEC(AM_ZeroPage())); break;
|
||||
case 0xc6: addCycles(5); BUS().write(DEC(AM_ZeroPage())); break;
|
||||
case 0xc7: addCycles(5); DCP(AM_ZeroPage()); break;
|
||||
case 0xc8: addCycles(2); adjustNZ(++Y()); break;
|
||||
case 0xc9: addCycles(2); CMP(A(), AM_Immediate()); break;
|
||||
@ -300,7 +300,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0xcb: addCycles(2); AXS(AM_Immediate()); break;
|
||||
case 0xcc: addCycles(4); CMP(Y(), AM_Absolute()); break;
|
||||
case 0xcd: addCycles(4); CMP(A(), AM_Absolute()); break;
|
||||
case 0xce: addCycles(6); setByte(DEC(AM_Absolute())); break;
|
||||
case 0xce: addCycles(6); BUS().write(DEC(AM_Absolute())); break;
|
||||
case 0xcf: addCycles(6); DCP(AM_Absolute()); break;
|
||||
|
||||
case 0xd0: addCycles(2); Branch(!(P() & ZF)); break;
|
||||
@ -309,7 +309,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0xd3: addCycles(7); DCP(AM_IndirectIndexedY()); break;
|
||||
case 0xd4: addCycles(4); AM_ZeroPageX(); break;
|
||||
case 0xd5: addCycles(4); CMP(A(), AM_ZeroPageX()); break;
|
||||
case 0xd6: addCycles(6); setByte(DEC(AM_ZeroPageX())); break;
|
||||
case 0xd6: addCycles(6); BUS().write(DEC(AM_ZeroPageX())); break;
|
||||
case 0xd7: addCycles(6); DCP(AM_ZeroPageX()); break;
|
||||
case 0xd8: addCycles(2); clearFlag(P(), DF); break;
|
||||
case 0xd9: addCycles(4); CMP(A(), AM_AbsoluteY()); break;
|
||||
@ -317,7 +317,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0xdb: addCycles(6); DCP(AM_AbsoluteY()); break;
|
||||
case 0xdc: addCycles(4); AM_AbsoluteX(); break;
|
||||
case 0xdd: addCycles(4); CMP(A(), AM_AbsoluteX()); break;
|
||||
case 0xde: addCycles(7); setByte(DEC(AM_AbsoluteX())); break;
|
||||
case 0xde: addCycles(7); BUS().write(DEC(AM_AbsoluteX())); break;
|
||||
case 0xdf: addCycles(6); DCP(AM_AbsoluteX()); break;
|
||||
|
||||
case 0xe0: addCycles(2); CMP(X(), AM_Immediate()); break;
|
||||
@ -326,7 +326,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0xe3: addCycles(8); ISB(AM_IndexedIndirectX()); break;
|
||||
case 0xe4: addCycles(3); CMP(X(), AM_ZeroPage()); break;
|
||||
case 0xe5: addCycles(3); A() = SBC(A(), AM_ZeroPage()); break;
|
||||
case 0xe6: addCycles(5); setByte(INC(AM_ZeroPage())); break;
|
||||
case 0xe6: addCycles(5); BUS().write(INC(AM_ZeroPage())); break;
|
||||
case 0xe7: addCycles(5); ISB(AM_ZeroPage()); break;
|
||||
case 0xe8: addCycles(2); adjustNZ(++X()); break;
|
||||
case 0xe9: addCycles(2); A() = SBC(A(), AM_Immediate()); break;
|
||||
@ -334,7 +334,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0xeb: addCycles(2); A() = SBC(A(), AM_Immediate()); break;
|
||||
case 0xec: addCycles(4); CMP(X(), AM_Absolute()); break;
|
||||
case 0xed: addCycles(4); A() = SBC(A(), AM_Absolute()); break;
|
||||
case 0xee: addCycles(6); setByte(INC(AM_Absolute())); break;
|
||||
case 0xee: addCycles(6); BUS().write(INC(AM_Absolute())); break;
|
||||
case 0xef: addCycles(6); ISB(AM_Absolute()); break;
|
||||
|
||||
case 0xf0: addCycles(2); Branch(!!(P() & ZF)); break;
|
||||
@ -343,7 +343,7 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0xf3: addCycles(7); ISB(AM_IndirectIndexedY()); break;
|
||||
case 0xf4: addCycles(4); AM_ZeroPageX(); break;
|
||||
case 0xf5: addCycles(4); A() = SBC(A(), AM_ZeroPageX()); break;
|
||||
case 0xf6: addCycles(6); setByte(INC(AM_ZeroPageX())); break;
|
||||
case 0xf6: addCycles(6); BUS().write(INC(AM_ZeroPageX())); break;
|
||||
case 0xf7: addCycles(6); ISB(AM_ZeroPageX()); break;
|
||||
case 0xf8: addCycles(2); setFlag(P(), DF); break;
|
||||
case 0xf9: addCycles(4); A() = SBC(A(), AM_AbsoluteY()); break;
|
||||
@ -351,13 +351,11 @@ int EightBit::MOS6502::execute(uint8_t cell) {
|
||||
case 0xfb: addCycles(6); ISB(AM_AbsoluteY()); break;
|
||||
case 0xfc: addCycles(4); AM_AbsoluteX(); break;
|
||||
case 0xfd: addCycles(4); A() = SBC(A(), AM_AbsoluteX()); break;
|
||||
case 0xfe: addCycles(7); setByte(INC(AM_AbsoluteX())); break;
|
||||
case 0xfe: addCycles(7); BUS().write(INC(AM_AbsoluteX())); break;
|
||||
case 0xff: addCycles(6); ISB(AM_AbsoluteX()); break;
|
||||
}
|
||||
|
||||
if (UNLIKELY(cycles() == 0))
|
||||
throw std::logic_error("Unhandled opcode");
|
||||
|
||||
ASSUME(cycles() > 0);
|
||||
return cycles();
|
||||
}
|
||||
|
||||
|
@ -126,6 +126,8 @@ namespace EightBit {
|
||||
}
|
||||
|
||||
uint8_t R(int r, uint8_t a) {
|
||||
ASSUME(r >= 0);
|
||||
ASSUME(r <= 7);
|
||||
switch (r) {
|
||||
case 0:
|
||||
return B();
|
||||
@ -140,16 +142,18 @@ namespace EightBit {
|
||||
case 5:
|
||||
return HL2().low;
|
||||
case 6:
|
||||
return getByte(LIKELY(!m_displaced) ? HL().word : displacedAddress());
|
||||
return BUS().read(LIKELY(!m_displaced) ? HL().word : displacedAddress());
|
||||
case 7:
|
||||
return a;
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
throw std::logic_error("Unhandled registry mechanism");
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
void R(int r, uint8_t& a, uint8_t value) {
|
||||
ASSUME(r >= 0);
|
||||
ASSUME(r <= 7);
|
||||
switch (r) {
|
||||
case 0:
|
||||
B() = value;
|
||||
@ -170,7 +174,7 @@ namespace EightBit {
|
||||
HL2().low = value;
|
||||
break;
|
||||
case 6:
|
||||
setByte(LIKELY(!m_displaced) ? HL().word : displacedAddress(), value);
|
||||
BUS().write(LIKELY(!m_displaced) ? HL().word : displacedAddress(), value);
|
||||
break;
|
||||
case 7:
|
||||
a = value;
|
||||
@ -178,9 +182,12 @@ namespace EightBit {
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
uint8_t R2(int r, const uint8_t& a) {
|
||||
ASSUME(r >= 0);
|
||||
ASSUME(r <= 7);
|
||||
switch (r) {
|
||||
case 0:
|
||||
return B();
|
||||
@ -195,16 +202,18 @@ namespace EightBit {
|
||||
case 5:
|
||||
return L();
|
||||
case 6:
|
||||
return getByte(HL());
|
||||
return BUS().read(HL());
|
||||
case 7:
|
||||
return a;
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
throw std::logic_error("Unhandled registry mechanism");
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
void R2(int r, uint8_t& a, uint8_t value) {
|
||||
ASSUME(r >= 0);
|
||||
ASSUME(r <= 7);
|
||||
switch (r) {
|
||||
case 0:
|
||||
B() = value;
|
||||
@ -225,7 +234,7 @@ namespace EightBit {
|
||||
L() = value;
|
||||
break;
|
||||
case 6:
|
||||
setByte(HL(), value);
|
||||
BUS().write(HL(), value);
|
||||
break;
|
||||
case 7:
|
||||
a = value;
|
||||
@ -233,9 +242,12 @@ namespace EightBit {
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
register16_t& RP(int rp) {
|
||||
ASSUME(rp >= 0);
|
||||
ASSUME(rp <= 3);
|
||||
switch (rp) {
|
||||
case 0:
|
||||
return BC();
|
||||
@ -248,6 +260,7 @@ namespace EightBit {
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
register16_t& HL2() {
|
||||
@ -260,6 +273,8 @@ namespace EightBit {
|
||||
}
|
||||
|
||||
register16_t& RP2(int rp) {
|
||||
ASSUME(rp >= 0);
|
||||
ASSUME(rp <= 3);
|
||||
switch (rp) {
|
||||
case 0:
|
||||
return BC();
|
||||
@ -272,6 +287,7 @@ namespace EightBit {
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
static void adjustHalfCarryAdd(uint8_t& f, uint8_t before, uint8_t value, int calculation) {
|
||||
|
179
Z80/src/Z80.cpp
179
Z80/src/Z80.cpp
@ -74,6 +74,8 @@ void EightBit::Z80::decrement(uint8_t& f, uint8_t& operand) {
|
||||
}
|
||||
|
||||
bool EightBit::Z80::jrConditionalFlag(uint8_t f, const int flag) {
|
||||
ASSUME(flag >= 0);
|
||||
ASSUME(flag <= 3);
|
||||
switch (flag) {
|
||||
case 0: // NZ
|
||||
return jrConditional(!(f & ZF));
|
||||
@ -86,10 +88,12 @@ bool EightBit::Z80::jrConditionalFlag(uint8_t f, const int flag) {
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
throw std::logic_error("Unhandled JR conditional");
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
bool EightBit::Z80::jumpConditionalFlag(uint8_t f, const int flag) {
|
||||
ASSUME(flag >= 0);
|
||||
ASSUME(flag <= 7);
|
||||
switch (flag) {
|
||||
case 0: // NZ
|
||||
return jumpConditional(!(f & ZF));
|
||||
@ -110,7 +114,7 @@ bool EightBit::Z80::jumpConditionalFlag(uint8_t f, const int flag) {
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
throw std::logic_error("Unhandled JP conditional");
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
void EightBit::Z80::retn() {
|
||||
@ -123,6 +127,8 @@ void EightBit::Z80::reti() {
|
||||
}
|
||||
|
||||
bool EightBit::Z80::returnConditionalFlag(uint8_t f, const int flag) {
|
||||
ASSUME(flag >= 0);
|
||||
ASSUME(flag <= 7);
|
||||
switch (flag) {
|
||||
case 0: // NZ
|
||||
return returnConditional(!(f & ZF));
|
||||
@ -143,10 +149,12 @@ bool EightBit::Z80::returnConditionalFlag(uint8_t f, const int flag) {
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
throw std::logic_error("Unhandled RET conditional");
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
bool EightBit::Z80::callConditionalFlag(uint8_t f, const int flag) {
|
||||
ASSUME(flag >= 0);
|
||||
ASSUME(flag <= 7);
|
||||
switch (flag) {
|
||||
case 0: // NZ
|
||||
return callConditional(!(f & ZF));
|
||||
@ -167,7 +175,7 @@ bool EightBit::Z80::callConditionalFlag(uint8_t f, const int flag) {
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
throw std::logic_error("Unhandled CALL conditional");
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
void EightBit::Z80::sbc(uint8_t& f, register16_t& operand, const register16_t value) {
|
||||
@ -190,7 +198,7 @@ void EightBit::Z80::sbc(uint8_t& f, register16_t& operand, const register16_t va
|
||||
setFlag(f, CF, result & Bit16);
|
||||
adjustXY<Z80>(f, operand.high);
|
||||
|
||||
MEMPTR().word++;
|
||||
++MEMPTR().word;
|
||||
}
|
||||
|
||||
void EightBit::Z80::adc(uint8_t& f, register16_t& operand, const register16_t value) {
|
||||
@ -213,7 +221,7 @@ void EightBit::Z80::adc(uint8_t& f, register16_t& operand, const register16_t va
|
||||
setFlag(f, CF, result & Bit16);
|
||||
adjustXY<Z80>(f, operand.high);
|
||||
|
||||
MEMPTR().word++;
|
||||
++MEMPTR().word;
|
||||
}
|
||||
|
||||
void EightBit::Z80::add(uint8_t& f, register16_t& operand, const register16_t value) {
|
||||
@ -229,7 +237,7 @@ void EightBit::Z80::add(uint8_t& f, register16_t& operand, const register16_t va
|
||||
adjustHalfCarryAdd(f, MEMPTR().high, value.high, operand.high);
|
||||
adjustXY<Z80>(f, operand.high);
|
||||
|
||||
MEMPTR().word++;
|
||||
++MEMPTR().word;
|
||||
}
|
||||
|
||||
void EightBit::Z80::add(uint8_t& f, uint8_t& operand, const uint8_t value, const int carry) {
|
||||
@ -368,6 +376,8 @@ uint8_t EightBit::Z80::srl(uint8_t& f, uint8_t operand) {
|
||||
}
|
||||
|
||||
uint8_t EightBit::Z80::bit(uint8_t& f, int n, uint8_t operand) {
|
||||
ASSUME(n >= 0);
|
||||
ASSUME(n <= 7);
|
||||
setFlag(f, HC);
|
||||
clearFlag(f, NF);
|
||||
const auto discarded = operand & (1 << n);
|
||||
@ -377,10 +387,14 @@ uint8_t EightBit::Z80::bit(uint8_t& f, int n, uint8_t operand) {
|
||||
}
|
||||
|
||||
uint8_t EightBit::Z80::res(int n, const uint8_t operand) {
|
||||
ASSUME(n >= 0);
|
||||
ASSUME(n <= 7);
|
||||
return operand & ~(1 << n);
|
||||
}
|
||||
|
||||
uint8_t EightBit::Z80::set(int n, const uint8_t operand) {
|
||||
ASSUME(n >= 0);
|
||||
ASSUME(n <= 7);
|
||||
return operand | (1 << n);
|
||||
}
|
||||
|
||||
@ -445,18 +459,18 @@ void EightBit::Z80::ccf(const uint8_t a, uint8_t& f) {
|
||||
}
|
||||
|
||||
void EightBit::Z80::xhtl(register16_t& operand) {
|
||||
MEMPTR().low = getByte(SP());
|
||||
setByte(operand.low);
|
||||
MEMPTR().low = BUS().read(SP());
|
||||
BUS().write(operand.low);
|
||||
operand.low = MEMPTR().low;
|
||||
BUS().ADDRESS().word++;
|
||||
MEMPTR().high = getByte();
|
||||
setByte(operand.high);
|
||||
++BUS().ADDRESS().word;
|
||||
MEMPTR().high = BUS().read();
|
||||
BUS().write(operand.high);
|
||||
operand.high = MEMPTR().high;
|
||||
}
|
||||
|
||||
void EightBit::Z80::blockCompare(const uint8_t a, uint8_t& f) {
|
||||
|
||||
const auto value = getByte(HL());
|
||||
const auto value = BUS().read(HL());
|
||||
uint8_t result = a - value;
|
||||
|
||||
setFlag(f, PF, --BC().word);
|
||||
@ -473,14 +487,14 @@ void EightBit::Z80::blockCompare(const uint8_t a, uint8_t& f) {
|
||||
|
||||
void EightBit::Z80::cpi(const uint8_t a, uint8_t& f) {
|
||||
blockCompare(a, f);
|
||||
HL().word++;
|
||||
MEMPTR().word++;
|
||||
++HL().word;
|
||||
++MEMPTR().word;
|
||||
}
|
||||
|
||||
void EightBit::Z80::cpd(const uint8_t a, uint8_t& f) {
|
||||
blockCompare(a, f);
|
||||
HL().word--;
|
||||
MEMPTR().word--;
|
||||
--HL().word;
|
||||
--MEMPTR().word;
|
||||
}
|
||||
|
||||
bool EightBit::Z80::cpir(const uint8_t a, uint8_t& f) {
|
||||
@ -488,7 +502,7 @@ bool EightBit::Z80::cpir(const uint8_t a, uint8_t& f) {
|
||||
MEMPTR() = PC();
|
||||
const auto again = (f & PF) && !(f & ZF); // See CPI
|
||||
if (LIKELY(again))
|
||||
MEMPTR().word--;
|
||||
--MEMPTR().word;
|
||||
return again;
|
||||
}
|
||||
|
||||
@ -497,13 +511,13 @@ bool EightBit::Z80::cpdr(const uint8_t a, uint8_t& f) {
|
||||
MEMPTR().word = PC().word - 1;
|
||||
const auto again = (f & PF) && !(f & ZF); // See CPD
|
||||
if (UNLIKELY(!again))
|
||||
MEMPTR().word--;
|
||||
--MEMPTR().word;
|
||||
return again;
|
||||
}
|
||||
|
||||
void EightBit::Z80::blockLoad(const uint8_t a, uint8_t& f, const register16_t source, const register16_t destination) {
|
||||
const auto value = getByte(source);
|
||||
setByte(destination, value);
|
||||
const auto value = BUS().read(source);
|
||||
BUS().write(destination, value);
|
||||
const auto xy = a + value;
|
||||
setFlag(f, XF, xy & 8);
|
||||
setFlag(f, YF, xy & 2);
|
||||
@ -513,14 +527,14 @@ void EightBit::Z80::blockLoad(const uint8_t a, uint8_t& f, const register16_t so
|
||||
|
||||
void EightBit::Z80::ldd(const uint8_t a, uint8_t& f) {
|
||||
blockLoad(a, f, HL(), DE());
|
||||
HL().word--;
|
||||
DE().word--;
|
||||
--HL().word;
|
||||
--DE().word;
|
||||
}
|
||||
|
||||
void EightBit::Z80::ldi(const uint8_t a, uint8_t& f) {
|
||||
blockLoad(a, f, HL(), DE());
|
||||
HL().word++;
|
||||
DE().word++;
|
||||
++HL().word;
|
||||
++DE().word;
|
||||
}
|
||||
|
||||
bool EightBit::Z80::ldir(const uint8_t a, uint8_t& f) {
|
||||
@ -541,20 +555,20 @@ bool EightBit::Z80::lddr(const uint8_t a, uint8_t& f) {
|
||||
|
||||
void EightBit::Z80::ini(uint8_t& f) {
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
MEMPTR().word++;
|
||||
++MEMPTR().word;
|
||||
readPort();
|
||||
auto value = BUS().DATA();
|
||||
setByte(HL().word++, value);
|
||||
const auto value = BUS().DATA();
|
||||
BUS().write(HL().word++, value);
|
||||
decrement(f, B());
|
||||
setFlag(f, NF);
|
||||
}
|
||||
|
||||
void EightBit::Z80::ind(uint8_t& f) {
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
MEMPTR().word--;
|
||||
--MEMPTR().word;
|
||||
readPort();
|
||||
auto value = BUS().DATA();
|
||||
setByte(HL().word--, value);
|
||||
const auto value = BUS().DATA();
|
||||
BUS().write(HL().word--, value);
|
||||
decrement(f, B());
|
||||
setFlag(f, NF);
|
||||
}
|
||||
@ -570,7 +584,7 @@ bool EightBit::Z80::indr(uint8_t& f) {
|
||||
}
|
||||
|
||||
void EightBit::Z80::blockOut(uint8_t& f) {
|
||||
const auto value = getByte();
|
||||
const auto value = BUS().read();
|
||||
BUS().ADDRESS() = BC();
|
||||
writePort();
|
||||
decrement(f, B());
|
||||
@ -602,20 +616,20 @@ bool EightBit::Z80::otdr(uint8_t& f) {
|
||||
}
|
||||
|
||||
void EightBit::Z80::rrd(uint8_t& a, uint8_t& f) {
|
||||
BUS().ADDRESS() = MEMPTR() = HL();
|
||||
const auto memory = getByte();
|
||||
MEMPTR().word++;
|
||||
setByte(promoteNibble(a) | highNibble(memory));
|
||||
MEMPTR() = BUS().ADDRESS() = HL();
|
||||
++MEMPTR().word;
|
||||
const auto memory = BUS().read();
|
||||
BUS().write(promoteNibble(a) | highNibble(memory));
|
||||
a = (a & 0xf0) | lowNibble(memory);
|
||||
adjustSZPXY<Z80>(f, a);
|
||||
clearFlag(f, NF | HC);
|
||||
}
|
||||
|
||||
void EightBit::Z80::rld(uint8_t& a, uint8_t& f) {
|
||||
BUS().ADDRESS() = MEMPTR() = HL();
|
||||
const auto memory = getByte();
|
||||
MEMPTR().word++;
|
||||
setByte(promoteNibble(memory) | lowNibble(a));
|
||||
MEMPTR() = BUS().ADDRESS() = HL();
|
||||
++MEMPTR().word;
|
||||
const auto memory = BUS().read();
|
||||
BUS().write(promoteNibble(memory) | lowNibble(a));
|
||||
a = (a & 0xf0) | highNibble(memory);
|
||||
adjustSZPXY<Z80>(f, a);
|
||||
clearFlag(f, NF | HC);
|
||||
@ -627,7 +641,7 @@ void EightBit::Z80::writePort(const uint8_t port, const uint8_t data) {
|
||||
MEMPTR() = BUS().ADDRESS();
|
||||
BUS().placeDATA(data);
|
||||
writePort();
|
||||
MEMPTR().low++;
|
||||
++MEMPTR().low;
|
||||
}
|
||||
|
||||
void EightBit::Z80::writePort() {
|
||||
@ -640,7 +654,7 @@ void EightBit::Z80::readPort(const uint8_t port, uint8_t& a) {
|
||||
MEMPTR() = BUS().ADDRESS();
|
||||
readPort();
|
||||
a = BUS().DATA();
|
||||
MEMPTR().low++;
|
||||
++MEMPTR().low;
|
||||
}
|
||||
|
||||
void EightBit::Z80::readPort() {
|
||||
@ -693,8 +707,7 @@ int EightBit::Z80::step() {
|
||||
|
||||
int EightBit::Z80::execute(const uint8_t opcode) {
|
||||
|
||||
if (UNLIKELY(raised(M1())))
|
||||
throw std::logic_error("M1 cannot be high");
|
||||
ASSUME(lowered(M1()));
|
||||
|
||||
if (LIKELY(!(m_prefixCB && m_displaced))) {
|
||||
++REFRESH();
|
||||
@ -726,16 +739,20 @@ int EightBit::Z80::execute(const uint8_t opcode) {
|
||||
UNREACHABLE;
|
||||
}
|
||||
|
||||
if (UNLIKELY(cycles() == 0))
|
||||
throw std::logic_error("Unhandled opcode");
|
||||
|
||||
ASSUME(cycles() > 0);
|
||||
return cycles();
|
||||
}
|
||||
|
||||
void EightBit::Z80::executeCB(uint8_t& a, uint8_t& f, const int x, const int y, const int z) {
|
||||
ASSUME(x >= 0);
|
||||
ASSUME(x <= 3);
|
||||
ASSUME(y >= 0);
|
||||
ASSUME(y <= 7);
|
||||
ASSUME(z >= 0);
|
||||
ASSUME(z <= 7);
|
||||
switch (x) {
|
||||
case 0: { // rot[y] r[z]
|
||||
auto operand = LIKELY(!m_displaced) ? R(z, a) : getByte(displacedAddress());
|
||||
auto operand = LIKELY(!m_displaced) ? R(z, a) : BUS().read(displacedAddress());
|
||||
switch (y) {
|
||||
case 0:
|
||||
operand = rlc(f, operand);
|
||||
@ -772,7 +789,7 @@ void EightBit::Z80::executeCB(uint8_t& a, uint8_t& f, const int x, const int y,
|
||||
} else {
|
||||
if (LIKELY(z != 6))
|
||||
R2(z, a, operand);
|
||||
setByte(operand);
|
||||
BUS().write(operand);
|
||||
addCycles(15);
|
||||
}
|
||||
addCycles(8);
|
||||
@ -788,7 +805,7 @@ void EightBit::Z80::executeCB(uint8_t& a, uint8_t& f, const int x, const int y,
|
||||
adjustXY<Z80>(f, operand);
|
||||
}
|
||||
} else {
|
||||
bit(f, y, getByte(displacedAddress()));
|
||||
bit(f, y, BUS().read(displacedAddress()));
|
||||
adjustXY<Z80>(f, MEMPTR().high);
|
||||
addCycles(12);
|
||||
}
|
||||
@ -800,9 +817,9 @@ void EightBit::Z80::executeCB(uint8_t& a, uint8_t& f, const int x, const int y,
|
||||
if (UNLIKELY(z == 6))
|
||||
addCycles(7);
|
||||
} else {
|
||||
auto operand = getByte(displacedAddress());
|
||||
auto operand = BUS().read(displacedAddress());
|
||||
operand = res(y, operand);
|
||||
setByte(operand);
|
||||
BUS().write(operand);
|
||||
R2(z, a, operand);
|
||||
addCycles(15);
|
||||
}
|
||||
@ -814,9 +831,9 @@ void EightBit::Z80::executeCB(uint8_t& a, uint8_t& f, const int x, const int y,
|
||||
if (UNLIKELY(z == 6))
|
||||
addCycles(7);
|
||||
} else {
|
||||
auto operand = getByte(displacedAddress());
|
||||
auto operand = BUS().read(displacedAddress());
|
||||
operand = set(y, operand);
|
||||
setByte(operand);
|
||||
BUS().write(operand);
|
||||
R2(z, a, operand);
|
||||
addCycles(15);
|
||||
}
|
||||
@ -827,6 +844,16 @@ void EightBit::Z80::executeCB(uint8_t& a, uint8_t& f, const int x, const int y,
|
||||
}
|
||||
|
||||
void EightBit::Z80::executeED(uint8_t& a, uint8_t& f, const int x, const int y, const int z, const int p, const int q) {
|
||||
ASSUME(x >= 0);
|
||||
ASSUME(x <= 3);
|
||||
ASSUME(y >= 0);
|
||||
ASSUME(y <= 7);
|
||||
ASSUME(z >= 0);
|
||||
ASSUME(z <= 7);
|
||||
ASSUME(p >= 0);
|
||||
ASSUME(p <= 3);
|
||||
ASSUME(q >= 0);
|
||||
ASSUME(q <= 1);
|
||||
switch (x) {
|
||||
case 0:
|
||||
case 3: // Invalid instruction, equivalent to NONI followed by NOP
|
||||
@ -836,7 +863,7 @@ void EightBit::Z80::executeED(uint8_t& a, uint8_t& f, const int x, const int y,
|
||||
switch (z) {
|
||||
case 0: // Input from port with 16-bit address
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
MEMPTR().word++;
|
||||
++MEMPTR().word;
|
||||
readPort();
|
||||
if (LIKELY(y != 6)) // IN r[y],(C)
|
||||
R(y, a, BUS().DATA());
|
||||
@ -846,7 +873,7 @@ void EightBit::Z80::executeED(uint8_t& a, uint8_t& f, const int x, const int y,
|
||||
break;
|
||||
case 1: // Output to port with 16-bit address
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
MEMPTR().word++;
|
||||
++MEMPTR().word;
|
||||
if (UNLIKELY(y == 6)) // OUT (C),0
|
||||
BUS().placeDATA(0);
|
||||
else // OUT (C),r[y]
|
||||
@ -1061,6 +1088,16 @@ void EightBit::Z80::executeED(uint8_t& a, uint8_t& f, const int x, const int y,
|
||||
}
|
||||
|
||||
void EightBit::Z80::executeOther(uint8_t& a, uint8_t& f, const int x, const int y, const int z, const int p, const int q) {
|
||||
ASSUME(x >= 0);
|
||||
ASSUME(x <= 3);
|
||||
ASSUME(y >= 0);
|
||||
ASSUME(y <= 7);
|
||||
ASSUME(z >= 0);
|
||||
ASSUME(z <= 7);
|
||||
ASSUME(p >= 0);
|
||||
ASSUME(p <= 3);
|
||||
ASSUME(q >= 0);
|
||||
ASSUME(q <= 1);
|
||||
switch (x) {
|
||||
case 0:
|
||||
switch (z) {
|
||||
@ -1113,14 +1150,16 @@ void EightBit::Z80::executeOther(uint8_t& a, uint8_t& f, const int x, const int
|
||||
case 0:
|
||||
switch (p) {
|
||||
case 0: // LD (BC),A
|
||||
MEMPTR() = BC();
|
||||
setByte(MEMPTR().word++, a);
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
++MEMPTR().word;
|
||||
BUS().write(a);
|
||||
MEMPTR().high = a;
|
||||
addCycles(7);
|
||||
break;
|
||||
case 1: // LD (DE),A
|
||||
MEMPTR() = DE();
|
||||
setByte(MEMPTR().word++, a);
|
||||
MEMPTR() = BUS().ADDRESS() = DE();
|
||||
++MEMPTR().word;
|
||||
BUS().write(a);
|
||||
MEMPTR().high = a;
|
||||
addCycles(7);
|
||||
break;
|
||||
@ -1130,8 +1169,9 @@ void EightBit::Z80::executeOther(uint8_t& a, uint8_t& f, const int x, const int
|
||||
addCycles(16);
|
||||
break;
|
||||
case 3: // LD (nn),A
|
||||
MEMPTR() = fetchWord();
|
||||
setByte(MEMPTR().word++, a);
|
||||
MEMPTR() = BUS().ADDRESS() = fetchWord();
|
||||
++MEMPTR().word;
|
||||
BUS().write(a);
|
||||