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Further work on the slow migration to a cycle accurate 6502

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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon 2019-01-03 01:04:12 +00:00
parent 6c582f6349
commit 556e06426e
3 changed files with 105 additions and 97 deletions
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8
M6502/inc/mos6502.h
View File

@ -129,7 +129,7 @@ namespace EightBit {
if (condition) {
jump(destination);
if (UNLIKELY(PC().high != page))
addCycle();
Processor::busRead({ PC().low, page });
}
return !!condition;
}
@ -146,6 +146,12 @@ namespace EightBit {
return data;
}
void busReadModifyWrite(const uint8_t data) {
// The read will have already taken place...
busWrite();
Processor::busWrite(data);
}
// Instruction implementations
uint8_t andr(uint8_t operand, uint8_t data);

190
M6502/src/mos6502.cpp
View File

@ -97,140 +97,140 @@ int EightBit::MOS6502::execute() {
switch (opcode()) {
case 0x00: brk(); break; // BRK
case 0x01: addCycle(); A() = orr(A(), AM_IndexedIndirectX()); break; // ORA (indexed indirect X)
case 0x01: A() = orr(A(), AM_IndexedIndirectX()); break; // ORA (indexed indirect X)
case 0x02: break;
case 0x03: addCycles(2); slo(AM_IndexedIndirectX()); break; // *SLO (indexed indirect X)
case 0x03: slo(AM_IndexedIndirectX()); break; // *SLO (indexed indirect X)
case 0x04: AM_ZeroPage(); break; // *NOP (zero page)
case 0x05: A() = orr(A(), AM_ZeroPage()); break; // ORA (zero page)
case 0x06: addCycle(); Processor::busWrite(asl(AM_ZeroPage())); break; // ASL (zero page)
case 0x07: addCycle(); slo(AM_ZeroPage()); break; // *SLO (zero page)
case 0x06: busReadModifyWrite(asl(AM_ZeroPage())); break; // ASL (zero page)
case 0x07: slo(AM_ZeroPage()); break; // *SLO (zero page)
case 0x08: addCycle(); php(); break; // PHP
case 0x09: A() = orr(A(), AM_Immediate()); break; // ORA (immediate)
case 0x0a: addCycle(); A() = asl(A()); break; // ASL A
case 0x0b: addCycle(); anc(AM_Immediate()); break; // *ANC (immediate)
case 0x0c: AM_Absolute(); break; // *NOP (absolute)
case 0x0d: A() = orr(A(), AM_Absolute()); break; // ORA (absolute)
case 0x0e: addCycle(); Processor::busWrite(asl(AM_Absolute())); break; // ASL (absolute)
case 0x0f: addCycle(); slo(AM_Absolute()); break; // *SLO (absolute)
case 0x0e: busReadModifyWrite(asl(AM_Absolute())); break; // ASL (absolute)
case 0x0f: slo(AM_Absolute()); break; // *SLO (absolute)
case 0x10: branch(!negative()); break; // BPL (relative)
case 0x11: A() = orr(A(), AM_IndirectIndexedY()); break; // ORA (indirect indexed Y)
case 0x12: break;
case 0x13: addCycle(); slo(AM_IndirectIndexedY()); break; // *SLO (indirect indexed Y)
case 0x14: addCycle(); AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x15: addCycle(); A() = orr(A(), AM_ZeroPageX()); break; // ORA (zero page, X)
case 0x16: addCycles(2); Processor::busWrite(asl(AM_ZeroPageX())); break; // ASL (zero page, X)
case 0x17: addCycles(2); slo(AM_ZeroPageX()); break; // *SLO (zero page, X)
case 0x13: slo(AM_IndirectIndexedY()); break; // *SLO (indirect indexed Y)
case 0x14: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x15: A() = orr(A(), AM_ZeroPageX()); break; // ORA (zero page, X)
case 0x16: busReadModifyWrite(asl(AM_ZeroPageX())); break; // ASL (zero page, X)
case 0x17: slo(AM_ZeroPageX()); break; // *SLO (zero page, X)
case 0x18: addCycle(); clearFlag(P(), CF); break; // CLC
case 0x19: A() = orr(A(), AM_AbsoluteY()); break; // ORA (absolute, Y)
case 0x1a: addCycle(); break; // *NOP (implied)
case 0x1b: addCycle(); slo(AM_AbsoluteY()); break; // *SLO (absolute, Y)
case 0x1b: slo(AM_AbsoluteY()); break; // *SLO (absolute, Y)
case 0x1c: AM_AbsoluteX(); break; // *NOP (absolute, X)
case 0x1d: A() = orr(A(), AM_AbsoluteX()); break; // ORA (absolute, X)
case 0x1e: addCycles(2); Processor::busWrite(asl(AM_AbsoluteX())); break; // ASL (absolute, X)
case 0x1f: addCycle(); slo(AM_AbsoluteX()); break; // *SLO (absolute, X)
case 0x1e: addCycle(); busReadModifyWrite(asl(AM_AbsoluteX())); break; // ASL (absolute, X)
case 0x1f: slo(AM_AbsoluteX()); break; // *SLO (absolute, X)
case 0x20: addCycle(); jsr(Address_Absolute()); break; // JSR (absolute)
case 0x21: addCycle(); A() = andr(A(), AM_IndexedIndirectX()); break; // AND (indexed indirect X)
case 0x21: A() = andr(A(), AM_IndexedIndirectX()); break; // AND (indexed indirect X)
case 0x22: break;
case 0x23: addCycles(2); rla(AM_IndexedIndirectX()); break; // *RLA (indexed indirect X)
case 0x23: rla(AM_IndexedIndirectX()); break; // *RLA (indexed indirect X)
case 0x24: bit(A(), AM_ZeroPage()); break; // BIT (zero page)
case 0x25: A() = andr(A(), AM_ZeroPage()); break; // AND (zero page)
case 0x26: addCycle(); Processor::busWrite(rol(AM_ZeroPage())); break; // ROL (zero page)
case 0x27: addCycle(); rla(AM_ZeroPage()); break; // *RLA (zero page)
case 0x26: busReadModifyWrite(rol(AM_ZeroPage())); break; // ROL (zero page)
case 0x27: rla(AM_ZeroPage()); break; // *RLA (zero page)
case 0x28: addCycles(2); plp(); break; // PLP
case 0x29: A() = andr(A(), AM_Immediate()); break; // AND (immediate)
case 0x2a: addCycle(); A() = rol(A()); break; // ROL A
case 0x2b: addCycle(); anc(AM_Immediate()); break; // *ANC (immediate)
case 0x2c: bit(A(), AM_Absolute()); break; // BIT (absolute)
case 0x2d: A() = andr(A(), AM_Absolute()); break; // AND (absolute)
case 0x2e: addCycle(); Processor::busWrite(rol(AM_Absolute())); break; // ROL (absolute)
case 0x2f: addCycle(); rla(AM_Absolute()); break; // *RLA (absolute)
case 0x2e: busReadModifyWrite(rol(AM_Absolute())); break; // ROL (absolute)
case 0x2f: rla(AM_Absolute()); break; // *RLA (absolute)
case 0x30: branch(negative()); break; // BMI
case 0x31: A() = andr(A(), AM_IndirectIndexedY()); break; // AND (indirect indexed Y)
case 0x32: break;
case 0x33: addCycle(); rla(AM_IndirectIndexedY()); break; // *RLA (indirect indexed Y)
case 0x34: addCycle(); AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x35: addCycle(); A() = andr(A(), AM_ZeroPageX()); break; // AND (zero page, X)
case 0x36: addCycles(2); Processor::busWrite(rol(AM_ZeroPageX())); break; // ROL (zero page, X)
case 0x37: addCycles(2); rla(AM_ZeroPageX()); break; // *RLA (zero page, X)
case 0x33: rla(AM_IndirectIndexedY()); break; // *RLA (indirect indexed Y)
case 0x34: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x35: A() = andr(A(), AM_ZeroPageX()); break; // AND (zero page, X)
case 0x36: busReadModifyWrite(rol(AM_ZeroPageX())); break; // ROL (zero page, X)
case 0x37: rla(AM_ZeroPageX()); break; // *RLA (zero page, X)
case 0x38: addCycle(); setFlag(P(), CF); break; // SEC
case 0x39: A() = andr(A(), AM_AbsoluteY()); break; // AND (absolute, Y)
case 0x3a: addCycle(); break; // *NOP (implied)
case 0x3b: addCycle(); rla(AM_AbsoluteY()); break; // *RLA (absolute, Y)
case 0x3b: rla(AM_AbsoluteY()); break; // *RLA (absolute, Y)
case 0x3c: AM_AbsoluteX(); break; // *NOP (absolute, X)
case 0x3d: A() = andr(A(), AM_AbsoluteX()); break; // AND (absolute, X)
case 0x3e: addCycles(2); Processor::busWrite(rol(AM_AbsoluteX())); break; // ROL (absolute, X)
case 0x3f: addCycle(); rla(AM_AbsoluteX()); break; // *RLA (absolute, X)
case 0x3e: addCycle(); busReadModifyWrite(rol(AM_AbsoluteX())); break; // ROL (absolute, X)
case 0x3f: rla(AM_AbsoluteX()); break; // *RLA (absolute, X)
case 0x40: addCycles(2); rti(); break; // RTI
case 0x41: addCycle(); A() = eorr(A(), AM_IndexedIndirectX()); break; // EOR (indexed indirect X)
case 0x41: A() = eorr(A(), AM_IndexedIndirectX()); break; // EOR (indexed indirect X)
case 0x42: break;
case 0x43: addCycles(2); sre(AM_IndexedIndirectX()); break; // *SRE (indexed indirect X)
case 0x43: sre(AM_IndexedIndirectX()); break; // *SRE (indexed indirect X)
case 0x44: AM_ZeroPage(); break; // *NOP (zero page)
case 0x45: A() = eorr(A(), AM_ZeroPage()); break; // EOR (zero page)
case 0x46: addCycle(); Processor::busWrite(lsr(AM_ZeroPage())); break; // LSR (zero page)
case 0x47: addCycle(); sre(AM_ZeroPage()); break; // *SRE (zero page)
case 0x46: busReadModifyWrite(lsr(AM_ZeroPage())); break; // LSR (zero page)
case 0x47: sre(AM_ZeroPage()); break; // *SRE (zero page)
case 0x48: addCycle(); push(A()); break; // PHA
case 0x49: A() = eorr(A(), AM_Immediate()); break; // EOR (immediate)
case 0x4a: addCycle(); A() = lsr(A()); break; // LSR A
case 0x4b: asr(AM_Immediate()); break; // *ASR (immediate)
case 0x4c: jump(Address_Absolute()); break; // JMP (absolute)
case 0x4d: A() = eorr(A(), AM_Absolute()); break; // EOR (absolute)
case 0x4e: addCycle(); Processor::busWrite(lsr(AM_Absolute())); break; // LSR (absolute)
case 0x4f: addCycle(); sre(AM_Absolute()); break; // *SRE (absolute)
case 0x4e: busReadModifyWrite(lsr(AM_Absolute())); break; // LSR (absolute)
case 0x4f: sre(AM_Absolute()); break; // *SRE (absolute)
case 0x50: branch(!overflow()); break; // BVC (relative)
case 0x51: A() = eorr(A(), AM_IndirectIndexedY()); break; // EOR (indirect indexed Y)
case 0x52: break;
case 0x53: addCycle(); sre(AM_IndirectIndexedY()); break; // *SRE (indirect indexed Y)
case 0x54: addCycle(); AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x55: addCycle(); A() = eorr(A(), AM_ZeroPageX()); break; // EOR (zero page, X)
case 0x56: addCycles(2); Processor::busWrite(lsr(AM_ZeroPageX())); break; // LSR (zero page, X)
case 0x57: addCycles(2); sre(AM_ZeroPageX()); break; // *SRE (zero page, X)
case 0x53: sre(AM_IndirectIndexedY()); break; // *SRE (indirect indexed Y)
case 0x54: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x55: A() = eorr(A(), AM_ZeroPageX()); break; // EOR (zero page, X)
case 0x56: busReadModifyWrite(lsr(AM_ZeroPageX())); break; // LSR (zero page, X)
case 0x57: sre(AM_ZeroPageX()); break; // *SRE (zero page, X)
case 0x58: addCycle(); clearFlag(P(), IF); break; // CLI
case 0x59: A() = eorr(A(), AM_AbsoluteY()); break; // EOR (absolute, Y)
case 0x5a: addCycle(); break; // *NOP (implied)
case 0x5b: addCycle(); sre(AM_AbsoluteY()); break; // *SRE (absolute, Y)
case 0x5b: sre(AM_AbsoluteY()); break; // *SRE (absolute, Y)
case 0x5c: AM_AbsoluteX(); break; // *NOP (absolute, X)
case 0x5d: A() = eorr(A(), AM_AbsoluteX()); break; // EOR (absolute, X)
case 0x5e: addCycles(2); Processor::busWrite(lsr(AM_AbsoluteX())); break; // LSR (absolute, X)
case 0x5f: addCycle(); sre(AM_AbsoluteX()); break; // *SRE (absolute, X)
case 0x5e: addCycle(); busReadModifyWrite(lsr(AM_AbsoluteX())); break; // LSR (absolute, X)
case 0x5f: sre(AM_AbsoluteX()); break; // *SRE (absolute, X)
case 0x60: addCycles(3); rts(); break; // RTS
case 0x61: addCycle(); A() = adc(A(), AM_IndexedIndirectX()); break; // ADC (indexed indirect X)
case 0x61: A() = adc(A(), AM_IndexedIndirectX()); break; // ADC (indexed indirect X)
case 0x62: break;
case 0x63: addCycles(2); rra(AM_IndexedIndirectX()); break; // *RRA (indexed indirect X)
case 0x63: rra(AM_IndexedIndirectX()); break; // *RRA (indexed indirect X)
case 0x64: AM_ZeroPage(); break; // *NOP (zero page)
case 0x65: A() = adc(A(), AM_ZeroPage()); break; // ADC (zero page)
case 0x66: addCycle(); Processor::busWrite(ror(AM_ZeroPage())); break; // ROR (zero page)
case 0x67: addCycle(); rra(AM_ZeroPage()); break; // *RRA (zero page)
case 0x66: busReadModifyWrite(ror(AM_ZeroPage())); break; // ROR (zero page)
case 0x67: rra(AM_ZeroPage()); break; // *RRA (zero page)
case 0x68: addCycles(2); A() = through(pop()); break; // PLA
case 0x69: A() = adc(A(), AM_Immediate()); break; // ADC (immediate)
case 0x6a: addCycle(); A() = ror(A()); break; // ROR A
case 0x6b: addCycle(); arr(AM_Immediate()); break; // *ARR (immediate)
case 0x6c: jump(Address_Indirect()); break; // JMP (indirect)
case 0x6d: A() = adc(A(), AM_Absolute()); break; // ADC (absolute)
case 0x6e: addCycle(); Processor::busWrite(ror(AM_Absolute())); break; // ROR (absolute)
case 0x6f: addCycle(); rra(AM_Absolute()); break; // *RRA (absolute)
case 0x6e: busReadModifyWrite(ror(AM_Absolute())); break; // ROR (absolute)
case 0x6f: rra(AM_Absolute()); break; // *RRA (absolute)
case 0x70: branch(overflow()); break; // BVS (relative)
case 0x71: A() = adc(A(), AM_IndirectIndexedY()); break; // ADC (indirect indexed Y)
case 0x72: break;
case 0x73: addCycle(); rra(AM_IndirectIndexedY()); break; // *RRA (indirect indexed Y)
case 0x74: addCycle(); AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x75: addCycle(); A() = adc(A(), AM_ZeroPageX()); break; // ADC (zero page, X)
case 0x76: addCycles(2); Processor::busWrite(ror(AM_ZeroPageX())); break; // ROR (zero page, X)
case 0x77: addCycles(2); rra(AM_ZeroPageX()); break; // *RRA (zero page, X)
case 0x73: rra(AM_IndirectIndexedY()); break; // *RRA (indirect indexed Y)
case 0x74: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x75: A() = adc(A(), AM_ZeroPageX()); break; // ADC (zero page, X)
case 0x76: busReadModifyWrite(ror(AM_ZeroPageX())); break; // ROR (zero page, X)
case 0x77: rra(AM_ZeroPageX()); break; // *RRA (zero page, X)
case 0x78: addCycle(); setFlag(P(), IF); break; // SEI
case 0x79: A() = adc(A(), AM_AbsoluteY()); break; // ADC (absolute, Y)
case 0x7a: addCycle(); break; // *NOP (implied)
case 0x7b: addCycle(); rra(AM_AbsoluteY()); break; // *RRA (absolute, Y)
case 0x7b: rra(AM_AbsoluteY()); break; // *RRA (absolute, Y)
case 0x7c: AM_AbsoluteX(); break; // *NOP (absolute, X)
case 0x7d: A() = adc(A(), AM_AbsoluteX()); break; // ADC (absolute, X)
case 0x7e: addCycles(2); Processor::busWrite(ror(AM_AbsoluteX())); break; // ROR (absolute, X)
case 0x7f: addCycle(); rra(AM_AbsoluteX()); break; // *RRA (absolute, X)
case 0x7e: addCycle(); busReadModifyWrite(ror(AM_AbsoluteX())); break; // ROR (absolute, X)
case 0x7f: rra(AM_AbsoluteX()); break; // *RRA (absolute, X)
case 0x80: AM_Immediate(); break; // *NOP (immediate)
case 0x81: addCycle(); Processor::busWrite(Address_IndexedIndirectX(), A()); break; // STA (indexed indirect X)
@ -267,9 +267,9 @@ int EightBit::MOS6502::execute() {
case 0x9f: break;
case 0xa0: Y() = through(AM_Immediate()); break; // LDY (immediate)
case 0xa1: addCycle(); A() = through(AM_IndexedIndirectX()); break; // LDA (indexed indirect X)
case 0xa1: A() = through(AM_IndexedIndirectX()); break; // LDA (indexed indirect X)
case 0xa2: X() = through(AM_Immediate()); break; // LDX (immediate)
case 0xa3: addCycle(); A() = X() = through(AM_IndexedIndirectX()); break; // *LAX (indexed indirect X)
case 0xa3: A() = X() = through(AM_IndexedIndirectX()); break; // *LAX (indexed indirect X)
case 0xa4: Y() = through(AM_ZeroPage()); break; // LDY (zero page)
case 0xa5: A() = through(AM_ZeroPage()); break; // LDA (zero page)
case 0xa6: X() = through(AM_ZeroPage()); break; // LDX (zero page)
@ -287,8 +287,8 @@ int EightBit::MOS6502::execute() {
case 0xb1: A() = through(AM_IndirectIndexedY()); break; // LDA (indirect indexed Y)
case 0xb2: break;
case 0xb3: A() = X() = through(AM_IndirectIndexedY()); break; // *LAX (indirect indexed Y)
case 0xb4: addCycle(); Y() = through(AM_ZeroPageX()); break; // LDY (zero page, X)
case 0xb5: addCycle(); A() = through(AM_ZeroPageX()); break; // LDA (zero page, X)
case 0xb4: Y() = through(AM_ZeroPageX()); break; // LDY (zero page, X)
case 0xb5: A() = through(AM_ZeroPageX()); break; // LDA (zero page, X)
case 0xb6: addCycle(); X() = through(AM_ZeroPageY()); break; // LDX (zero page, Y)
case 0xb7: addCycle(); A() = X() = through(AM_ZeroPageY()); break; // *LAX (zero page, Y)
case 0xb8: addCycle(); clearFlag(P(), VF); break; // CLV
@ -301,72 +301,72 @@ int EightBit::MOS6502::execute() {
case 0xbf: A() = X() = through(AM_AbsoluteY()); break; // *LAX (absolute, Y)
case 0xc0: cmp(Y(), AM_Immediate()); break; // CPY (immediate)
case 0xc1: addCycle(); cmp(A(), AM_IndexedIndirectX()); break; // CMP (indexed indirect X)
case 0xc1: cmp(A(), AM_IndexedIndirectX()); break; // CMP (indexed indirect X)
case 0xc2: AM_Immediate(); break; // *NOP (immediate)
case 0xc3: addCycles(2); dcp(AM_IndexedIndirectX()); break; // *DCP (indexed indirect X)
case 0xc3: dcp(AM_IndexedIndirectX()); break; // *DCP (indexed indirect X)
case 0xc4: cmp(Y(), AM_ZeroPage()); break; // CPY (zero page)
case 0xc5: cmp(A(), AM_ZeroPage()); break; // CMP (zero page)
case 0xc6: addCycle(); Processor::busWrite(dec(AM_ZeroPage())); break; // DEC (zero page)
case 0xc7: addCycle(); dcp(AM_ZeroPage()); break; // *DCP (zero page)
case 0xc6: busReadModifyWrite(dec(AM_ZeroPage())); break; // DEC (zero page)
case 0xc7: dcp(AM_ZeroPage()); break; // *DCP (zero page)
case 0xc8: addCycle(); Y() = inc(Y()); break; // INY
case 0xc9: cmp(A(), AM_Immediate()); break; // CMP (immediate)
case 0xca: addCycle(); X() = dec(X()); break; // DEX
case 0xcb: axs(AM_Immediate()); break; // *AXS (immediate)
case 0xcc: cmp(Y(), AM_Absolute()); break; // CPY (absolute)
case 0xcd: cmp(A(), AM_Absolute()); break; // CMP (absolute)
case 0xce: addCycle(); Processor::busWrite(dec(AM_Absolute())); break; // DEC (absolute)
case 0xcf: addCycle(); dcp(AM_Absolute()); break; // *DCP (absolute)
case 0xce: busReadModifyWrite(dec(AM_Absolute())); break; // DEC (absolute)
case 0xcf: dcp(AM_Absolute()); break; // *DCP (absolute)
case 0xd0: branch(!zero()); break; // BNE
case 0xd1: cmp(A(), AM_IndirectIndexedY()); break; // CMP (indirect indexed Y)
case 0xd2: break;
case 0xd3: addCycle(); dcp(AM_IndirectIndexedY()); break; // *DCP (indirect indexed Y)
case 0xd4: addCycle(); AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0xd5: addCycle(); cmp(A(), AM_ZeroPageX()); break; // CMP (zero page, X)
case 0xd6: addCycles(2); Processor::busWrite(dec(AM_ZeroPageX())); break; // DEC (zero page, X)
case 0xd7: addCycles(2); dcp(AM_ZeroPageX()); break; // *DCP (zero page, X)
case 0xd3: dcp(AM_IndirectIndexedY()); break; // *DCP (indirect indexed Y)
case 0xd4: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0xd5: cmp(A(), AM_ZeroPageX()); break; // CMP (zero page, X)
case 0xd6: busReadModifyWrite(dec(AM_ZeroPageX())); break; // DEC (zero page, X)
case 0xd7: dcp(AM_ZeroPageX()); break; // *DCP (zero page, X)
case 0xd8: addCycle(); clearFlag(P(), DF); break; // CLD
case 0xd9: cmp(A(), AM_AbsoluteY()); break; // CMP (absolute, Y)
case 0xda: addCycle(); break; // *NOP (implied)
case 0xdb: addCycle(); dcp(AM_AbsoluteY()); break; // *DCP (absolute, Y)
case 0xdb: dcp(AM_AbsoluteY()); break; // *DCP (absolute, Y)
case 0xdc: AM_AbsoluteX(); break; // *NOP (absolute, X)
case 0xdd: cmp(A(), AM_AbsoluteX()); break; // CMP (absolute, X)
case 0xde: addCycles(2); Processor::busWrite(dec(AM_AbsoluteX())); break; // DEC (absolute, X)
case 0xdf: addCycle(); dcp(AM_AbsoluteX()); break; // *DCP (absolute, X)
case 0xde: addCycle(); busReadModifyWrite(dec(AM_AbsoluteX())); break; // DEC (absolute, X)
case 0xdf: dcp(AM_AbsoluteX()); break; // *DCP (absolute, X)
case 0xe0: cmp(X(), AM_Immediate()); break; // CPX (immediate)
case 0xe1: addCycle(); A() = sbc(A(), AM_IndexedIndirectX()); break; // SBC (indexed indirect X)
case 0xe1: A() = sbc(A(), AM_IndexedIndirectX()); break; // SBC (indexed indirect X)
case 0xe2: AM_Immediate(); break; // *NOP (immediate)
case 0xe3: addCycles(2); isb(AM_IndexedIndirectX()); break; // *ISB (indexed indirect X)
case 0xe3: isb(AM_IndexedIndirectX()); break; // *ISB (indexed indirect X)
case 0xe4: cmp(X(), AM_ZeroPage()); break; // CPX (zero page)
case 0xe5: A() = sbc(A(), AM_ZeroPage()); break; // SBC (zero page)
case 0xe6: addCycle(); Processor::busWrite(inc(AM_ZeroPage())); break; // INC (zero page)
case 0xe7: addCycle(); isb(AM_ZeroPage()); break; // *ISB (zero page)
case 0xe6: busReadModifyWrite(inc(AM_ZeroPage())); break; // INC (zero page)
case 0xe7: isb(AM_ZeroPage()); break; // *ISB (zero page)
case 0xe8: addCycle(); X() = inc(X()); break; // INX
case 0xe9: A() = sbc(A(), AM_Immediate()); break; // SBC (immediate)
case 0xea: addCycle(); break; // NOP
case 0xeb: A() = sbc(A(), AM_Immediate()); break; // *SBC (immediate)
case 0xec: cmp(X(), AM_Absolute()); break; // CPX (absolute)
case 0xed: A() = sbc(A(), AM_Absolute()); break; // SBC (absolute)
case 0xee: addCycle(); Processor::busWrite(inc(AM_Absolute())); break; // INC (absolute)
case 0xef: addCycle(); isb(AM_Absolute()); break; // *ISB (absolute)
case 0xee: busReadModifyWrite(inc(AM_Absolute())); break; // INC (absolute)
case 0xef: isb(AM_Absolute()); break; // *ISB (absolute)
case 0xf0: branch(zero()); break; // BEQ
case 0xf1: A() = sbc(A(), AM_IndirectIndexedY()); break; // SBC (indirect indexed Y)
case 0xf2: break;
case 0xf3: addCycle(); isb(AM_IndirectIndexedY()); break; // *ISB (indirect indexed Y)
case 0xf4: addCycle(); AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0xf5: addCycle(); A() = sbc(A(), AM_ZeroPageX()); break; // SBC (zero page, X)
case 0xf6: addCycles(2); Processor::busWrite(inc(AM_ZeroPageX())); break; // INC (zero page, X)
case 0xf7: addCycles(2); isb(AM_ZeroPageX()); break; // *ISB (zero page, X)
case 0xf3: isb(AM_IndirectIndexedY()); break; // *ISB (indirect indexed Y)
case 0xf4: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0xf5: A() = sbc(A(), AM_ZeroPageX()); break; // SBC (zero page, X)
case 0xf6: busReadModifyWrite(inc(AM_ZeroPageX())); break; // INC (zero page, X)
case 0xf7: isb(AM_ZeroPageX()); break; // *ISB (zero page, X)
case 0xf8: addCycle(); setFlag(P(), DF); break; // SED
case 0xf9: A() = sbc(A(), AM_AbsoluteY()); break; // SBC (absolute, Y)
case 0xfa: addCycle(); break; // *NOP (implied)
case 0xfb: addCycle(); isb(AM_AbsoluteY()); break; // *ISB (absolute, Y)
case 0xfb: isb(AM_AbsoluteY()); break; // *ISB (absolute, Y)
case 0xfc: AM_AbsoluteX(); break; // *NOP (absolute, X)
case 0xfd: A() = sbc(A(), AM_AbsoluteX()); break; // SBC (absolute, X)
case 0xfe: addCycles(2); Processor::busWrite(inc(AM_AbsoluteX())); break; // INC (absolute, X)
case 0xff: addCycle(); isb(AM_AbsoluteX()); break; // *ISB (absolute, X)
case 0xfe: addCycle(); busReadModifyWrite(inc(AM_AbsoluteX())); break; // INC (absolute, X)
case 0xff: isb(AM_AbsoluteX()); break; // *ISB (absolute, X)
}
ASSUME(cycles() > 0);
@ -468,6 +468,7 @@ uint8_t EightBit::MOS6502::AM_AbsoluteY() {
}
uint8_t EightBit::MOS6502::AM_ZeroPageX() {
addCycle();
return Processor::busRead(Address_ZeroPageX());
}
@ -476,6 +477,7 @@ uint8_t EightBit::MOS6502::AM_ZeroPageY() {
}
uint8_t EightBit::MOS6502::AM_IndexedIndirectX() {
addCycle();
return Processor::busRead(Address_IndexedIndirectX());
}
@ -674,31 +676,31 @@ void EightBit::MOS6502::axs(const uint8_t value) {
}
void EightBit::MOS6502::dcp(const uint8_t value) {
Processor::busWrite(dec(value));
busReadModifyWrite(dec(value));
cmp(A(), BUS().DATA());
}
void EightBit::MOS6502::isb(const uint8_t value) {
Processor::busWrite(inc(value));
busReadModifyWrite(inc(value));
A() = sbc(A(), BUS().DATA());
}
void EightBit::MOS6502::rla(const uint8_t value) {
Processor::busWrite(rol(value));
busReadModifyWrite(rol(value));
A() = andr(A(), BUS().DATA());
}
void EightBit::MOS6502::rra(const uint8_t value) {
Processor::busWrite(ror(value));
busReadModifyWrite(ror(value));
A() = adc(A(), BUS().DATA());
}
void EightBit::MOS6502::slo(const uint8_t value) {
Processor::busWrite(asl(value));
busReadModifyWrite(asl(value));
A() = orr(A(), BUS().DATA());
}
void EightBit::MOS6502::sre(const uint8_t value) {
Processor::busWrite(lsr(value));
busReadModifyWrite(lsr(value));
A() = eorr(A(), BUS().DATA());
}

4
inc/Processor.h
View File

@ -55,8 +55,8 @@ namespace EightBit {
void busWrite(uint8_t data);
virtual void busWrite();
[[nodiscard]] uint8_t busRead(register16_t address);
[[nodiscard]] virtual uint8_t busRead();
uint8_t busRead(register16_t address);
virtual uint8_t busRead();
[[nodiscard]] auto getBytePaged(const uint8_t page, const uint8_t offset) {
return busRead(register16_t(offset, page));