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Ensure that memory read/write events are triggered.

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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
This commit is contained in:
Adrian.Conlon 2017-07-16 10:40:38 +01:00
parent d522b694bd
commit 71d213faec
2 changed files with 63 additions and 11 deletions

26
M6502/inc/mos6502.h

@ -140,30 +140,33 @@ namespace EightBit {
#pragma region References
uint8_t& AM_A() {
m_busRW = false;
return A();
}
uint8_t& AM_Immediate() {
m_busRW = false;
FetchByte();
return m_memory.reference();
}
uint8_t& AM_Absolute() {
m_busRW = true;
Address_Absolute();
m_memory.ADDRESS() = m_memptr;
return m_memory.reference();
}
uint8_t& AM_ZeroPage() {
m_busRW = true;
Address_ZeroPage();
m_memory.ADDRESS() = m_memptr;
return m_memory.reference();
}
uint8_t& AM_ZeroPageIndirect() {
Address_ZeroPageIndirect();
m_memory.ADDRESS() = m_memptr;
return m_memory.reference();
}
uint8_t& AM_AbsoluteX(bool read = true) {
m_busRW = true;
Address_AbsoluteX();
m_memory.ADDRESS() = m_memptr;
if (read && (m_memory.ADDRESS().low == 0xff))
@ -172,6 +175,7 @@ namespace EightBit {
}
uint8_t& AM_AbsoluteY(bool read = true) {
m_busRW = true;
Address_AbsoluteY();
m_memory.ADDRESS() = m_memptr;
if (read && (m_memory.ADDRESS().low == 0xff))
@ -180,24 +184,28 @@ namespace EightBit {
}
uint8_t& AM_ZeroPageX() {
m_busRW = true;
Address_ZeroPageX();
m_memory.ADDRESS() = m_memptr;
return m_memory.reference();
}
uint8_t& AM_ZeroPageY() {
m_busRW = true;
Address_ZeroPageY();
m_memory.ADDRESS() = m_memptr;
return m_memory.reference();
}
uint8_t& AM_IndexedIndirectX() {
m_busRW = true;
Address_IndexedIndirectX();
m_memory.ADDRESS() = m_memptr;
return m_memory.reference();
}
uint8_t& AM_IndirectIndexedY(bool read = true) {
m_busRW = true;
Address_IndirectIndexedY();
m_memory.ADDRESS() = m_memptr;
if (read && (m_memory.ADDRESS().low == 0xff))
@ -260,7 +268,7 @@ namespace EightBit {
case 0b001:
return AM_ZeroPage();
case 0b010:
return A();
return AM_A();
case 0b011:
return AM_Absolute();
case 0b101:
@ -282,7 +290,7 @@ namespace EightBit {
case 0b001:
return AM_ZeroPage();
case 0b010:
return A();
return AM_A();
case 0b011:
return AM_Absolute();
case 0b101:
@ -364,5 +372,7 @@ namespace EightBit {
register16_t m_memptr;
std::array<int, 0x100> m_timings;
bool m_busRW;
};
}

48
M6502/src/mos6502.cpp

@ -130,6 +130,8 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
break;
default: // BIT
BIT(AM_00(bbb, false));
assert(m_busRW);
m_memory.read();
break;
}
break;
@ -187,7 +189,9 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
adjustNZ(A() = Y());
break;
default: // STY
AM_00(bbb, false) = Y();
AM_00(bbb, false);
assert(m_busRW);
m_memory.write(Y());
break;
}
break;
@ -204,6 +208,8 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
break;
default: // LDY
LDY(AM_00(bbb));
if (m_busRW)
m_memory.read();
break;
}
break;
@ -220,6 +226,8 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
break;
default: // CPY
CMP(Y(), AM_00(bbb));
if (m_busRW)
m_memory.read();
break;
}
break;
@ -236,6 +244,8 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
break;
default: // CPX
CMP(X(), AM_00(bbb));
if (m_busRW)
m_memory.read();
break;
}
break;
@ -245,27 +255,43 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
switch (aaa) {
case 0b000: // ORA
ORA(AM_01(bbb));
if (m_busRW)
m_memory.read();
break;
case 0b001: // AND
AND(AM_01(bbb));
if (m_busRW)
m_memory.read();
break;
case 0b010: // EOR
EOR(AM_01(bbb));
if (m_busRW)
m_memory.read();
break;
case 0b011: // ADC
ADC(AM_01(bbb));
if (m_busRW)
m_memory.read();
break;
case 0b100: // STA
AM_01(bbb, false) = A();
AM_01(bbb, false);
assert(m_busRW);
m_memory.write(A());
break;
case 0b101: // LDA
LDA(AM_01(bbb));
if (m_busRW)
m_memory.read();
break;
case 0b110: // CMP
CMP(A(), AM_01(bbb));
if (m_busRW)
m_memory.read();
break;
case 0b111: // SBC
SBC(AM_01(bbb));
if (m_busRW)
m_memory.read();
break;
default:
__assume(0);
@ -275,15 +301,23 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
switch (aaa) {
case 0b000: // ASL
ASL(AM_10(bbb, false));
if (m_busRW)
m_memory.read();
break;
case 0b001: // ROL
ROL(AM_10(bbb, false));
if (m_busRW)
m_memory.read();
break;
case 0b010: // LSR
LSR(AM_10(bbb, false));
if (m_busRW)
m_memory.read();
break;
case 0b011: // ROR
ROR(AM_10(bbb, false));
if (m_busRW)
m_memory.read();
break;
case 0b100:
switch (bbb) {
@ -294,7 +328,9 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
S() = X();
break;
default: // STX
AM_10_x(bbb, false) = X();
AM_10_x(bbb, false);
assert(m_busRW);
m_memory.write(X());
break;
}
break;
@ -305,6 +341,8 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
break;
default: // LDX
LDX(AM_10_x(bbb));
if (m_busRW)
m_memory.read();
break;
}
break;
@ -315,6 +353,8 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
break;
default: // DEC
DEC(AM_10(bbb, false));
if (m_busRW)
m_memory.read();
break;
}
break;
@ -324,6 +364,8 @@ int EightBit::MOS6502::Execute(uint8_t cell) {
break;
default: // INC
INC(AM_10(bbb, false));
if (m_busRW)
m_memory.read();
break;
}
break;