mirror of
https://github.com/MoleskiCoder/EightBit.git
synced 2024-12-21 18:29:57 +00:00
Use the virtual methods, busRead and busWrite for all processor bus actions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon
parent
ed47983928
commit
934a1f7025
@ -65,7 +65,7 @@ namespace EightBit {
|
||||
case 0b101:
|
||||
return L();
|
||||
case 0b110:
|
||||
return BUS().read(HL());
|
||||
return busRead(HL());
|
||||
case 0b111:
|
||||
return A();
|
||||
default:
|
||||
@ -94,7 +94,7 @@ namespace EightBit {
|
||||
L() = value;
|
||||
break;
|
||||
case 0b110:
|
||||
BUS().write(HL(), value);
|
||||
busWrite(HL(), value);
|
||||
break;
|
||||
case 0b111:
|
||||
A() = value;
|
||||
|
||||
@ -238,12 +238,12 @@ void EightBit::Intel8080::cmc() {
|
||||
}
|
||||
|
||||
void EightBit::Intel8080::xhtl() {
|
||||
MEMPTR().low = BUS().read(SP());
|
||||
BUS().write(L());
|
||||
MEMPTR().low = busRead(SP());
|
||||
busWrite(L());
|
||||
L() = MEMPTR().low;
|
||||
++BUS().ADDRESS();
|
||||
MEMPTR().high = BUS().read();
|
||||
BUS().write(H());
|
||||
MEMPTR().high = busRead();
|
||||
busWrite(H());
|
||||
H() = MEMPTR().high;
|
||||
}
|
||||
|
||||
@ -331,11 +331,11 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
|
||||
case 0:
|
||||
switch (p) {
|
||||
case 0: // LD (BC),A
|
||||
BUS().write(BC(), A());
|
||||
busWrite(BC(), A());
|
||||
tick(7);
|
||||
break;
|
||||
case 1: // LD (DE),A
|
||||
BUS().write(DE(), A());
|
||||
busWrite(DE(), A());
|
||||
tick(7);
|
||||
break;
|
||||
case 2: // LD (nn),HL
|
||||
@ -345,7 +345,7 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
|
||||
break;
|
||||
case 3: // LD (nn),A
|
||||
BUS().ADDRESS() = fetchWord();
|
||||
BUS().write(A());
|
||||
busWrite(A());
|
||||
tick(13);
|
||||
break;
|
||||
default:
|
||||
@ -355,11 +355,11 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
|
||||
case 1:
|
||||
switch (p) {
|
||||
case 0: // LD A,(BC)
|
||||
A() = BUS().read(BC());
|
||||
A() = busRead(BC());
|
||||
tick(7);
|
||||
break;
|
||||
case 1: // LD A,(DE)
|
||||
A() = BUS().read(DE());
|
||||
A() = busRead(DE());
|
||||
tick(7);
|
||||
break;
|
||||
case 2: // LD HL,(nn)
|
||||
@ -369,7 +369,7 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
|
||||
break;
|
||||
case 3: // LD A,(nn)
|
||||
BUS().ADDRESS() = fetchWord();
|
||||
A() = BUS().read();
|
||||
A() = busRead();
|
||||
tick(13);
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -74,7 +74,7 @@ namespace EightBit {
|
||||
case 5:
|
||||
return L();
|
||||
case 6:
|
||||
return BUS().read(HL());
|
||||
return busRead(HL());
|
||||
case 7:
|
||||
return A();
|
||||
default:
|
||||
@ -105,7 +105,7 @@ namespace EightBit {
|
||||
L() = value;
|
||||
break;
|
||||
case 6:
|
||||
BUS().write(HL(), value);
|
||||
busWrite(HL(), value);
|
||||
break;
|
||||
case 7:
|
||||
A() = value;
|
||||
|
||||
@ -325,7 +325,7 @@ int EightBit::GameBoy::LR35902::step() {
|
||||
handleRESET();
|
||||
} else if (UNLIKELY(lowered(INT()))) {
|
||||
handleINT();
|
||||
} else if (UNLIKELY(lowered(HALT()))) {
|
||||
} else if (UNLIKELY(halted())) {
|
||||
Processor::execute(0); // NOP
|
||||
} else {
|
||||
Processor::execute(fetchByte());
|
||||
@ -475,19 +475,19 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
case 0:
|
||||
switch (p) {
|
||||
case 0: // LD (BC),A
|
||||
BUS().write(BC(), A());
|
||||
busWrite(BC(), A());
|
||||
tick(2);
|
||||
break;
|
||||
case 1: // LD (DE),A
|
||||
BUS().write(DE(), A());
|
||||
busWrite(DE(), A());
|
||||
tick(2);
|
||||
break;
|
||||
case 2: // GB: LDI (HL),A
|
||||
BUS().write(HL()++, A());
|
||||
busWrite(HL()++, A());
|
||||
tick(2);
|
||||
break;
|
||||
case 3: // GB: LDD (HL),A
|
||||
BUS().write(HL()--, A());
|
||||
busWrite(HL()--, A());
|
||||
tick(2);
|
||||
break;
|
||||
default:
|
||||
@ -497,19 +497,19 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
case 1:
|
||||
switch (p) {
|
||||
case 0: // LD A,(BC)
|
||||
A() = BUS().read(BC());
|
||||
A() = busRead(BC());
|
||||
tick(2);
|
||||
break;
|
||||
case 1: // LD A,(DE)
|
||||
A() = BUS().read(DE());
|
||||
A() = busRead(DE());
|
||||
tick(2);
|
||||
break;
|
||||
case 2: // GB: LDI A,(HL)
|
||||
A() = BUS().read(HL()++);
|
||||
A() = busRead(HL()++);
|
||||
tick(2);
|
||||
break;
|
||||
case 3: // GB: LDD A,(HL)
|
||||
A() = BUS().read(HL()--);
|
||||
A() = busRead(HL()--);
|
||||
tick(2);
|
||||
break;
|
||||
default:
|
||||
@ -644,7 +644,7 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
tick(2);
|
||||
break;
|
||||
case 4: // GB: LD (FF00 + n),A
|
||||
BUS().write(IoRegisters::BASE + fetchByte(), A());
|
||||
busWrite(IoRegisters::BASE + fetchByte(), A());
|
||||
tick(3);
|
||||
break;
|
||||
case 5: { // GB: ADD SP,dd
|
||||
@ -660,7 +660,7 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
tick(4);
|
||||
break;
|
||||
case 6: // GB: LD A,(FF00 + n)
|
||||
A() = BUS().read(IoRegisters::BASE + fetchByte());
|
||||
A() = busRead(IoRegisters::BASE + fetchByte());
|
||||
tick(3);
|
||||
break;
|
||||
case 7: { // GB: LD HL,SP + dd
|
||||
@ -721,21 +721,21 @@ void EightBit::GameBoy::LR35902::executeOther(const int x, const int y, const in
|
||||
tick(3);
|
||||
break;
|
||||
case 4: // GB: LD (FF00 + C),A
|
||||
BUS().write(IoRegisters::BASE + C(), A());
|
||||
busWrite(IoRegisters::BASE + C(), A());
|
||||
tick(2);
|
||||
break;
|
||||
case 5: // GB: LD (nn),A
|
||||
BUS().ADDRESS() = MEMPTR() = fetchWord();
|
||||
BUS().write(A());
|
||||
busWrite(A());
|
||||
tick(4);
|
||||
break;
|
||||
case 6: // GB: LD A,(FF00 + C)
|
||||
A() = BUS().read(IoRegisters::BASE + C());
|
||||
A() = busRead(IoRegisters::BASE + C());
|
||||
tick(2);
|
||||
break;
|
||||
case 7: // GB: LD A,(nn)
|
||||
BUS().ADDRESS() = MEMPTR() = fetchWord();
|
||||
A() = BUS().read();
|
||||
A() = busRead();
|
||||
tick(4);
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -24,7 +24,7 @@ int EightBit::mc6809::step() {
|
||||
ExecutingInstruction.fire(*this);
|
||||
if (LIKELY(powered())) {
|
||||
m_prefix10 = m_prefix11 = false;
|
||||
if (UNLIKELY(lowered(HALT())))
|
||||
if (UNLIKELY(halted()))
|
||||
handleHALT();
|
||||
else if (UNLIKELY(lowered(RESET())))
|
||||
handleRESET();
|
||||
@ -165,18 +165,18 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
case 0x1c: tick(3); CC() &= AM_immediate_byte(); break; // AND (ANDCC immediate)
|
||||
|
||||
// ASL/LSL
|
||||
case 0x08: tick(6); BUS().write(asl(AM_direct_byte())); break; // ASL (direct)
|
||||
case 0x08: tick(6); busWrite(asl(AM_direct_byte())); break; // ASL (direct)
|
||||
case 0x48: tick(2); A() = asl(A()); break; // ASL (ASLA inherent)
|
||||
case 0x58: tick(2); B() = asl(B()); break; // ASL (ASLB inherent)
|
||||
case 0x68: tick(6); BUS().write(asl(AM_indexed_byte())); break; // ASL (indexed)
|
||||
case 0x78: tick(7); BUS().write(asl(AM_extended_byte())); break; // ASL (extended)
|
||||
case 0x68: tick(6); busWrite(asl(AM_indexed_byte())); break; // ASL (indexed)
|
||||
case 0x78: tick(7); busWrite(asl(AM_extended_byte())); break; // ASL (extended)
|
||||
|
||||
// ASR
|
||||
case 0x07: tick(6); BUS().write(asr(AM_direct_byte())); break; // ASR (direct)
|
||||
case 0x07: tick(6); busWrite(asr(AM_direct_byte())); break; // ASR (direct)
|
||||
case 0x47: tick(2); A() = asr(A()); break; // ASR (ASRA inherent)
|
||||
case 0x57: tick(2); B() = asr(B()); break; // ASR (ASRB inherent)
|
||||
case 0x67: tick(6); BUS().write(asr(AM_indexed_byte())); break; // ASR (indexed)
|
||||
case 0x77: tick(7); BUS().write(asr(AM_extended_byte())); break; // ASR (extended)
|
||||
case 0x67: tick(6); busWrite(asr(AM_indexed_byte())); break; // ASR (indexed)
|
||||
case 0x77: tick(7); busWrite(asr(AM_extended_byte())); break; // ASR (extended)
|
||||
|
||||
// BIT
|
||||
case 0x85: tick(2); bit(A(), AM_immediate_byte()); break; // BIT (BITA immediate)
|
||||
@ -190,11 +190,11 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
case 0xf5: tick(5); bit(B(), AM_extended_byte()); break; // BIT (BITB extended)
|
||||
|
||||
// CLR
|
||||
case 0x0f: tick(6); BUS().write(Address_direct(), clr()); break; // CLR (direct)
|
||||
case 0x0f: tick(6); busWrite(Address_direct(), clr()); break; // CLR (direct)
|
||||
case 0x4f: tick(2); A() = clr(); break; // CLR (CLRA implied)
|
||||
case 0x5f: tick(2); B() = clr(); break; // CLR (CLRB implied)
|
||||
case 0x6f: tick(6); BUS().write(Address_indexed(), clr()); break; // CLR (indexed)
|
||||
case 0x7f: tick(7); BUS().write(Address_extended(), clr()); break; // CLR (extended)
|
||||
case 0x6f: tick(6); busWrite(Address_indexed(), clr()); break; // CLR (indexed)
|
||||
case 0x7f: tick(7); busWrite(Address_extended(), clr()); break; // CLR (extended)
|
||||
|
||||
// CMP
|
||||
|
||||
@ -217,11 +217,11 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
case 0xbc: tick(7); cmp(X(), AM_extended_word()); break; // CMP (CMPX, extended)
|
||||
|
||||
// COM
|
||||
case 0x03: tick(6); BUS().write(com(AM_direct_byte())); break; // COM (direct)
|
||||
case 0x03: tick(6); busWrite(com(AM_direct_byte())); break; // COM (direct)
|
||||
case 0x43: tick(2); A() = com(A()); break; // COM (COMA inherent)
|
||||
case 0x53: tick(2); B() = com(B()); break; // COM (COMB inherent)
|
||||
case 0x63: tick(6); BUS().write(com(AM_indexed_byte())); break; // COM (indexed)
|
||||
case 0x73: tick(7); BUS().write(com(AM_extended_byte())); break; // COM (extended)
|
||||
case 0x63: tick(6); busWrite(com(AM_indexed_byte())); break; // COM (indexed)
|
||||
case 0x73: tick(7); busWrite(com(AM_extended_byte())); break; // COM (extended)
|
||||
|
||||
// CWAI
|
||||
case 0x3c: tick(11); cwai(AM_direct_byte()); break; // CWAI (direct)
|
||||
@ -230,11 +230,11 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
case 0x19: tick(2); A() = da(A()); break; // DAA (inherent)
|
||||
|
||||
// DEC
|
||||
case 0x0a: tick(6); BUS().write(dec(AM_direct_byte())); break; // DEC (direct)
|
||||
case 0x0a: tick(6); busWrite(dec(AM_direct_byte())); break; // DEC (direct)
|
||||
case 0x4a: tick(2); A() = dec(A()); break; // DEC (DECA inherent)
|
||||
case 0x5a: tick(2); B() = dec(B()); break; // DEC (DECB inherent)
|
||||
case 0x6a: tick(6); BUS().write(dec(AM_indexed_byte())); break; // DEC (indexed)
|
||||
case 0x7a: tick(7); BUS().write(dec(AM_extended_byte())); break; // DEC (extended)
|
||||
case 0x6a: tick(6); busWrite(dec(AM_indexed_byte())); break; // DEC (indexed)
|
||||
case 0x7a: tick(7); busWrite(dec(AM_extended_byte())); break; // DEC (extended)
|
||||
|
||||
// EOR
|
||||
|
||||
@ -254,11 +254,11 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
case 0x1e: tick(8); exg(AM_immediate_byte()); break; // EXG (R1,R2 immediate)
|
||||
|
||||
// INC
|
||||
case 0x0c: tick(6); BUS().write(inc(AM_direct_byte())); break; // INC (direct)
|
||||
case 0x0c: tick(6); busWrite(inc(AM_direct_byte())); break; // INC (direct)
|
||||
case 0x4c: tick(2); A() = inc(A()); break; // INC (INCA inherent)
|
||||
case 0x5c: tick(2); B() = inc(B()); break; // INC (INCB inherent)
|
||||
case 0x6c: tick(6); BUS().write(inc(AM_indexed_byte())); break; // INC (indexed)
|
||||
case 0x7c: tick(7); BUS().write(inc(AM_extended_byte())); break; // INC (extended)
|
||||
case 0x6c: tick(6); busWrite(inc(AM_indexed_byte())); break; // INC (indexed)
|
||||
case 0x7c: tick(7); busWrite(inc(AM_extended_byte())); break; // INC (extended)
|
||||
|
||||
// JMP
|
||||
case 0x0e: tick(6); jump(Address_direct()); break; // JMP (direct)
|
||||
@ -309,21 +309,21 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
case 0x33: tick(4); U() = Address_indexed(); break; // LEA (LEAU indexed)
|
||||
|
||||
// LSR
|
||||
case 0x04: tick(6); BUS().write(lsr(AM_direct_byte())); break; // LSR (direct)
|
||||
case 0x04: tick(6); busWrite(lsr(AM_direct_byte())); break; // LSR (direct)
|
||||
case 0x44: tick(2); A() = lsr(A()); break; // LSR (LSRA inherent)
|
||||
case 0x54: tick(2); B() = lsr(B()); break; // LSR (LSRB inherent)
|
||||
case 0x64: tick(6); BUS().write(lsr(AM_indexed_byte())); break; // LSR (indexed)
|
||||
case 0x74: tick(7); BUS().write(lsr(AM_extended_byte())); break; // LSR (extended)
|
||||
case 0x64: tick(6); busWrite(lsr(AM_indexed_byte())); break; // LSR (indexed)
|
||||
case 0x74: tick(7); busWrite(lsr(AM_extended_byte())); break; // LSR (extended)
|
||||
|
||||
// MUL
|
||||
case 0x3d: tick(11); D() = mul(A(), B()); break; // MUL (inherent)
|
||||
|
||||
// NEG
|
||||
case 0x00: tick(6); BUS().write(neg(AM_direct_byte())); break; // NEG (direct)
|
||||
case 0x00: tick(6); busWrite(neg(AM_direct_byte())); break; // NEG (direct)
|
||||
case 0x40: tick(2); A() = neg(A()); break; // NEG (NEGA, inherent)
|
||||
case 0x50: tick(2); B() = neg(B()); break; // NEG (NEGB, inherent)
|
||||
case 0x60: tick(6); BUS().write(neg(AM_indexed_byte())); break; // NEG (indexed)
|
||||
case 0x70: tick(7); BUS().write(neg(AM_extended_byte())); break; // NEG (extended)
|
||||
case 0x60: tick(6); busWrite(neg(AM_indexed_byte())); break; // NEG (indexed)
|
||||
case 0x70: tick(7); busWrite(neg(AM_extended_byte())); break; // NEG (extended)
|
||||
|
||||
// NOP
|
||||
case 0x12: tick(2); break; // NOP (inherent)
|
||||
@ -354,18 +354,18 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
case 0x37: tick(5); pul(U(), AM_immediate_byte()); break; // PUL (PULU immediate)
|
||||
|
||||
// ROL
|
||||
case 0x09: tick(6); BUS().write(rol(AM_direct_byte())); break; // ROL (direct)
|
||||
case 0x09: tick(6); busWrite(rol(AM_direct_byte())); break; // ROL (direct)
|
||||
case 0x49: tick(2); A() = rol(A()); break; // ROL (ROLA inherent)
|
||||
case 0x59: tick(2); B() = rol(B()); break; // ROL (ROLB inherent)
|
||||
case 0x69: tick(6); BUS().write(rol(AM_indexed_byte())); break; // ROL (indexed)
|
||||
case 0x79: tick(7); BUS().write(rol(AM_extended_byte())); break; // ROL (extended)
|
||||
case 0x69: tick(6); busWrite(rol(AM_indexed_byte())); break; // ROL (indexed)
|
||||
case 0x79: tick(7); busWrite(rol(AM_extended_byte())); break; // ROL (extended)
|
||||
|
||||
// ROR
|
||||
case 0x06: tick(6); BUS().write(ror(AM_direct_byte())); break; // ROR (direct)
|
||||
case 0x06: tick(6); busWrite(ror(AM_direct_byte())); break; // ROR (direct)
|
||||
case 0x46: tick(2); A() = ror(A()); break; // ROR (RORA inherent)
|
||||
case 0x56: tick(2); B() = ror(B()); break; // ROR (RORB inherent)
|
||||
case 0x66: tick(6); BUS().write(ror(AM_indexed_byte())); break; // ROR (indexed)
|
||||
case 0x76: tick(7); BUS().write(ror(AM_extended_byte())); break; // ROR (extended)
|
||||
case 0x66: tick(6); busWrite(ror(AM_indexed_byte())); break; // ROR (indexed)
|
||||
case 0x76: tick(7); busWrite(ror(AM_extended_byte())); break; // ROR (extended)
|
||||
|
||||
// RTI
|
||||
case 0x3B: tick(6); rti(); break; // RTI (inherent)
|
||||
@ -393,14 +393,14 @@ void EightBit::mc6809::executeUnprefixed() {
|
||||
// ST
|
||||
|
||||
// STA
|
||||
case 0x97: tick(4); BUS().write(Address_direct(), st(A())); break; // ST (STA direct)
|
||||
case 0xa7: tick(4); BUS().write(Address_indexed(), st(A())); break; // ST (STA indexed)
|
||||
case 0xb7: tick(5); BUS().write(Address_extended(), st(A())); break; // ST (STA extended)
|
||||
case 0x97: tick(4); busWrite(Address_direct(), st(A())); break; // ST (STA direct)
|
||||
case 0xa7: tick(4); busWrite(Address_indexed(), st(A())); break; // ST (STA indexed)
|
||||
case 0xb7: tick(5); busWrite(Address_extended(), st(A())); break; // ST (STA extended)
|
||||
|
||||
// STB
|
||||
case 0xd7: tick(4); BUS().write(Address_direct(), st(B())); break; // ST (STB direct)
|
||||
case 0xe7: tick(4); BUS().write(Address_indexed(), st(B())); break; // ST (STB indexed)
|
||||
case 0xf7: tick(5); BUS().write(Address_extended(), st(B())); break; // ST (STB extended)
|
||||
case 0xd7: tick(4); busWrite(Address_direct(), st(B())); break; // ST (STB direct)
|
||||
case 0xe7: tick(4); busWrite(Address_indexed(), st(B())); break; // ST (STB indexed)
|
||||
case 0xf7: tick(5); busWrite(Address_extended(), st(B())); break; // ST (STB extended)
|
||||
|
||||
// STD
|
||||
case 0xdd: tick(5); Processor::setWord(Address_direct(), st(D())); break; // ST (STD direct)
|
||||
@ -592,11 +592,11 @@ uint8_t EightBit::mc6809::pop() {
|
||||
}
|
||||
|
||||
void EightBit::mc6809::push(register16_t& stack, const uint8_t value) {
|
||||
BUS().write(--stack, value);
|
||||
busWrite(--stack, value);
|
||||
}
|
||||
|
||||
uint8_t EightBit::mc6809::pop(register16_t& stack) {
|
||||
return BUS().read(stack++);
|
||||
return busRead(stack++);
|
||||
}
|
||||
|
||||
//
|
||||
@ -720,15 +720,15 @@ uint8_t EightBit::mc6809::AM_immediate_byte() {
|
||||
}
|
||||
|
||||
uint8_t EightBit::mc6809::AM_direct_byte() {
|
||||
return BUS().read(Address_direct());
|
||||
return busRead(Address_direct());
|
||||
}
|
||||
|
||||
uint8_t EightBit::mc6809::AM_indexed_byte() {
|
||||
return BUS().read(Address_indexed());
|
||||
return busRead(Address_indexed());
|
||||
}
|
||||
|
||||
uint8_t EightBit::mc6809::AM_extended_byte() {
|
||||
return BUS().read(Address_extended());
|
||||
return busRead(Address_extended());
|
||||
}
|
||||
|
||||
//
|
||||
|
||||
@ -191,7 +191,7 @@ namespace EightBit {
|
||||
case 5:
|
||||
return HL2().low;
|
||||
case 6:
|
||||
return BUS().read(UNLIKELY(m_displaced) ? displacedAddress() : HL().word);
|
||||
return busRead(UNLIKELY(m_displaced) ? displacedAddress() : HL().word);
|
||||
case 7:
|
||||
return A();
|
||||
default:
|
||||
@ -222,7 +222,7 @@ namespace EightBit {
|
||||
HL2().low = value;
|
||||
break;
|
||||
case 6:
|
||||
BUS().write(UNLIKELY(m_displaced) ? displacedAddress() : HL().word, value);
|
||||
busWrite(UNLIKELY(m_displaced) ? displacedAddress() : HL().word, value);
|
||||
break;
|
||||
case 7:
|
||||
A() = value;
|
||||
@ -232,31 +232,6 @@ namespace EightBit {
|
||||
}
|
||||
}
|
||||
|
||||
[[nodiscard]] auto R2(const int r) {
|
||||
ASSUME(r >= 0);
|
||||
ASSUME(r <= 7);
|
||||
switch (r) {
|
||||
case 0:
|
||||
return B();
|
||||
case 1:
|
||||
return C();
|
||||
case 2:
|
||||
return D();
|
||||
case 3:
|
||||
return E();
|
||||
case 4:
|
||||
return H();
|
||||
case 5:
|
||||
return L();
|
||||
case 6:
|
||||
return BUS().read(HL());
|
||||
case 7:
|
||||
return A();
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
}
|
||||
|
||||
void R2(const int r, const uint8_t value) {
|
||||
ASSUME(r >= 0);
|
||||
ASSUME(r <= 7);
|
||||
@ -280,7 +255,7 @@ namespace EightBit {
|
||||
L() = value;
|
||||
break;
|
||||
case 6:
|
||||
BUS().write(HL(), value);
|
||||
busWrite(HL(), value);
|
||||
break;
|
||||
case 7:
|
||||
A() = value;
|
||||
|
||||
@ -488,18 +488,18 @@ void EightBit::Z80::ccf() {
|
||||
}
|
||||
|
||||
void EightBit::Z80::xhtl() {
|
||||
MEMPTR().low = BUS().read(SP());
|
||||
BUS().write(HL2().low);
|
||||
MEMPTR().low = busRead(SP());
|
||||
busWrite(HL2().low);
|
||||
HL2().low = MEMPTR().low;
|
||||
++BUS().ADDRESS();
|
||||
MEMPTR().high = BUS().read();
|
||||
BUS().write(HL2().high);
|
||||
MEMPTR().high = busRead();
|
||||
busWrite(HL2().high);
|
||||
HL2().high = MEMPTR().high;
|
||||
}
|
||||
|
||||
void EightBit::Z80::blockCompare(const register16_t source, register16_t& counter) {
|
||||
|
||||
const auto value = BUS().read(source);
|
||||
const auto value = busRead(source);
|
||||
uint8_t result = A() - value;
|
||||
|
||||
setFlag(F(), PF, --counter.word);
|
||||
@ -535,8 +535,8 @@ bool EightBit::Z80::cpdr() {
|
||||
}
|
||||
|
||||
void EightBit::Z80::blockLoad(const register16_t source, const register16_t destination, register16_t& counter) {
|
||||
const auto value = BUS().read(source);
|
||||
BUS().write(destination, value);
|
||||
const auto value = busRead(source);
|
||||
busWrite(destination, value);
|
||||
const auto xy = A() + value;
|
||||
setFlag(F(), XF, xy & Bit3);
|
||||
setFlag(F(), YF, xy & Bit1);
|
||||
@ -565,7 +565,7 @@ bool EightBit::Z80::lddr() {
|
||||
void EightBit::Z80::blockIn(register16_t& source, const register16_t destination) {
|
||||
MEMPTR() = BUS().ADDRESS() = source;
|
||||
const auto value = readPort();
|
||||
BUS().write(destination, value);
|
||||
busWrite(destination, value);
|
||||
source.high = decrement(source.high);
|
||||
setFlag(F(), NF);
|
||||
}
|
||||
@ -591,7 +591,7 @@ bool EightBit::Z80::indr() {
|
||||
}
|
||||
|
||||
void EightBit::Z80::blockOut(const register16_t source, register16_t& destination) {
|
||||
const auto value = BUS().read(source);
|
||||
const auto value = busRead(source);
|
||||
BUS().ADDRESS() = destination;
|
||||
writePort();
|
||||
destination.high = decrement(destination.high);
|
||||
@ -623,8 +623,8 @@ bool EightBit::Z80::otdr() {
|
||||
|
||||
void EightBit::Z80::rrd() {
|
||||
(MEMPTR() = BUS().ADDRESS() = HL())++;
|
||||
const auto memory = BUS().read();
|
||||
BUS().write(promoteNibble(A()) | highNibble(memory));
|
||||
const auto memory = busRead();
|
||||
busWrite(promoteNibble(A()) | highNibble(memory));
|
||||
A() = higherNibble(A()) | lowerNibble(memory);
|
||||
adjustSZPXY<Z80>(F(), A());
|
||||
clearFlag(F(), NF | HC);
|
||||
@ -632,8 +632,8 @@ void EightBit::Z80::rrd() {
|
||||
|
||||
void EightBit::Z80::rld() {
|
||||
(MEMPTR() = BUS().ADDRESS() = HL())++;
|
||||
const auto memory = BUS().read();
|
||||
BUS().write(promoteNibble(memory) | lowNibble(A()));
|
||||
const auto memory = busRead();
|
||||
busWrite(promoteNibble(memory) | lowNibble(A()));
|
||||
A() = higherNibble(A()) | highNibble(memory);
|
||||
adjustSZPXY<Z80>(F(), A());
|
||||
clearFlag(F(), NF | HC);
|
||||
@ -672,7 +672,7 @@ int EightBit::Z80::step() {
|
||||
handleNMI();
|
||||
} else if (UNLIKELY(lowered(INT()))) {
|
||||
handleINT();
|
||||
} else if (UNLIKELY(lowered(HALT()))) {
|
||||
} else if (UNLIKELY(halted())) {
|
||||
IntelProcessor::execute(0); // NOP
|
||||
} else {
|
||||
IntelProcessor::execute(fetchByte());
|
||||
@ -727,7 +727,7 @@ void EightBit::Z80::executeCB(const int x, const int y, const int z) {
|
||||
const bool memoryZ = z == 6;
|
||||
const bool indirect = (!m_displaced && memoryZ) || m_displaced;
|
||||
const bool direct = !indirect;
|
||||
auto operand = LIKELY(!m_displaced) ? R(z) : BUS().read(displacedAddress());
|
||||
auto operand = LIKELY(!m_displaced) ? R(z) : busRead(displacedAddress());
|
||||
const bool update = x != 1; // BIT does not update
|
||||
switch (x) {
|
||||
case 0: { // rot[y] r[z]
|
||||
@ -789,7 +789,7 @@ void EightBit::Z80::executeCB(const int x, const int y, const int z) {
|
||||
if (UNLIKELY(memoryZ))
|
||||
tick(7);
|
||||
} else {
|
||||
BUS().write(operand);
|
||||
busWrite(operand);
|
||||
R2(z, operand);
|
||||
tick(15);
|
||||
}
|
||||
@ -1108,13 +1108,13 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
||||
case 0: // LD (BC),A
|
||||
(MEMPTR() = BUS().ADDRESS() = BC())++;
|
||||
MEMPTR().high = BUS().DATA() = A();
|
||||
BUS().write();
|
||||
busWrite();
|
||||
tick(7);
|
||||
break;
|
||||
case 1: // LD (DE),A
|
||||
(MEMPTR() = BUS().ADDRESS() = DE())++;
|
||||
MEMPTR().high = BUS().DATA() = A();
|
||||
BUS().write();
|
||||
busWrite();
|
||||
tick(7);
|
||||
break;
|
||||
case 2: // LD (nn),HL
|
||||
@ -1125,7 +1125,7 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
||||
case 3: // LD (nn),A
|
||||
(MEMPTR() = BUS().ADDRESS() = fetchWord())++;
|
||||
MEMPTR().high = BUS().DATA() = A();
|
||||
BUS().write();
|
||||
busWrite();
|
||||
tick(13);
|
||||
break;
|
||||
default:
|
||||
@ -1136,12 +1136,12 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
||||
switch (p) {
|
||||
case 0: // LD A,(BC)
|
||||
(MEMPTR() = BUS().ADDRESS() = BC())++;
|
||||
A() = BUS().read();
|
||||
A() = busRead();
|
||||
tick(7);
|
||||
break;
|
||||
case 1: // LD A,(DE)
|
||||
(MEMPTR() = BUS().ADDRESS() = DE())++;
|
||||
A() = BUS().read();
|
||||
A() = busRead();
|
||||
tick(7);
|
||||
break;
|
||||
case 2: // LD HL,(nn)
|
||||
@ -1151,7 +1151,7 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
||||
break;
|
||||
case 3: // LD A,(nn)
|
||||
(MEMPTR() = BUS().ADDRESS() = fetchWord())++;
|
||||
A() = BUS().read();
|
||||
A() = busRead();
|
||||
tick(13);
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -109,15 +109,15 @@ namespace EightBit {
|
||||
}
|
||||
|
||||
[[nodiscard]] static auto calculateHalfCarryAdd(const uint8_t before, const uint8_t value, const int calculation) noexcept {
|
||||
static std::array<bool, 8> m_halfCarryTableAdd = { { false, false, true, false, true, false, true, true } };
|
||||
static std::array<int, 8> halfCarryTableAdd = { { 0, 0, 1, 0, 1, 0, 1, 1} };
|
||||
const auto index = buildHalfCarryIndex(before, value, calculation);
|
||||
return m_halfCarryTableAdd[index & Mask3];
|
||||
return halfCarryTableAdd[index & Mask3];
|
||||
}
|
||||
|
||||
[[nodiscard]] static auto calculateHalfCarrySub(const uint8_t before, const uint8_t value, const int calculation) noexcept {
|
||||
std::array<bool, 8> m_halfCarryTableSub = { { false, true, true, true, false, false, false, true } };
|
||||
std::array<int, 8> halfCarryTableSub = { { 0, 1, 1, 1, 0, 0, 0, 1 } };
|
||||
const auto index = buildHalfCarryIndex(before, value, calculation);
|
||||
return m_halfCarryTableSub[index & Mask3];
|
||||
return halfCarryTableSub[index & Mask3];
|
||||
}
|
||||
|
||||
void handleRESET() override;
|
||||
|
||||
@ -21,11 +21,11 @@ void EightBit::IntelProcessor::handleRESET() {
|
||||
}
|
||||
|
||||
void EightBit::IntelProcessor::push(const uint8_t value) {
|
||||
BUS().write(--SP(), value);
|
||||
busWrite(--SP(), value);
|
||||
}
|
||||
|
||||
uint8_t EightBit::IntelProcessor::pop() {
|
||||
return BUS().read(SP()++);
|
||||
return busRead(SP()++);
|
||||
}
|
||||
|
||||
EightBit::register16_t EightBit::IntelProcessor::getWord() {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user