More addressing clarifications
This commit is contained in:
Adrian Conlon
parent
2ef9437ded
commit
a81dec6c6e
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@ -105,29 +105,29 @@ namespace EightBit {
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// Addressing modes
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[[nodiscard]] auto Address_Immediate() noexcept { return PC()++; }
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[[nodiscard]] auto Address_Absolute() noexcept { return fetchWord(); }
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[[nodiscard]] auto Address_ZeroPage() noexcept { return register16_t(fetchByte(), 0); }
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[[nodiscard]] register16_t Address_ZeroPageIndirect() noexcept;
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[[nodiscard]] register16_t Address_Indirect() noexcept;
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[[nodiscard]] register16_t Address_ZeroPageX() noexcept;
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[[nodiscard]] register16_t Address_ZeroPageY() noexcept;
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[[nodiscard]] register16_t Address_AbsoluteX() noexcept;
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[[nodiscard]] register16_t Address_AbsoluteY() noexcept;
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[[nodiscard]] register16_t Address_IndexedIndirectX() noexcept;
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[[nodiscard]] register16_t Address_IndirectIndexedY() noexcept;
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void Address_Immediate() noexcept { BUS().ADDRESS() = PC()++; }
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void Address_Absolute() noexcept { BUS().ADDRESS() = fetchWord(); }
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void Address_ZeroPage() noexcept { BUS().ADDRESS() = register16_t(fetchByte(), 0); }
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void Address_ZeroPageIndirect() noexcept;
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void Address_Indirect() noexcept;
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void Address_ZeroPageX() noexcept;
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void Address_ZeroPageY() noexcept;
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void Address_AbsoluteX() noexcept;
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void Address_AbsoluteY() noexcept;
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void Address_IndexedIndirectX() noexcept;
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void Address_IndirectIndexedY() noexcept;
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// Addressing modes, read
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void AM_Immediate() noexcept { BUS().ADDRESS() = Address_Immediate(); memoryRead(); }
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void AM_Absolute() noexcept { BUS().ADDRESS() = Address_Absolute(); memoryRead(); }
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void AM_ZeroPage() noexcept { BUS().ADDRESS() = Address_ZeroPage(); memoryRead(); }
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void AM_ZeroPageX() noexcept { BUS().ADDRESS() = Address_ZeroPageX(); memoryRead(); }
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void AM_ZeroPageY() noexcept { BUS().ADDRESS() = Address_ZeroPageY(); memoryRead(); }
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void AM_IndexedIndirectX() noexcept { BUS().ADDRESS() = Address_IndexedIndirectX(); memoryRead(); }
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void AM_AbsoluteX() noexcept { BUS().ADDRESS() = Address_AbsoluteX(); maybe_fixup(BUS().ADDRESS()); memoryRead(); }
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void AM_AbsoluteY() noexcept { BUS().ADDRESS() = Address_AbsoluteY(); maybe_fixup(BUS().ADDRESS()); memoryRead(); }
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void AM_IndirectIndexedY() noexcept { BUS().ADDRESS() = Address_IndirectIndexedY(); maybe_fixup(BUS().ADDRESS()); memoryRead(); }
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void AM_Immediate() noexcept { Address_Immediate(); memoryRead(); }
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void AM_Absolute() noexcept { Address_Absolute(); memoryRead(); }
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void AM_ZeroPage() noexcept { Address_ZeroPage(); memoryRead(); }
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void AM_ZeroPageX() noexcept { Address_ZeroPageX(); memoryRead(); }
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void AM_ZeroPageY() noexcept { Address_ZeroPageY(); memoryRead(); }
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void AM_IndexedIndirectX() noexcept { Address_IndexedIndirectX(); memoryRead(); }
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void AM_AbsoluteX() noexcept { Address_AbsoluteX(); maybe_fixup(); memoryRead(); }
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void AM_AbsoluteY() noexcept { Address_AbsoluteY(); maybe_fixup(); memoryRead(); }
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void AM_IndirectIndexedY() noexcept { Address_IndirectIndexedY(); maybe_fixup(); memoryRead(); }
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// Flag checking
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@ -173,19 +173,13 @@ namespace EightBit {
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return data;
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}
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#define FIXUP_RMW(ADDRESSING, OPERATION) \
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#define FIXUP_RMW(OPERATION) \
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{ \
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fixup(ADDRESSING()); \
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_RMW(OPERATION); \
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fixup(); \
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RMW(OPERATION); \
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}
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#define RMW(ADDRESSING, OPERATION) \
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{ \
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BUS().ADDRESS() = ADDRESSING(); \
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_RMW(OPERATION); \
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}
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#define _RMW(OPERATION) \
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#define RMW(OPERATION) \
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{ \
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const auto data = memoryRead(); \
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const auto result = OPERATION(data); \
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@ -193,18 +187,20 @@ namespace EightBit {
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memoryWrite(result); \
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}
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void maybe_fixup(register16_t address) noexcept {
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BUS().ADDRESS() = { address.low, m_unfixed_page };
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if (m_unfixed_page != address.high) {
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void maybe_fixup() noexcept {
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const auto fixed = BUS().ADDRESS();
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BUS().ADDRESS() = { fixed.low, m_unfixed_page };
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if (m_unfixed_page != fixed.high) {
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memoryRead();
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BUS().ADDRESS().high = address.high;
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BUS().ADDRESS().high = fixed.high;
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}
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}
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void fixup(register16_t address) noexcept {
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BUS().ADDRESS() = { address.low, m_unfixed_page };
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void fixup() noexcept {
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const auto fixed = BUS().ADDRESS();
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BUS().ADDRESS() = { fixed.low, m_unfixed_page };
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memoryRead();
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BUS().ADDRESS().high = address.high;
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BUS().ADDRESS().high = fixed.high;
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}
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// Status flag operations
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@ -133,44 +133,44 @@ void EightBit::MOS6502::execute() noexcept {
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case 0x00: swallow_fetch(); interrupt(); break; // BRK (implied)
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case 0x01: AM_IndexedIndirectX(); orr(); break; // ORA (indexed indirect X)
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case 0x02: jam(); break; // *JAM
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case 0x03: RMW(Address_IndexedIndirectX, asl); orr(); break; // *SLO (indexed indirect X)
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case 0x03: Address_IndexedIndirectX(); RMW(asl); orr(); break; // *SLO (indexed indirect X)
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case 0x04: AM_ZeroPage(); break; // *NOP (zero page)
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case 0x05: AM_ZeroPage(); orr(); break; // ORA (zero page)
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case 0x06: RMW(Address_ZeroPage, asl); break; // ASL (zero page)
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case 0x07: RMW(Address_ZeroPage, asl); orr(); break; // *SLO (zero page)
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case 0x06: Address_ZeroPage(); RMW(asl); break; // ASL (zero page)
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case 0x07: Address_ZeroPage(); RMW(asl); orr(); break; // *SLO (zero page)
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case 0x08: swallow(); php(); break; // PHP (implied)
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case 0x09: AM_Immediate(); orr(); break; // ORA (immediate)
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case 0x0a: swallow(); A() = asl(A()); break; // ASL A (implied)
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case 0x0b: AM_Immediate(); anc(); break; // *ANC (immediate)
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case 0x0c: { auto ignored = Address_Absolute(); } break; // *NOP (absolute)
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case 0x0c: Address_Absolute(); break; // *NOP (absolute)
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case 0x0d: AM_Absolute(); orr(); break; // ORA (absolute)
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case 0x0e: RMW(Address_Absolute, asl); break; // ASL (absolute)
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case 0x0e: Address_Absolute(); RMW(asl); break; // ASL (absolute)
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case 0x0f: Processor::execute(0x0e); orr(); break; // *SLO (absolute)
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case 0x10: branch(negative() == 0); break; // BPL (relative)
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case 0x11: AM_IndirectIndexedY(); orr(); break; // ORA (indirect indexed Y)
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case 0x12: jam(); break; // *JAM
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case 0x13: FIXUP_RMW(Address_IndirectIndexedY, asl); orr(); break; // *SLO (indirect indexed Y)
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case 0x13: Address_IndirectIndexedY(); FIXUP_RMW(asl); orr(); break; // *SLO (indirect indexed Y)
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case 0x14: AM_ZeroPageX(); break; // *NOP (zero page, X)
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case 0x15: AM_ZeroPageX(); orr(); break; // ORA (zero page, X)
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case 0x16: RMW(Address_ZeroPageX, asl); break; // ASL (zero page, X)
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case 0x16: Address_ZeroPageX(); RMW(asl); break; // ASL (zero page, X)
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case 0x17: Processor::execute(0x16); orr(); break; // *SLO (zero page, X)
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case 0x18: swallow(); reset_flag(CF); break; // CLC (implied)
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case 0x19: AM_AbsoluteY(); orr(); break; // ORA (absolute, Y)
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case 0x1a: swallow(); break; // *NOP (implied)
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case 0x1b: FIXUP_RMW(Address_AbsoluteY, asl); orr(); break; // *SLO (absolute, Y)
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case 0x1c: BUS().ADDRESS() = Address_AbsoluteX(); fixup(BUS().ADDRESS()); break; // *NOP (absolute, X)
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case 0x1b: Address_AbsoluteY(); FIXUP_RMW(asl); orr(); break; // *SLO (absolute, Y)
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case 0x1c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
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case 0x1d: AM_AbsoluteX(); orr(); break; // ORA (absolute, X)
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case 0x1e: FIXUP_RMW(Address_AbsoluteX, asl); break; // ASL (absolute, X)
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case 0x1e: Address_AbsoluteX(); FIXUP_RMW(asl); break; // ASL (absolute, X)
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case 0x1f: Processor::execute(0x1e); orr(); break; // *SLO (absolute, X)
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case 0x20: jsr(); break; // JSR (absolute)
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case 0x21: AM_IndexedIndirectX(); andr(); break; // AND (indexed indirect X)
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case 0x22: jam(); break; // *JAM
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case 0x23: RMW(Address_IndexedIndirectX, rol); andr(); break; // *RLA (indexed indirect X)
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case 0x23: Address_IndexedIndirectX(); RMW(rol); andr(); break; // *RLA (indexed indirect X)
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case 0x24: AM_ZeroPage(); bit(A()); break; // BIT (zero page)
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case 0x25: AM_ZeroPage(); andr(); break; // AND (zero page)
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case 0x26: RMW(Address_ZeroPage, rol); break; // ROL (zero page)
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case 0x26: Address_ZeroPage(); RMW(rol); break; // ROL (zero page)
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case 0x27: Processor::execute(0x26); andr(); break; // *RLA (zero page)
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case 0x28: swallow(); plp(); break; // PLP (implied)
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case 0x29: AM_Immediate(); andr(); break; // AND (immediate)
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@ -178,126 +178,126 @@ void EightBit::MOS6502::execute() noexcept {
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case 0x2b: AM_Immediate(); anc(); break; // *ANC (immediate)
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case 0x2c: AM_Absolute(); bit(A()); break; // BIT (absolute)
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case 0x2d: AM_Absolute(); andr(); break; // AND (absolute)
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case 0x2e: RMW(Address_Absolute, rol); break; // ROL (absolute)
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case 0x2e: Address_Absolute(); RMW(rol); break; // ROL (absolute)
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case 0x2f: Processor::execute(0x2e); andr(); break; // *RLA (absolute)
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case 0x30: branch(negative()); break; // BMI (relative)
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case 0x31: AM_IndirectIndexedY(); andr(); break; // AND (indirect indexed Y)
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case 0x32: jam(); break; // *JAM
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case 0x33: FIXUP_RMW(Address_IndirectIndexedY, rol); andr(); break; // *RLA (indirect indexed Y)
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case 0x33: Address_IndirectIndexedY(); FIXUP_RMW(rol); andr(); break; // *RLA (indirect indexed Y)
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case 0x34: AM_ZeroPageX(); break; // *NOP (zero page, X)
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case 0x35: AM_ZeroPageX(); andr(); break; // AND (zero page, X)
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case 0x36: RMW(Address_ZeroPageX, rol); break; // ROL (zero page, X)
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case 0x36: Address_ZeroPageX(); RMW(rol); break; // ROL (zero page, X)
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case 0x37: Processor::execute(0x36); andr(); break; // *RLA (zero page, X)
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case 0x38: swallow(); set_flag(CF); break; // SEC (implied)
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case 0x39: AM_AbsoluteY(); andr(); break; // AND (absolute, Y)
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case 0x3a: swallow(); break; // *NOP (implied)
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case 0x3b: FIXUP_RMW(Address_AbsoluteY, rol); andr(); break; // *RLA (absolute, Y)
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case 0x3c: BUS().ADDRESS() = Address_AbsoluteX(); fixup(BUS().ADDRESS()); break; // *NOP (absolute, X)
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case 0x3b: Address_AbsoluteY(); FIXUP_RMW(rol); andr(); break; // *RLA (absolute, Y)
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case 0x3c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
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case 0x3d: AM_AbsoluteX(); andr(); break; // AND (absolute, X)
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case 0x3e: FIXUP_RMW(Address_AbsoluteX, rol); break; // ROL (absolute, X)
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case 0x3e: Address_AbsoluteX(); FIXUP_RMW(rol); break; // ROL (absolute, X)
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case 0x3f: Processor::execute(0x3e); andr(); break; // *RLA (absolute, X)
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case 0x40: swallow(); rti(); break; // RTI (implied)
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case 0x41: AM_IndexedIndirectX(); eorr(); break; // EOR (indexed indirect X)
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case 0x42: jam(); break; // *JAM
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case 0x43: RMW(Address_IndexedIndirectX, lsr); eorr(); break; // *SRE (indexed indirect X)
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case 0x43: Address_IndexedIndirectX(); RMW(lsr); eorr(); break; // *SRE (indexed indirect X)
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case 0x44: AM_ZeroPage(); break; // *NOP (zero page)
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case 0x45: AM_ZeroPage(); eorr(); break; // EOR (zero page)
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case 0x46: RMW(Address_ZeroPage, lsr); break; // LSR (zero page)
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case 0x46: Address_ZeroPage(); RMW(lsr); break; // LSR (zero page)
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case 0x47: Processor::execute(0x46); eorr(); break; // *SRE (zero page)
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case 0x48: swallow(); push(A()); break; // PHA (implied)
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case 0x49: AM_Immediate(); eorr(); break; // EOR (immediate)
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case 0x4a: swallow(); A() = lsr(A()); break; // LSR A (implied)
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case 0x4b: AM_Immediate(); andr(); A() = lsr(A()); break; // *ASR (immediate)
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case 0x4c: jump(Address_Absolute()); break; // JMP (absolute)
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case 0x4c: Address_Absolute(); jump(BUS().ADDRESS()); break; // JMP (absolute)
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case 0x4d: AM_Absolute(); eorr(); break; // EOR (absolute)
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case 0x4e: RMW(Address_Absolute, lsr); break; // LSR (absolute)
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case 0x4e: Address_Absolute(); RMW(lsr); break; // LSR (absolute)
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case 0x4f: Processor::execute(0x4e); eorr(); break; // *SRE (absolute)
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case 0x50: branch(overflow() == 0); break; // BVC (relative)
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case 0x51: AM_IndirectIndexedY(); eorr(); break; // EOR (indirect indexed Y)
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case 0x52: jam(); break; // *JAM
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case 0x53: FIXUP_RMW(Address_IndirectIndexedY, lsr); eorr(); break; // *SRE (indirect indexed Y)
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case 0x53: Address_IndirectIndexedY(); FIXUP_RMW(lsr); eorr(); break; // *SRE (indirect indexed Y)
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case 0x54: AM_ZeroPageX(); break; // *NOP (zero page, X)
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case 0x55: AM_ZeroPageX(); eorr(); break; // EOR (zero page, X)
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case 0x56: RMW(Address_ZeroPageX, lsr); break; // LSR (zero page, X)
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case 0x56: Address_ZeroPageX(); RMW(lsr); break; // LSR (zero page, X)
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case 0x57: Processor::execute(0x56); eorr(); break; // *SRE (zero page, X)
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case 0x58: swallow(); reset_flag(IF); break; // CLI (implied)
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case 0x59: AM_AbsoluteY(); eorr(); break; // EOR (absolute, Y)
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case 0x5a: swallow(); break; // *NOP (implied)
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case 0x5b: FIXUP_RMW(Address_AbsoluteY, lsr); eorr(); break; // *SRE (absolute, Y)
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case 0x5c: BUS().ADDRESS()= Address_AbsoluteX(); fixup(BUS().ADDRESS()); break; // *NOP (absolute, X)
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case 0x5b: Address_AbsoluteY(); FIXUP_RMW(lsr); eorr(); break; // *SRE (absolute, Y)
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case 0x5c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
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case 0x5d: AM_AbsoluteX(); eorr(); break; // EOR (absolute, X)
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case 0x5e: FIXUP_RMW(Address_AbsoluteX, lsr); break; // LSR (absolute, X)
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case 0x5e: Address_AbsoluteX(); FIXUP_RMW(lsr); break; // LSR (absolute, X)
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case 0x5f: Processor::execute(0x5e); eorr(); break; // *SRE (absolute, X)
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case 0x60: swallow(); rts(); break; // RTS (implied)
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case 0x61: AM_IndexedIndirectX(); adc(); break; // ADC (indexed indirect X)
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case 0x62: jam(); break; // *JAM
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case 0x63: RMW(Address_IndexedIndirectX, ror); adc(); break; // *RRA (indexed indirect X)
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case 0x63: Address_IndexedIndirectX(); RMW(ror); adc(); break; // *RRA (indexed indirect X)
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case 0x64: AM_ZeroPage(); break; // *NOP (zero page)
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case 0x65: AM_ZeroPage(); adc(); break; // ADC (zero page)
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case 0x66: RMW(Address_ZeroPage, ror); break; // ROR (zero page)
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case 0x66: Address_ZeroPage(); RMW(ror); break; // ROR (zero page)
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case 0x67: Processor::execute(0x66); adc(); break; // *RRA (zero page)
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case 0x68: swallow(); swallow_stack(); A() = through(pop()); break; // PLA (implied)
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case 0x69: AM_Immediate(); adc(); break; // ADC (immediate)
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case 0x6a: swallow(); A() = ror(A()); break; // ROR A (implied)
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case 0x6b: AM_Immediate(); arr(); break; // *ARR (immediate)
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case 0x6c: jump(Address_Indirect()); break; // JMP (indirect)
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case 0x6c: Address_Indirect(); jump(BUS().ADDRESS()); break; // JMP (indirect)
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case 0x6d: AM_Absolute(); adc(); break; // ADC (absolute)
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case 0x6e: RMW(Address_Absolute, ror); break; // ROR (absolute)
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case 0x6e: Address_Absolute(); RMW(ror); break; // ROR (absolute)
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case 0x6f: Processor::execute(0x6e); adc(); break; // *RRA (absolute)
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case 0x70: branch(overflow()); break; // BVS (relative)
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case 0x71: AM_IndirectIndexedY(); adc(); break; // ADC (indirect indexed Y)
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case 0x72: jam(); break; // *JAM
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case 0x73: FIXUP_RMW(Address_IndirectIndexedY, ror); adc(); break; // *RRA (indirect indexed Y)
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case 0x73: Address_IndirectIndexedY(); FIXUP_RMW(ror); adc(); break; // *RRA (indirect indexed Y)
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case 0x74: AM_ZeroPageX(); break; // *NOP (zero page, X)
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case 0x75: AM_ZeroPageX(); adc(); break; // ADC (zero page, X)
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case 0x76: RMW(Address_ZeroPageX, ror); break; // ROR (zero page, X)
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case 0x76: Address_ZeroPageX(); RMW(ror); break; // ROR (zero page, X)
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case 0x77: Processor::execute(0x76); adc(); break; // *RRA (zero page, X)
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case 0x78: swallow(); set_flag(IF); break; // SEI (implied)
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case 0x79: AM_AbsoluteY(); adc(); break; // ADC (absolute, Y)
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case 0x7a: swallow(); break; // *NOP (implied)
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case 0x7b: FIXUP_RMW(Address_AbsoluteY, ror); adc(); break; // *RRA (absolute, Y)
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case 0x7c: BUS().ADDRESS() = Address_AbsoluteX(); fixup(BUS().ADDRESS()); break; // *NOP (absolute, X)
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case 0x7b: Address_AbsoluteY(); FIXUP_RMW(ror); adc(); break; // *RRA (absolute, Y)
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case 0x7c: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
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case 0x7d: AM_AbsoluteX(); adc(); break; // ADC (absolute, X)
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case 0x7e: FIXUP_RMW(Address_AbsoluteX, ror); break; // ROR (absolute, X)
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case 0x7e: Address_AbsoluteX(); FIXUP_RMW(ror); break; // ROR (absolute, X)
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case 0x7f: Processor::execute(0x7e); adc(); break; // *RRA (absolute, X)
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case 0x80: AM_Immediate(); break; // *NOP (immediate)
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case 0x81: BUS().ADDRESS() = Address_IndexedIndirectX(); memoryWrite(A()); break; // STA (indexed indirect X)
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case 0x81: Address_IndexedIndirectX(); memoryWrite(A()); break; // STA (indexed indirect X)
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case 0x82: AM_Immediate(); break; // *NOP (immediate)
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case 0x83: BUS().ADDRESS() = Address_IndexedIndirectX(); memoryWrite(A() & X()); break; // *SAX (indexed indirect X)
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case 0x84: BUS().ADDRESS() = Address_ZeroPage(); memoryWrite(Y()); break; // STY (zero page)
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case 0x85: BUS().ADDRESS() = Address_ZeroPage(); memoryWrite(A()); break; // STA (zero page)
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case 0x86: BUS().ADDRESS() = Address_ZeroPage(); memoryWrite(X()); break; // STX (zero page)
|
||||
case 0x87: BUS().ADDRESS() = Address_ZeroPage(); memoryWrite(A() & X()); break; // *SAX (zero page)
|
||||
case 0x83: Address_IndexedIndirectX(); memoryWrite(A() & X()); break; // *SAX (indexed indirect X)
|
||||
case 0x84: Address_ZeroPage(); memoryWrite(Y()); break; // STY (zero page)
|
||||
case 0x85: Address_ZeroPage(); memoryWrite(A()); break; // STA (zero page)
|
||||
case 0x86: Address_ZeroPage(); memoryWrite(X()); break; // STX (zero page)
|
||||
case 0x87: Address_ZeroPage(); memoryWrite(A() & X()); break; // *SAX (zero page)
|
||||
case 0x88: swallow(); Y() = dec(Y()); break; // DEY (implied)
|
||||
case 0x89: AM_Immediate(); break; // *NOP (immediate)
|
||||
case 0x8a: swallow(); A() = through(X()); break; // TXA (implied)
|
||||
case 0x8b: AM_Immediate(); A() = through((A() | 0xee) & X() & BUS().DATA());
|
||||
break; // *ANE (immediate)
|
||||
case 0x8c: BUS().ADDRESS() = Address_Absolute(); memoryWrite(Y()); break; // STY (absolute)
|
||||
case 0x8d: BUS().ADDRESS() = Address_Absolute(); memoryWrite(A()); break; // STA (absolute)
|
||||
case 0x8e: BUS().ADDRESS() = Address_Absolute(); memoryWrite(X()); break; // STX (absolute)
|
||||
case 0x8f: BUS().ADDRESS() = Address_Absolute(); memoryWrite(A() & X()); break; // *SAX (absolute)
|
||||
case 0x8c: Address_Absolute(); memoryWrite(Y()); break; // STY (absolute)
|
||||
case 0x8d: Address_Absolute(); memoryWrite(A()); break; // STA (absolute)
|
||||
case 0x8e: Address_Absolute(); memoryWrite(X()); break; // STX (absolute)
|
||||
case 0x8f: Address_Absolute(); memoryWrite(A() & X()); break; // *SAX (absolute)
|
||||
|
||||
case 0x90: branch(carry() == 0); break; // BCC (relative)
|
||||
case 0x91: BUS().ADDRESS() = Address_IndirectIndexedY(); fixup(BUS().ADDRESS()); memoryWrite(A()); break; // STA (indirect indexed Y)
|
||||
case 0x91: Address_IndirectIndexedY(); fixup(); memoryWrite(A()); break; // STA (indirect indexed Y)
|
||||
case 0x92: jam(); break; // *JAM
|
||||
case 0x93: sha_IndirectIndexedY(); break; // *SHA (indirect indexed, Y)
|
||||
case 0x94: BUS().ADDRESS() = Address_ZeroPageX(); memoryWrite(Y()); break; // STY (zero page, X)
|
||||
case 0x95: BUS().ADDRESS() = Address_ZeroPageX(); memoryWrite(A()); break; // STA (zero page, X)
|
||||
case 0x96: BUS().ADDRESS() = Address_ZeroPageY(); memoryWrite(X()); break; // STX (zero page, Y)
|
||||
case 0x97: BUS().ADDRESS() = Address_ZeroPageY(); memoryWrite(A() & X()); break; // *SAX (zero page, Y)
|
||||
case 0x94: Address_ZeroPageX(); memoryWrite(Y()); break; // STY (zero page, X)
|
||||
case 0x95: Address_ZeroPageX(); memoryWrite(A()); break; // STA (zero page, X)
|
||||
case 0x96: Address_ZeroPageY(); memoryWrite(X()); break; // STX (zero page, Y)
|
||||
case 0x97: Address_ZeroPageY(); memoryWrite(A() & X()); break; // *SAX (zero page, Y)
|
||||
case 0x98: swallow(); A() = through(Y()); break; // TYA (implied)
|
||||
case 0x99: BUS().ADDRESS() = Address_AbsoluteY(); fixup(BUS().ADDRESS()); memoryWrite(A()); break; // STA (absolute, Y)
|
||||
case 0x99: Address_AbsoluteY(); fixup(); memoryWrite(A()); break; // STA (absolute, Y)
|
||||
case 0x9a: swallow(); S() = X(); break; // TXS (implied)
|
||||
case 0x9b: tas_AbsoluteY(); break; // *TAS (absolute, Y)
|
||||
case 0x9c: sya_AbsoluteX(); break; // *SYA (absolute, X)
|
||||
case 0x9d: BUS().ADDRESS() = Address_AbsoluteX(); fixup(BUS().ADDRESS()); memoryWrite(A()); break; // STA (absolute, X)
|
||||
case 0x9d: Address_AbsoluteX(); fixup(); memoryWrite(A()); break; // STA (absolute, X)
|
||||
case 0x9e: sxa_AbsoluteY(); break; // *SXA (absolute, Y)
|
||||
case 0x9f: sha_AbsoluteY(); break; // *SHA (absolute, Y)
|
||||
|
||||
|
|
@ -339,10 +339,10 @@ void EightBit::MOS6502::execute() noexcept {
|
|||
case 0xc0: AM_Immediate(); cmp(Y()); break; // CPY (immediate)
|
||||
case 0xc1: AM_IndexedIndirectX(); cmp(A()); break; // CMP (indexed indirect X)
|
||||
case 0xc2: AM_Immediate(); break; // *NOP (immediate)
|
||||
case 0xc3: RMW(Address_IndexedIndirectX, dec); cmp(A()); break; // *DCP (indexed indirect X)
|
||||
case 0xc3: Address_IndexedIndirectX(); RMW(dec); cmp(A()); break; // *DCP (indexed indirect X)
|
||||
case 0xc4: AM_ZeroPage(); cmp(Y()); break; // CPY (zero page)
|
||||
case 0xc5: AM_ZeroPage(); cmp(A()); break; // CMP (zero page)
|
||||
case 0xc6: RMW(Address_ZeroPage, dec); break; // DEC (zero page)
|
||||
case 0xc6: Address_ZeroPage(); RMW(dec); break; // DEC (zero page)
|
||||
case 0xc7: Processor::execute(0xc6); cmp(A()); break; // *DCP (zero page)
|
||||
case 0xc8: swallow(); Y() = inc(Y()); break; // INY (implied)
|
||||
case 0xc9: AM_Immediate(); cmp(A()); break; // CMP (immediate)
|
||||
|
|
@ -350,33 +350,33 @@ void EightBit::MOS6502::execute() noexcept {
|
|||
case 0xcb: AM_Immediate(); axs(); break; // *AXS (immediate)
|
||||
case 0xcc: AM_Absolute(); cmp(Y()); break; // CPY (absolute)
|
||||
case 0xcd: AM_Absolute(); cmp(A()); break; // CMP (absolute)
|
||||
case 0xce: RMW(Address_Absolute, dec); break; // DEC (absolute)
|
||||
case 0xce: Address_Absolute(); RMW(dec); break; // DEC (absolute)
|
||||
case 0xcf: Processor::execute(0xce); cmp(A()); break; // *DCP (absolute)
|
||||
|
||||
case 0xd0: branch(zero() == 0); break; // BNE (relative)
|
||||
case 0xd1: AM_IndirectIndexedY(); cmp(A()); break; // CMP (indirect indexed Y)
|
||||
case 0xd2: jam(); break; // *JAM
|
||||
case 0xd3: FIXUP_RMW(Address_IndirectIndexedY, dec); cmp(A()); break; // *DCP (indirect indexed Y)
|
||||
case 0xd3: Address_IndirectIndexedY(); FIXUP_RMW(dec); cmp(A()); break; // *DCP (indirect indexed Y)
|
||||
case 0xd4: AM_ZeroPageX(); break; // *NOP (zero page, X)
|
||||
case 0xd5: AM_ZeroPageX(); cmp(A()); break; // CMP (zero page, X)
|
||||
case 0xd6: RMW(Address_ZeroPageX, dec); break; // DEC (zero page, X)
|
||||
case 0xd6: Address_ZeroPageX(); RMW(dec); break; // DEC (zero page, X)
|
||||
case 0xd7: Processor::execute(0xd6); cmp(A()); break; // *DCP (zero page, X)
|
||||
case 0xd8: swallow(); reset_flag(DF); break; // CLD (implied)
|
||||
case 0xd9: AM_AbsoluteY(); cmp(A()); break; // CMP (absolute, Y)
|
||||
case 0xda: swallow(); break; // *NOP (implied)
|
||||
case 0xdb: FIXUP_RMW(Address_AbsoluteY, dec); cmp(A()); break; // *DCP (absolute, Y)
|
||||
case 0xdc: BUS().ADDRESS() = Address_AbsoluteX(); fixup(BUS().ADDRESS()); break; // *NOP (absolute, X)
|
||||
case 0xdb: Address_AbsoluteY(); FIXUP_RMW(dec); cmp(A()); break; // *DCP (absolute, Y)
|
||||
case 0xdc: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
|
||||
case 0xdd: AM_AbsoluteX(); cmp(A()); break; // CMP (absolute, X)
|
||||
case 0xde: FIXUP_RMW(Address_AbsoluteX, dec); break; // DEC (absolute, X)
|
||||
case 0xde: Address_AbsoluteX(); FIXUP_RMW(dec); break; // DEC (absolute, X)
|
||||
case 0xdf: Processor::execute(0xde); cmp(A()); break; // *DCP (absolute, X)
|
||||
|
||||
case 0xe0: AM_Immediate(); cmp(X()); break; // CPX (immediate)
|
||||
case 0xe1: AM_IndexedIndirectX(); sbc(); break; // SBC (indexed indirect X)
|
||||
case 0xe2: AM_Immediate(); break; // *NOP (immediate)
|
||||
case 0xe3: RMW(Address_IndexedIndirectX, inc); sbc(); break; // *ISB (indexed indirect X)
|
||||
case 0xe3: Address_IndexedIndirectX(); RMW(inc); sbc(); break; // *ISB (indexed indirect X)
|
||||
case 0xe4: AM_ZeroPage(); cmp(X()); break; // CPX (zero page)
|
||||
case 0xe5: AM_ZeroPage(); sbc(); break; // SBC (zero page)
|
||||
case 0xe6: RMW(Address_ZeroPage, inc); break; // INC (zero page)
|
||||
case 0xe6: Address_ZeroPage(); RMW(inc); break; // INC (zero page)
|
||||
case 0xe7: Processor::execute(0xe6); sbc(); break; // *ISB (zero page)
|
||||
case 0xe8: swallow(); X() = inc(X()); break; // INX (implied)
|
||||
case 0xe9: AM_Immediate(); sbc(); break; // SBC (immediate)
|
||||
|
|
@ -384,24 +384,24 @@ void EightBit::MOS6502::execute() noexcept {
|
|||
case 0xeb: AM_Immediate(); sbc(); break; // *SBC (immediate)
|
||||
case 0xec: AM_Absolute(); cmp(X()); break; // CPX (absolute)
|
||||
case 0xed: AM_Absolute(); sbc(); break; // SBC (absolute)
|
||||
case 0xee: RMW(Address_Absolute, inc); break; // INC (absolute)
|
||||
case 0xee: Address_Absolute(); RMW(inc); break; // INC (absolute)
|
||||
case 0xef: Processor::execute(0xee); sbc(); break; // *ISB (absolute)
|
||||
|
||||
case 0xf0: branch(zero()); break; // BEQ (relative)
|
||||
case 0xf1: AM_IndirectIndexedY(); sbc(); break; // SBC (indirect indexed Y)
|
||||
case 0xf2: jam(); break; // *JAM
|
||||
case 0xf3: FIXUP_RMW(Address_IndirectIndexedY, inc); sbc(); break; // *ISB (indirect indexed Y)
|
||||
case 0xf3: Address_IndirectIndexedY(); FIXUP_RMW(inc); sbc(); break; // *ISB (indirect indexed Y)
|
||||
case 0xf4: AM_ZeroPageX(); break; // *NOP (zero page, X)
|
||||
case 0xf5: AM_ZeroPageX(); sbc(); break; // SBC (zero page, X)
|
||||
case 0xf6: RMW(Address_ZeroPageX, inc); break; // INC (zero page, X)
|
||||
case 0xf6: Address_ZeroPageX(); RMW(inc); break; // INC (zero page, X)
|
||||
case 0xf7: Processor::execute(0xf6); sbc(); break; // *ISB (zero page, X)
|
||||
case 0xf8: swallow(); set_flag(DF); break; // SED (implied)
|
||||
case 0xf9: AM_AbsoluteY(); sbc(); break; // SBC (absolute, Y)
|
||||
case 0xfa: swallow(); break; // *NOP (implied)
|
||||
case 0xfb: FIXUP_RMW(Address_AbsoluteY, inc); sbc(); break; // *ISB (absolute, Y)
|
||||
case 0xfc: BUS().ADDRESS() = Address_AbsoluteX(); fixup(BUS().ADDRESS()); break; // *NOP (absolute, X)
|
||||
case 0xfb: Address_AbsoluteY(); FIXUP_RMW(inc); sbc(); break; // *ISB (absolute, Y)
|
||||
case 0xfc: Address_AbsoluteX(); fixup(); break; // *NOP (absolute, X)
|
||||
case 0xfd: AM_AbsoluteX(); sbc(); break; // SBC (absolute, X)
|
||||
case 0xfe: FIXUP_RMW(Address_AbsoluteX, inc); break; // INC (absolute, X)
|
||||
case 0xfe: Address_AbsoluteX(); FIXUP_RMW(inc); break; // INC (absolute, X)
|
||||
case 0xff: Processor::execute(0xfe); sbc(); break; // *ISB (absolute, X)
|
||||
}
|
||||
}
|
||||
|
|
@ -425,44 +425,49 @@ void EightBit::MOS6502::dummyPush(uint8_t value) noexcept {
|
|||
|
||||
////
|
||||
|
||||
EightBit::register16_t EightBit::MOS6502::Address_ZeroPageIndirect() noexcept {
|
||||
return Processor::getWordPaged(Address_ZeroPage());
|
||||
void EightBit::MOS6502::Address_ZeroPageIndirect() noexcept {
|
||||
Address_ZeroPage();
|
||||
BUS().ADDRESS() = getWordPaged();
|
||||
}
|
||||
|
||||
EightBit::register16_t EightBit::MOS6502::Address_Indirect() noexcept {
|
||||
return Processor::getWordPaged(Address_Absolute());
|
||||
void EightBit::MOS6502::Address_Indirect() noexcept {
|
||||
Address_Absolute();
|
||||
BUS().ADDRESS() = getWordPaged();
|
||||
}
|
||||
|
||||
EightBit::register16_t EightBit::MOS6502::Address_ZeroPageX() noexcept {
|
||||
void EightBit::MOS6502::Address_ZeroPageX() noexcept {
|
||||
AM_ZeroPage();
|
||||
return register16_t(BUS().ADDRESS().low + X(), 0);
|
||||
assert(BUS().ADDRESS().high == 0);
|
||||
BUS().ADDRESS().low += X();
|
||||
}
|
||||
|
||||
EightBit::register16_t EightBit::MOS6502::Address_ZeroPageY() noexcept {
|
||||
void EightBit::MOS6502::Address_ZeroPageY() noexcept {
|
||||
AM_ZeroPage();
|
||||
return register16_t(BUS().ADDRESS().low + Y(), 0);
|
||||
assert(BUS().ADDRESS().high == 0);
|
||||
BUS().ADDRESS().low += Y();
|
||||
}
|
||||
|
||||
EightBit::register16_t EightBit::MOS6502::Address_AbsoluteX() noexcept {
|
||||
const auto address = Address_Absolute();
|
||||
m_unfixed_page = address.high;
|
||||
return address + X();
|
||||
void EightBit::MOS6502::Address_AbsoluteX() noexcept {
|
||||
Address_Absolute();
|
||||
m_unfixed_page = BUS().ADDRESS().high;
|
||||
BUS().ADDRESS() += X();
|
||||
}
|
||||
|
||||
EightBit::register16_t EightBit::MOS6502::Address_AbsoluteY() noexcept {
|
||||
const auto address = Address_Absolute();
|
||||
m_unfixed_page = address.high;
|
||||
return address + Y();
|
||||
void EightBit::MOS6502::Address_AbsoluteY() noexcept {
|
||||
Address_Absolute();
|
||||
m_unfixed_page = BUS().ADDRESS().high;
|
||||
BUS().ADDRESS() += Y();
|
||||
}
|
||||
|
||||
EightBit::register16_t EightBit::MOS6502::Address_IndexedIndirectX() noexcept {
|
||||
return Processor::getWordPaged(Address_ZeroPageX());
|
||||
void EightBit::MOS6502::Address_IndexedIndirectX() noexcept {
|
||||
Address_ZeroPageX();
|
||||
BUS().ADDRESS() = getWordPaged();
|
||||
}
|
||||
|
||||
EightBit::register16_t EightBit::MOS6502::Address_IndirectIndexedY() noexcept {
|
||||
const auto address = Address_ZeroPageIndirect();
|
||||
m_unfixed_page = address.high;
|
||||
return address + Y();
|
||||
void EightBit::MOS6502::Address_IndirectIndexedY() noexcept {
|
||||
Address_ZeroPageIndirect();
|
||||
m_unfixed_page = BUS().ADDRESS().high;
|
||||
BUS().ADDRESS() += Y();
|
||||
}
|
||||
|
||||
////
|
||||
|
|
@ -474,7 +479,7 @@ void EightBit::MOS6502::branch(const int condition) noexcept {
|
|||
m_unfixed_page = PC().high;
|
||||
jump(PC() + relative);
|
||||
BUS().ADDRESS() = PC();
|
||||
maybe_fixup(BUS().ADDRESS());
|
||||
maybe_fixup();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -674,17 +679,20 @@ void EightBit::MOS6502::jam() noexcept {
|
|||
//
|
||||
|
||||
void EightBit::MOS6502::sha_AbsoluteY() noexcept {
|
||||
fixup(Address_AbsoluteY());
|
||||
Address_AbsoluteY();
|
||||
fixup();
|
||||
memoryWrite(A() & X() & (BUS().ADDRESS().high + 1));
|
||||
}
|
||||
|
||||
void EightBit::MOS6502::sha_IndirectIndexedY() noexcept {
|
||||
fixup(Address_IndirectIndexedY());
|
||||
Address_IndirectIndexedY();
|
||||
fixup();
|
||||
memoryWrite(A() & X() & (BUS().ADDRESS().high + 1));
|
||||
}
|
||||
|
||||
void EightBit::MOS6502::sya_AbsoluteX() noexcept {
|
||||
fixup(Address_AbsoluteX());
|
||||
Address_AbsoluteX();
|
||||
fixup();
|
||||
memoryWrite(Y() & (BUS().ADDRESS().high + 1));
|
||||
}
|
||||
|
||||
|
|
@ -694,13 +702,13 @@ void EightBit::MOS6502::tas_AbsoluteY() noexcept {
|
|||
}
|
||||
|
||||
void EightBit::MOS6502::las_AbsoluteY() noexcept {
|
||||
BUS().ADDRESS() = Address_AbsoluteY();
|
||||
maybe_fixup(BUS().ADDRESS());
|
||||
Address_AbsoluteY();
|
||||
maybe_fixup();
|
||||
A() = X() = S() = through(memoryRead() & S());
|
||||
}
|
||||
|
||||
void EightBit::MOS6502::sxa_AbsoluteY() noexcept {
|
||||
BUS().ADDRESS() = Address_AbsoluteY();
|
||||
fixup(BUS().ADDRESS());
|
||||
Address_AbsoluteY();
|
||||
fixup();
|
||||
memoryWrite(X() & (BUS().ADDRESS().high + 1));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue