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Some more small clarifications of shared processor implementation.

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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
This commit is contained in:
Adrian.Conlon 2017-07-25 18:56:43 +01:00
parent ff21263b97
commit b6dd48ca63
11 changed files with 63 additions and 59 deletions
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10
Intel8080/inc/Intel8080.h
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@ -8,8 +8,6 @@
namespace EightBit {
class Intel8080 : public IntelProcessor {
public:
typedef std::function<void()> instruction_t;
enum StatusBits {
SF = Bit7,
ZF = Bit6,
@ -29,6 +27,8 @@ namespace EightBit {
int step();
virtual register16_t& AF() override {
auto& f = af.low;
f = (f | Bit1) & ~(Bit5 | Bit3);
return af;
}
@ -117,10 +117,6 @@ namespace EightBit {
}
}
void adjustReservedFlags() {
F() = (F() | Bit1) & ~(Bit5 | Bit3);
}
static void adjustAuxiliaryCarryAdd(uint8_t& f, uint8_t before, uint8_t value, int calculation) {
setFlag(f, AC, calculateHalfCarryAdd(before, value, calculation));
}
@ -131,7 +127,7 @@ namespace EightBit {
static void subtract(uint8_t& f, uint8_t& operand, uint8_t value, int carry = 0);
int execute(uint8_t opcode);
virtual int execute(uint8_t opcode);
void execute(int x, int y, int z, int p, int q);
static void increment(uint8_t& f, uint8_t& operand);

4
Intel8080/src/Intel8080.cpp
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@ -14,7 +14,6 @@ EightBit::Intel8080::Intel8080(Memory& memory, InputOutput& ports)
void EightBit::Intel8080::initialise() {
IntelProcessor::initialise();
AF().word = BC().word = DE().word = HL().word = 0;
adjustReservedFlags();
}
#pragma region Interrupt routines
@ -345,7 +344,7 @@ void EightBit::Intel8080::execute(int x, int y, int z, int p, int q) {
case 1: // 16-bit load immediate/add
switch (q) {
case 0: // LD rp,nn
fetchWord(RP(p));
Processor::fetchWord(RP(p));
cycles += 10;
break;
case 1: // ADD HL,rp
@ -532,7 +531,6 @@ void EightBit::Intel8080::execute(int x, int y, int z, int p, int q) {
switch (q) {
case 0: // POP rp2[p]
popWord(RP2(p));
adjustReservedFlags();
cycles += 10;
break;
case 1:

3
Intel8080/test/test.cpp
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@ -8,9 +8,10 @@ int main(int, char*[]) {
Configuration configuration;
#ifdef _DEBUG
configuration.setDebugMode(true);
//configuration.setDebugMode(true);
configuration.setProfileMode(true);
#endif
//configuration.setDebugMode(true);
EightBit::TestHarness<Configuration, Board> harness(configuration);
harness.initialise();

56
LR35902/inc/LR35902.h
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@ -31,44 +31,42 @@ namespace EightBit {
int interrupt(uint8_t value);
int execute(uint8_t opcode);
virtual int execute(uint8_t opcode);
int step();
// Mutable access to processor!!
virtual register16_t& AF() override {
m_accumulatorFlag.low &= 0xf0;
return m_accumulatorFlag;
af.low &= 0xf0;
return af;
}
virtual register16_t& BC() override {
return m_registers[BC_IDX];
return bc;
}
virtual register16_t& DE() override {
return m_registers[DE_IDX];
return de;
}
virtual register16_t& HL() override {
return m_registers[HL_IDX];
return hl;
}
virtual void reset();
virtual void initialise();
protected:
virtual uint8_t fetchByte() {
virtual uint8_t fetchByte() override {
auto returned = IntelProcessor::fetchByte();
m_memory.fireReadBusEvent();
return returned;
}
virtual void push(uint8_t value) {
virtual void push(uint8_t value) override {
IntelProcessor::push(value);
m_memory.fireWriteBusEvent();
}
virtual uint8_t pop() {
virtual uint8_t pop() override {
auto returned = IntelProcessor::pop();
m_memory.fireReadBusEvent();
return returned;
@ -91,12 +89,12 @@ namespace EightBit {
}
private:
enum { BC_IDX, DE_IDX, HL_IDX };
Bus& m_bus;
std::array<register16_t, 3> m_registers;
register16_t m_accumulatorFlag;
register16_t af;
register16_t bc;
register16_t de;
register16_t hl;
bool m_ime;
@ -104,10 +102,6 @@ namespace EightBit {
bool m_stopped;
int fetchExecute() {
return execute(fetchByte());
}
uint8_t& R(int r, uint8_t& a) {
switch (r) {
case 0:
@ -132,20 +126,36 @@ namespace EightBit {
}
register16_t& RP(int rp) {
__assume(rp < 4);
__assume(rp >= 0);
switch (rp) {
case 3:
case 0b00:
return BC();
case 0b01:
return DE();
case 0b10:
return HL();
case 0b11:
return SP();
default:
return m_registers[rp];
__assume(0);
}
}
register16_t& RP2(int rp) {
__assume(rp < 4);
__assume(rp >= 0);
switch (rp) {
case 3:
case 0b00:
return BC();
case 0b01:
return DE();
case 0b10:
return HL();
case 0b11:
return AF();
default:
return m_registers[rp];
__assume(0);
}
}

2
LR35902/src/LR35902.cpp
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@ -500,7 +500,7 @@ void EightBit::LR35902::executeOther(int x, int y, int z, int p, int q) {
case 1: // 16-bit load immediate/add
switch (q) {
case 0: // LD rp,nn
fetchWord(RP(p));
Processor::fetchWord(RP(p));
cycles += 3;
break;
case 1: // ADD HL,rp

5
M6502/inc/mos6502.h
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@ -78,7 +78,7 @@ namespace EightBit {
protected:
virtual void interrupt(uint16_t vector);
virtual int execute(uint8_t cell);
virtual int execute(uint8_t opcode);
private:
register16_t& MEMPTR() { return m_memptr; }
@ -96,8 +96,7 @@ namespace EightBit {
void pushWord(register16_t value);
void popWord(register16_t& output);
uint8_t fetchByte();
void fetchWord(register16_t& output);
virtual uint8_t fetchByte() override;
#pragma region 6502 addressing modes

6
M6502/src/mos6502.cpp
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@ -385,12 +385,6 @@ uint8_t EightBit::MOS6502::fetchByte() {
return getByte();
}
void EightBit::MOS6502::fetchWord(register16_t& output) {
m_memory.ADDRESS().word = PC().word++;
getWord(output);
PC().word++;
}
////
void EightBit::MOS6502::ROR(uint8_t& output) {

6
Z80/inc/Z80.h
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@ -54,7 +54,7 @@ namespace EightBit {
int interrupt(bool maskable, uint8_t value);
int execute(uint8_t opcode);
virtual int execute(uint8_t opcode);
int step();
virtual register16_t& AF() override {
@ -131,9 +131,9 @@ namespace EightBit {
int8_t m_displacement;
bool m_displaced;
int fetchExecute() {
virtual int fetchExecute() override{
M1() = true;
return execute(fetchByte());
return IntelProcessor::fetchExecute();
}
uint8_t& DISPLACED() {

2
Z80/src/Z80.cpp
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@ -1152,7 +1152,7 @@ void EightBit::Z80::executeOther(int x, int y, int z, int p, int q) {
case 1: // 16-bit load immediate/add
switch (q) {
case 0: // LD rp,nn
fetchWord(RP(p));
Processor::fetchWord(RP(p));
cycles += 10;
break;
case 1: // ADD HL,rp

12
inc/IntelProcessor.h
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@ -119,16 +119,6 @@ namespace EightBit {
return m_halfCarryTableSub[index & Mask3];
}
virtual uint8_t fetchByte() {
m_memory.ADDRESS().word = PC().word++;
return m_memory.reference();
}
void fetchWord(register16_t& output) {
output.low = fetchByte();
output.high = fetchByte();
}
virtual void push(uint8_t value) {
m_memory.ADDRESS().word = --SP().word;
m_memory.reference() = value;
@ -150,7 +140,7 @@ namespace EightBit {
}
void fetchWord() {
fetchWord(MEMPTR());
Processor::fetchWord(MEMPTR());
}
//

16
inc/Processor.h
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@ -55,6 +55,8 @@ namespace EightBit {
void reset();
virtual int execute(uint8_t opcode) = 0;
protected:
static void clearFlag(uint8_t& f, int flag) { f &= ~flag; }
static void setFlag(uint8_t& f, int flag) { f |= flag; }
@ -72,6 +74,20 @@ namespace EightBit {
Memory& m_memory;
int cycles;
virtual uint8_t fetchByte() {
m_memory.ADDRESS().word = PC().word++;
return m_memory.reference();
}
virtual void fetchWord(register16_t& output) {
output.low = fetchByte();
output.high = fetchByte();
}
virtual int fetchExecute() {
return execute(fetchByte());
}
private:
register16_t pc;
bool m_halted;