mirror of
https://github.com/MoleskiCoder/EightBit.git
synced 2024-06-26 04:29:26 +00:00
Start refactoring CPU cores to use C++17/14 features. (This commit covers the 6502 and Z80)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon
parent
62f3cd717b
commit
fac2da9ac4
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@ -63,10 +63,10 @@ namespace EightBit {
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void interrupt(uint8_t vector);
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void adjustZero(uint8_t datum) { clearFlag(P(), ZF, datum); }
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void adjustNegative(uint8_t datum) { setFlag(P(), NF, datum & NF); }
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void adjustZero(const uint8_t datum) { clearFlag(P(), ZF, datum); }
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void adjustNegative(const uint8_t datum) { setFlag(P(), NF, datum & NF); }
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void adjustNZ(uint8_t datum) {
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void adjustNZ(const uint8_t datum) {
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adjustZero(datum);
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adjustNegative(datum);
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}
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@ -76,19 +76,19 @@ namespace EightBit {
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// Address resolution
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register16_t Address_Absolute() {
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auto Address_Absolute() {
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return fetchWord();
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}
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uint8_t Address_ZeroPage() {
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auto Address_ZeroPage() {
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return fetchByte();
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}
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register16_t Address_ZeroPageIndirect() {
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auto Address_ZeroPageIndirect() {
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return getWordPaged(0, Address_ZeroPage());
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}
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register16_t Address_Indirect() {
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auto Address_Indirect() {
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const auto address = Address_Absolute();
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return getWordPaged(address.high, address.low);
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}
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@ -101,110 +101,113 @@ namespace EightBit {
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return Address_ZeroPage() + Y();
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}
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std::tuple<register16_t, bool> Address_AbsoluteX() {
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auto Address_AbsoluteX() {
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auto address = Address_Absolute();
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const auto page = address.high;
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address += X();
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return std::tuple<register16_t, bool>(address, address.high != page);
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return std::make_pair(address, address.high != page);
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}
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std::tuple<register16_t, bool> Address_AbsoluteY() {
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auto Address_AbsoluteY() {
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auto address = Address_Absolute();
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const auto page = address.high;
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address += Y();
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return std::tuple<register16_t, bool>(address, address.high != page);
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return std::make_pair(address, address.high != page);
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}
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register16_t Address_IndexedIndirectX() {
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auto Address_IndexedIndirectX() {
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return getWordPaged(0, Address_ZeroPageX());
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}
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std::tuple<register16_t, bool> Address_IndirectIndexedY() {
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auto Address_IndirectIndexedY() {
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auto address = Address_ZeroPageIndirect();
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const auto page = address.high;
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address += Y();
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return std::tuple<register16_t, bool>(address, address.high != page);
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return std::make_pair(address, address.high != page);
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}
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// Addressing modes, read
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uint8_t AM_Immediate() {
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auto AM_Immediate() {
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return fetchByte();
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}
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uint8_t AM_Absolute() {
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auto AM_Absolute() {
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return BUS().read(Address_Absolute());
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}
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uint8_t AM_ZeroPage() {
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auto AM_ZeroPage() {
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return BUS().read(Address_ZeroPage());
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}
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uint8_t AM_AbsoluteX() {
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const auto ap = Address_AbsoluteX();
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if (UNLIKELY(std::get<1>(ap)))
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auto AM_AbsoluteX() {
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const auto [address, paged] = Address_AbsoluteX();
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if (UNLIKELY(paged))
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addCycle();
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return BUS().read(std::get<0>(ap));
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return BUS().read(address);
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}
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uint8_t AM_AbsoluteY() {
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const auto ap = Address_AbsoluteY();
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if (UNLIKELY(std::get<1>(ap)))
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auto AM_AbsoluteY() {
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const auto [address, paged] = Address_AbsoluteY();
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if (UNLIKELY(paged))
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addCycle();
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return BUS().read(std::get<0>(ap));
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return BUS().read(address);
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}
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uint8_t AM_ZeroPageX() {
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auto AM_ZeroPageX() {
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return BUS().read(Address_ZeroPageX());
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}
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uint8_t AM_ZeroPageY() {
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auto AM_ZeroPageY() {
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return BUS().read(Address_ZeroPageY());
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}
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uint8_t AM_IndexedIndirectX() {
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auto AM_IndexedIndirectX() {
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return BUS().read(Address_IndexedIndirectX());
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}
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uint8_t AM_IndirectIndexedY() {
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const auto ap = Address_IndirectIndexedY();
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if (UNLIKELY(std::get<1>(ap)))
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auto AM_IndirectIndexedY() {
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const auto [address, paged] = Address_IndirectIndexedY();
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if (UNLIKELY(paged))
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addCycle();
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return BUS().read(std::get<0>(ap));
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return BUS().read(address);
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}
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// Addressing modes, write
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void AM_Absolute(uint8_t value) {
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void AM_Absolute(const uint8_t value) {
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BUS().write(Address_Absolute(), value);
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}
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void AM_ZeroPage(uint8_t value) {
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void AM_ZeroPage(const uint8_t value) {
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BUS().write(Address_ZeroPage(), value);
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}
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void AM_AbsoluteX(uint8_t value) {
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BUS().write(std::get<0>(Address_AbsoluteX()), value);
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void AM_AbsoluteX(const uint8_t value) {
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const auto [address, paged] = Address_AbsoluteX();
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BUS().write(address, value);
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}
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void AM_AbsoluteY(uint8_t value) {
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BUS().write(std::get<0>(Address_AbsoluteY()), value);
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void AM_AbsoluteY(const uint8_t value) {
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const auto [address, paged] = Address_AbsoluteY();
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BUS().write(address, value);
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}
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void AM_ZeroPageX(uint8_t value) {
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void AM_ZeroPageX(const uint8_t value) {
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BUS().write(Address_ZeroPageX(), value);
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}
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void AM_ZeroPageY(uint8_t value) {
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void AM_ZeroPageY(const uint8_t value) {
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BUS().write(Address_ZeroPageY(), value);
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}
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void AM_IndexedIndirectX(uint8_t value) {
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void AM_IndexedIndirectX(const uint8_t value) {
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BUS().write(Address_IndexedIndirectX(), value);
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}
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void AM_IndirectIndexedY(uint8_t value) {
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BUS().write(std::get<0>(Address_IndirectIndexedY()), value);
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void AM_IndirectIndexedY(const uint8_t value) {
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const auto [address, paged] = Address_IndirectIndexedY();
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BUS().write(address, value);
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}
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// Operations
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@ -219,77 +222,77 @@ namespace EightBit {
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A() = SBC(A(), value);
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}
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void SLO(uint8_t value) {
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void SLO(const uint8_t value) {
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const auto result = ASL(value);
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BUS().write(result);
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ORA(result);
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}
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void SRE(uint8_t value) {
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void SRE(const uint8_t value) {
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const auto result = LSR(value);
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BUS().write(result);
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EORA(result);
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}
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void RLA(uint8_t value) {
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void RLA(const uint8_t value) {
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const auto result = ROL(value);
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BUS().write(result);
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ANDA(result);
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}
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void RRA(uint8_t value) {
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void RRA(const uint8_t value) {
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const auto result = ROR(value);
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BUS().write(result);
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A() = ADC(A(), result);
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}
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void LAX(uint8_t value) {
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void LAX(const uint8_t value) {
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adjustNZ(X() = A() = value);
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}
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void AAC(uint8_t value) {
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void AAC(const uint8_t value) {
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ANDA(value);
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setFlag(P(), CF, A() & Bit7);
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}
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void ASR(uint8_t value) {
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void ASR(const uint8_t value) {
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A() = LSR(A() & value);
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}
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void ARR(uint8_t value) {
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void ARR(const uint8_t value) {
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}
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void ATX(uint8_t value) {
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void ATX(const uint8_t value) {
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ANDA(value);
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X() = A();
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}
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void AXS(uint8_t value) {
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void AXS(const uint8_t value) {
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}
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//
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uint8_t DEC(uint8_t value) {
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auto DEC(uint8_t value) {
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const auto result = --value;
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adjustNZ(result);
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return result;
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}
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uint8_t INC(uint8_t value) {
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auto INC(uint8_t value) {
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const auto result = ++value;
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adjustNZ(result);
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return result;
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}
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void ORA(uint8_t value) {
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void ORA(const uint8_t value) {
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adjustNZ(A() |= value);
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}
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void ANDA(uint8_t value) {
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void ANDA(const uint8_t value) {
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adjustNZ(A() &= value);
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}
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void EORA(uint8_t value) {
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void EORA(const uint8_t value) {
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adjustNZ(A() ^= value);
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}
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@ -441,7 +441,7 @@ uint8_t EightBit::MOS6502::SUB_d(const uint8_t operand, const uint8_t data, cons
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return promoteNibble(high) | lowNibble(low);
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}
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void EightBit::MOS6502::CMP(uint8_t first, uint8_t second) {
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void EightBit::MOS6502::CMP(const uint8_t first, const uint8_t second) {
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const register16_t result = first - second;
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adjustNZ(result.low);
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clearFlag(P(), CF, result.high);
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@ -487,7 +487,7 @@ uint8_t EightBit::MOS6502::ADD_d(uint8_t operand, uint8_t data, int carry) {
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////
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void EightBit::MOS6502::Branch(int8_t displacement) {
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void EightBit::MOS6502::Branch(const int8_t displacement) {
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const auto page = PC().high;
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PC() += displacement;
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if (UNLIKELY(PC().high != page))
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@ -495,7 +495,7 @@ void EightBit::MOS6502::Branch(int8_t displacement) {
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addCycle();
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}
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void EightBit::MOS6502::Branch(bool flag) {
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void EightBit::MOS6502::Branch(const bool flag) {
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const int8_t displacement = AM_Immediate();
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if (UNLIKELY(flag))
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Branch(displacement);
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120
Z80/inc/Z80.h
120
Z80/inc/Z80.h
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@ -28,7 +28,7 @@ namespace EightBit {
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return (high << 7) | variable;
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}
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refresh_t& operator++() {
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auto& operator++() {
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++variable;
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return *this;
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}
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@ -51,8 +51,8 @@ namespace EightBit {
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Signal<Z80> ExecutingInstruction;
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Signal<Z80> ExecutedInstruction;
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PinLevel& NMI() { return m_nmiLine; } // In
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PinLevel& M1() { return m_m1Line; } // Out
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auto& NMI() { return m_nmiLine; } // In
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auto& M1() { return m_m1Line; } // Out
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virtual int execute(uint8_t opcode) final;
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virtual int step() final;
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@ -63,19 +63,19 @@ namespace EightBit {
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virtual register16_t& DE() final;
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virtual register16_t& HL() final;
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register16_t& IX() { return m_ix; }
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uint8_t& IXH() { return IX().high; }
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uint8_t& IXL() { return IX().low; }
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auto& IX() { return m_ix; }
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auto& IXH() { return IX().high; }
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auto& IXL() { return IX().low; }
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register16_t& IY() { return m_iy; }
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uint8_t& IYH() { return IY().high; }
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uint8_t& IYL() { return IY().low; }
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auto& IY() { return m_iy; }
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auto& IYH() { return IY().high; }
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auto& IYL() { return IY().low; }
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refresh_t& REFRESH() { return m_refresh; }
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uint8_t& IV() { return iv; }
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int& IM() { return m_interruptMode; }
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bool& IFF1() { return m_iff1; }
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bool& IFF2() { return m_iff2; }
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auto& REFRESH() { return m_refresh; }
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auto& IV() { return iv; }
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auto& IM() { return m_interruptMode; }
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auto& IFF1() { return m_iff1; }
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auto& IFF2() { return m_iff2; }
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void exx() {
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m_registerSet ^= 1;
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@ -132,7 +132,50 @@ namespace EightBit {
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m_displacement = fetchByte();
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}
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uint8_t R(const int r) {
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auto& HL2() {
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if (LIKELY(!m_displaced))
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return HL();
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if (m_prefixDD)
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return IX();
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// Must be FD prefix
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return IY();
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}
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auto& RP(const int rp) {
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ASSUME(rp >= 0);
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ASSUME(rp <= 3);
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switch (rp) {
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case 0:
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return BC();
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case 1:
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return DE();
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case 2:
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return HL2();
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case 3:
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return SP();
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default:
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UNREACHABLE;
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}
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}
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auto& RP2(const int rp) {
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ASSUME(rp >= 0);
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ASSUME(rp <= 3);
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switch (rp) {
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case 0:
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return BC();
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case 1:
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return DE();
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case 2:
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return HL2();
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case 3:
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return AF();
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default:
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UNREACHABLE;
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}
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}
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auto R(const int r) {
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ASSUME(r >= 0);
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ASSUME(r <= 7);
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switch (r) {
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@ -190,7 +233,7 @@ namespace EightBit {
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}
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}
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uint8_t R2(const int r) {
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auto R2(const int r) {
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ASSUME(r >= 0);
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ASSUME(r <= 7);
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switch (r) {
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@ -248,49 +291,6 @@ namespace EightBit {
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}
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}
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register16_t& RP(const int rp) {
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ASSUME(rp >= 0);
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ASSUME(rp <= 3);
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switch (rp) {
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case 0:
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return BC();
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case 1:
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return DE();
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case 2:
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return HL2();
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case 3:
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return SP();
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default:
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UNREACHABLE;
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}
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}
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register16_t& HL2() {
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if (LIKELY(!m_displaced))
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return HL();
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if (m_prefixDD)
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return IX();
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// Must be FD prefix
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return IY();
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}
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register16_t& RP2(const int rp) {
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ASSUME(rp >= 0);
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ASSUME(rp <= 3);
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switch (rp) {
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case 0:
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return BC();
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case 1:
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return DE();
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case 2:
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return HL2();
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case 3:
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return AF();
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default:
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UNREACHABLE;
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}
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}
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static void adjustHalfCarryAdd(uint8_t& f, const uint8_t before, const uint8_t value, const int calculation) {
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setFlag(f, HC, calculateHalfCarryAdd(before, value, calculation));
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}
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@ -395,7 +395,7 @@ namespace EightBit {
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void ind();
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bool indr();
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void blockOut(const register16_t source, register16_t& destination);
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void blockOut(register16_t source, register16_t& destination);
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void outi();
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bool otir();
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@ -38,15 +38,16 @@ void EightBit::Z80::powerOn() {
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IV() = Mask8;
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exxAF();
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exx();
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AF() = Mask16;
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IX() = IY() = AF() = BC() = DE() = HL() = Mask16;
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exx();
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IX() = IY() = BC() = DE() = HL() = Mask16;
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m_prefixCB = m_prefixDD = m_prefixED = m_prefixFD = false;
|
||||
}
|
||||
|
||||
void EightBit::Z80::handleRESET() {
|
||||
Processor::handleRESET();
|
||||
IntelProcessor::handleRESET();
|
||||
di();
|
||||
addCycles(3);
|
||||
}
|
||||
|
|
@ -60,7 +61,7 @@ void EightBit::Z80::handleNMI() {
|
|||
}
|
||||
|
||||
void EightBit::Z80::handleINT() {
|
||||
Processor::handleINT();
|
||||
IntelProcessor::handleINT();
|
||||
raise(HALT());
|
||||
if (IFF1()) {
|
||||
di();
|
||||
|
|
@ -73,7 +74,7 @@ void EightBit::Z80::handleINT() {
|
|||
addCycles(13);
|
||||
break;
|
||||
case 2:
|
||||
call(MEMPTR() = register16_t(BUS().DATA(), IV()));
|
||||
call(MEMPTR() = { BUS().DATA(), IV() });
|
||||
addCycles(19);
|
||||
break;
|
||||
default:
|
||||
|
|
@ -599,8 +600,7 @@ bool EightBit::Z80::otdr() {
|
|||
}
|
||||
|
||||
void EightBit::Z80::rrd() {
|
||||
MEMPTR() = BUS().ADDRESS() = HL();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = HL();
|
||||
const auto memory = BUS().read();
|
||||
BUS().write(promoteNibble(A()) | highNibble(memory));
|
||||
A() = higherNibble(A()) | lowerNibble(memory);
|
||||
|
|
@ -609,8 +609,7 @@ void EightBit::Z80::rrd() {
|
|||
}
|
||||
|
||||
void EightBit::Z80::rld() {
|
||||
MEMPTR() = BUS().ADDRESS() = HL();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = HL();
|
||||
const auto memory = BUS().read();
|
||||
BUS().write(promoteNibble(memory) | lowNibble(A()));
|
||||
A() = higherNibble(A()) | highNibble(memory);
|
||||
|
|
@ -619,7 +618,7 @@ void EightBit::Z80::rld() {
|
|||
}
|
||||
|
||||
void EightBit::Z80::writePort(const uint8_t port) {
|
||||
MEMPTR() = BUS().ADDRESS() = register16_t(port, A());
|
||||
MEMPTR() = BUS().ADDRESS() = { port, A() };
|
||||
BUS().DATA() = A();
|
||||
writePort();
|
||||
++MEMPTR().low;
|
||||
|
|
@ -630,7 +629,7 @@ void EightBit::Z80::writePort() {
|
|||
}
|
||||
|
||||
uint8_t EightBit::Z80::readPort(const uint8_t port) {
|
||||
MEMPTR() = BUS().ADDRESS() = register16_t(port, A());
|
||||
MEMPTR() = BUS().ADDRESS() = { port, A() };
|
||||
++MEMPTR().low;
|
||||
return readPort();
|
||||
}
|
||||
|
|
@ -814,8 +813,7 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
|
|||
case 1:
|
||||
switch (z) {
|
||||
case 0: // Input from port with 16-bit address
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = BC();
|
||||
readPort();
|
||||
if (LIKELY(y != 6)) // IN r[y],(C)
|
||||
R(y, BUS().DATA());
|
||||
|
|
@ -824,8 +822,7 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
|
|||
addCycles(12);
|
||||
break;
|
||||
case 1: // Output to port with 16-bit address
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = BC();
|
||||
if (UNLIKELY(y == 6)) // OUT (C),0
|
||||
BUS().DATA() = 0;
|
||||
else // OUT (C),r[y]
|
||||
|
|
@ -1105,15 +1102,13 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
|||
case 0:
|
||||
switch (p) {
|
||||
case 0: // LD (BC),A
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = BC();
|
||||
MEMPTR().high = BUS().DATA() = A();
|
||||
BUS().write();
|
||||
addCycles(7);
|
||||
break;
|
||||
case 1: // LD (DE),A
|
||||
MEMPTR() = BUS().ADDRESS() = DE();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = DE();
|
||||
MEMPTR().high = BUS().DATA() = A();
|
||||
BUS().write();
|
||||
addCycles(7);
|
||||
|
|
@ -1124,8 +1119,7 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
|||
addCycles(16);
|
||||
break;
|
||||
case 3: // LD (nn),A
|
||||
MEMPTR() = BUS().ADDRESS() = fetchWord();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = fetchWord();
|
||||
MEMPTR().high = BUS().DATA() = A();
|
||||
BUS().write();
|
||||
addCycles(13);
|
||||
|
|
@ -1137,14 +1131,12 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
|||
case 1:
|
||||
switch (p) {
|
||||
case 0: // LD A,(BC)
|
||||
MEMPTR() = BUS().ADDRESS() = BC();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = BC();
|
||||
A() = BUS().read();
|
||||
addCycles(7);
|
||||
break;
|
||||
case 1: // LD A,(DE)
|
||||
MEMPTR() = BUS().ADDRESS() = DE();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = DE();
|
||||
A() = BUS().read();
|
||||
addCycles(7);
|
||||
break;
|
||||
|
|
@ -1154,8 +1146,7 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
|||
addCycles(16);
|
||||
break;
|
||||
case 3: // LD A,(nn)
|
||||
MEMPTR() = BUS().ADDRESS() = fetchWord();
|
||||
++MEMPTR();
|
||||
MEMPTR()++ = BUS().ADDRESS() = fetchWord();
|
||||
A() = BUS().read();
|
||||
addCycles(13);
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user