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+Interrupt Behaviour of the Z80 CPU
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+ Interrupt Behaviour of the Z80 CPU
+by Achim Flammenkamp
+
+Interrupt timing
+Only at the end of an instruction execution, except a NOP in case HALT, a LDD in case LDDR, a OUTI in case OTIR, etc., the CPU checks for an interrupt request.
+Thus the INT-pin should be active for at least 23 clock ticks because some IX
+resp. IY instruction last so long.
+Now an interrupt is accepted if INT-pin is low(active) and the interrupt flip flop
+IFF1 is set or the NMI-pin is respectively was active during the just performed instruction.
+If this is the case, the following happens:
+
+Immediately IFF1 is reset to 0 and if INT-pin is low also IFF2 is reset to 0.
+Then the behavior depends whether it is a non maskable interrupt (NMI) or a
+maskable interrupt (INT). In the later case the interrupt mode (IM) of the CPU is
+also decisive:
+
+- NMI
+It takes 11 clock cycles to get to #0066:
+
+ - M1 cycle: 5 T states to do an opcode read and decrement SP
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- M2 cycle: 3 T states write high byte of PC to the stack and decrement SP
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- M3 cycle: 3 T states write the low byte of PC and jump to #0066.
+
+ - INT and interrupt mode 0 set
+In this mode, timing depends on the instruction put on the bus.
+The interrupt processing last 2 clock cycles more
+than this instruction usually needs.
+Two typical examples follow:
+
+a RST n on the data bus, it takes 13 cycles to get to 'n':
+- M1 cycle: 7 ticks
acknowledge interrupt and decrement SP
+ - M2 cycle: 3 ticks
write high byte and decrement SP
+ - M3 cycle: 3 ticks
write low byte and jump to 'n'
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+With a CALL nnnn on the data bus, it takes 19 cycles:
+- M1 cycle: 7 ticks
acknowledge interrupt
+ - M2 cycle: 3 ticks
read low byte of 'nnnn' from data bus
+ - M3 cycle: 3 ticks
read high byte of 'nnnn' and decrement SP
+ - M4 cycle: 3 ticks
write high byte of PC to the stack and decrement SP
+ - M5 cycle: 3 ticks
write low byte of PC and jump to 'nnnn'.
+
+ - INT and interrupt mode 1 set
+It takes 13 clock cycles to reach #0038:
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+ - M1 cycle: 7 ticks
+ acknowledge interrupt and decrement SP
+ - M2 cycle: 3 ticks
+ write high byte of PC onto the stack and decrement SP
+ - M3 cycle: 3 ticks
+ write low byte onto the stack and to set PC to #0038.
+
+ - INT and interrupt mode 2 set
+It takes 19 clock cycles to get to the interrupt routine:
+
+ - M1 cycle: 7 ticks
+ acknowledge interrupt and decrement SP
+ - M2 cycle: 3 ticks
+ write high byte of PC onto stack and decrement SP
+ - M3 cycle: 3 ticks
+ write low byte onto the stack
+ - M4 cycle: 3 ticks
+ read low byte from the interrupt vector
+ - M5 cycle: 3 ticks
+ read high byte from bus and jump to interrupt routine
+
+Some remarks:
+
+- "acknowledge interrupt" means pin IORQ gets together with M1-pin
+active/low. Furthermore the CPU adds 2 wait states to the normal machine cycle.
+
- Quoted remark:
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+- If a LD A,I or LD A,R (which copy IFF2
+to the P/V flag) is interrupted, then the P/V flag is reset, even if
+interrupts were enabled beforehand.
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- If interrupts are disabled when a EI instruction is
+interrupted, then the interrupt will not occur until after the
+instruction following the EI, as when IFF1 is sampled
+during the one and only machine-cycle of the EI, it will be reset.
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+ - An INT will let the INT-pin low(active) until it is indirectly
+reseted by an RETI or other external hardware. In contrast a signal
+at the NMI-pin will be recognized when its state going from high to low!
+Thus it is not a level trigger signal, but a pulse which is stored internally
+by the CPU until the next M1 cycle.
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Reset Timing
+One can consider a reset (RESET-pin gets low) as a very special interrupt.
+If this occurs, the following happens in one machine cycle:
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+It takes 3 clock cycles:
+- IFF1 and IFF2 as well as interrupt mode is set to 0
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- PC is set to 0, I and R registers are reset also.
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- SP is set to 0xffff as well as the A and the F register is set to 0xff.
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Thanks for contribution goes to:
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+Back to main page.
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