6502/EightBit
1
0
Fork 0
mirror of https://github.com/MoleskiCoder/EightBit.git synced 2024-07-03 19:29:29 +00:00
Code Issues Projects Releases Wiki Activity
673 Commits 1 Branch 0 Tags 112 MiB
047babbe7c
Commit Graph

92 Commits

Author SHA1 Message Date
Adrian Conlon
047babbe7c Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 23:09:52 +00:00
Adrian Conlon
25321e78e7 Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 01:32:43 +00:00
Adrian Conlon
06e2a5c947 Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-07 01:06:07 +00:00
Adrian Conlon
c3d2ef51d9 Cycle accuracy for a couple of the indexed write (store) instructions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 20:39:37 +00:00
Adrian Conlon
4d3be9e756 Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 12:58:13 +00:00
Adrian Conlon
baf32cef89 Get the memory access more correct for more of boundary crossing indexed addressing modes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 12:17:43 +00:00
Adrian Conlon
3337f57747 More cycle accuracy changes, concentrating on stack operations. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-05 23:21:43 +00:00
Adrian Conlon
143e9a9e68 More cycle accuracy changes: 
1) implied instruction, pointless fetch
 2) branch pointless fetch when condition is met

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-05 17:23:50 +00:00
Adrian Conlon
556e06426e Further work on the slow migration to a cycle accurate 6502 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-03 01:04:12 +00:00
Adrian Conlon
5ade05a689 Add a bunch of undocumented 6502 instructions. Abandoned ATX implementation. Too poorly documented. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-30 12:01:23 +00:00
Adrian Conlon
815c99710a Add enough undocumented 6502 instructions to get through "nestest". 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-29 22:22:31 +00:00
Adrian Conlon
c136b306ab Use the new busRead/Write processor methods to simplify the 6502 cycle counting. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-29 22:18:01 +00:00
Adrian Conlon
adb60a6e90 Port the 6502 to the new bus architecture. 2018-12-29 19:40:02 +00:00
Adrian Conlon
dc477cd050 Use explicit enumeration types (improves type safety) where appropriate. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-12-01 15:24:29 +00:00
Adrian Conlon
003cea0d64 Make 6502 symbols code a little more like normal C++ 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-11-04 13:27:43 +00:00
Adrian Conlon
8ef5d97366 Update boost from 1.65 -> 1.68 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-11-04 12:58:01 +00:00
Adrian Conlon
4dc0becb74 Refactor the 6502 implementation to be a lot more like the MC6809. Hopefully show bugs in the latter a little more easily. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-31 23:29:13 +00:00
Adrian Conlon
fac2da9ac4 Start refactoring CPU cores to use C++17/14 features. (This commit covers the 6502 and Z80) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-27 18:41:55 +01:00
Adrian Conlon
1b2ddd8843 Don't expose the bus via the CPU any more: if a component needs the bus, it should be prepared to hold a reference to it. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-20 20:52:41 +01:00
Adrian Conlon
735f70e717 Remove a couple of unused headers from the 6502 processor. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-26 19:06:00 +01:00
Adrian Conlon
1212e8d4f0 Tidy some processor virtual specifications. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 13:35:53 +01:00
Adrian Conlon
c105ee37bf Have a stab at sorting out processor pin handling. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 12:09:26 +01:00
Adrian Conlon
b0aacce406 Tidy header file usage a little. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-18 23:56:16 +01:00
Adrian Conlon
cc64e114a9 Start refactoring the processor classes to allow big/little endian processors to be specified. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-17 21:53:49 +01:00
Adrian Conlon
70c70af969 Sort out some exception and member initialisation rules. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-11 21:19:19 +01:00
Adrian Conlon
cac871cf2b Remove duplicated code (from const definitions) the performance benefit isn't worth the amount of duplicated code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-24 20:58:20 +01:00
Adrian Conlon
d27b490d4c (Hopefully) fix compilation issue on g++ 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-16 09:53:44 +01:00
Adrian Conlon
67487b5b6e Simplify the usage of the register16_t union. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-16 00:55:32 +01:00
Adrian Conlon
3e854c7c49 Const some more bus/processor usage, and ensure the data bus is a member, not a reference to memory. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-10 00:40:56 +01:00
Adrian Conlon
d818095815 MEMPTR is really only a concept of Intel style processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-18 22:40:23 +00:00
Adrian Conlon
45dc274167 Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 01:53:57 +00:00
Adrian Conlon
c6eb68ba13 Further return by value, rather than reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-26 19:47:35 +00:00
Adrian Conlon
adf506a41e Optimisation: Prefer return by value to return by reference. ~10% speed-up! 
Just watch a video by Chandler Carruth from 2015, where he talked about C++ optimisers...

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-25 19:48:01 +00:00
Adrian Conlon
1bf2a9bdfb 6502, Disassembly: Some dump methods can be static 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-27 10:13:17 +00:00
Adrian Conlon
9124f10008 6502: Implement some more undocumented instructions (for the Blargg nes cpu tests) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-21 10:45:25 +00:00
Adrian Conlon
b5fee5b5d9 Make explicit the notion of page based loads in M6502. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-18 21:17:45 +00:00
Adrian Conlon
21bd8a06e6 Power on conditions are chip specific and *not* directly related to construction/destruction. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-18 17:50:15 +00:00
Adrian Conlon
19aea5244b The vector of instructions was good, but a switch is fastest and probably easiest to read/modify. (Running at 101Mz, 32M instructions per second) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-17 22:17:08 +00:00
Adrian Conlon
d57cb8c9be 6502: I might regret this, but move to a vector of instructions, rather than decoding them one at a time 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-16 23:54:43 +00:00
Adrian Conlon
43573ac699 6502: Rotate and shift by value, not reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-14 21:03:29 +00:00
Adrian Conlon
ac95670cfc Add support for 6502 pin 38 (SO: set overflow) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-12 20:13:35 +00:00
Adrian Conlon
847e07be86 Add undocumented 6502 instruction RRA. nestest.nes now runs to completion: Hurrah! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-07 23:42:26 +00:00
Adrian Conlon
4d9c0b490a Add undocumented 6502 instruction: SRE 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-07 23:16:24 +00:00
Adrian Conlon
65b856611e Undocumented 6502 instruction RLA added. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-07 22:50:14 +00:00
Adrian Conlon
5b62a6b70b Sort out M6502 precompiled headers. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-06 23:19:29 +00:00
Adrian Conlon
5c3568aebd Undocumented instruction: SLO added 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-04 22:46:44 +00:00
Adrian Conlon
cb89eb8c82 Add undocumented 6502 instruction: ISB 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-04 21:47:50 +00:00
Adrian Conlon
12565966de Remove some assertions from the 6502 implementation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-02 23:24:52 +00:00
Adrian Conlon
4d5afb67a3 Refactor the 6502 code a little. No functional changes and tests still seem to work. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-02 21:20:47 +00:00
Adrian Conlon
345ab2e2c6 Undocumented instruction: DCP added 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-01 21:05:42 +00:00