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Author SHA1 Message Date
Adrian Conlon
4b2f8e3599 Correct "LE" definition to at least match the MC6809 documentation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-17 20:39:58 +01:00
Adrian Conlon
8c8438f819 Tidy the test code formatting a little 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 23:39:37 +01:00
Adrian Conlon
4e48f4a5a0 Slightly simplify half-carry evaluation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 23:18:13 +01:00
Adrian Conlon
140e87485c Whoops: Correct dodgy CMP test. That explains why I never understood why it was failing! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 21:26:33 +01:00
Adrian Conlon
9d71c78338 DEC/INC don't adjust carry flags 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 21:19:37 +01:00
Adrian Conlon
0c07d39250 Share (hopefully!) correct overflow implementations 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 21:19:03 +01:00
Adrian Conlon
707a742899 Not complete, but this gets large chunks of the MC6809 addition and subtraction parts of the emulator working correctly 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 20:40:20 +01:00
Adrian Conlon
337e35ca1b Use the newly added CPU pokeWord method. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 20:39:09 +01:00
Adrian Conlon
769c65394b The extra _getch isn't required as I fix the MC6809 CPU emulation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 20:38:07 +01:00
Adrian Conlon
12dc90c064 Add lots of tests, mainly covering addition and subtraction. Shows quite a few problems... 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 10:06:47 +01:00
Adrian Conlon
7e527ff093 Add Processor::pokeWord to define an endian specific 16-bit word write. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-14 10:05:43 +01:00
Adrian Conlon
9445e7d1c4 Add test for CLRA implied 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-07 11:04:22 +01:00
Adrian Conlon
9296eaf954 Add test for BITA immediate. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-07 10:55:30 +01:00
Adrian Conlon
cf32f37fc3 Add test for ASRA inherent. And fix resulting bugs exposed! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-07 10:48:27 +01:00
Adrian Conlon
f2b9ab0814 Add test for ASLA inherent. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-07 10:32:26 +01:00
Adrian Conlon
7719c8e875 Add test for ANDA immediate 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-07 10:08:12 +01:00
Adrian Conlon
1f4a84b803 Add test for ADDA immediate. Seems to be working. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-07 09:47:10 +01:00
Adrian Conlon
5dc185866e Add a test for ADCA immediate. Half carry and overflow flags incorrect! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-07 09:14:30 +01:00
Adrian Conlon
7e57efd4cd Modification of unit test comments: no functional modification. 2018-10-06 23:54:33 +01:00
Adrian Conlon
fe05d468d6 Start adding MC6809 unit tests for each instruction. Just ABX, so far 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-06 23:52:39 +01:00
Adrian Conlon
8048165aab Reorder the output of the M6850 status dump, so it more easily matches the bit order most -> least significant. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-03 20:16:59 +01:00
Adrian Conlon
0c174afc02 More MC6809 disassembly corrections: tabs and pshu/s puls/u stack order. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-03 20:15:44 +01:00
Adrian Conlon
f6cd8a4277 Properly disassemble MC6809 PULS/PULU PSHS/PSHU instructions to show registers. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-02 22:35:31 +01:00
Adrian Conlon
f58e3ded83 Use corrected MC6850 in MC6809 test board. Working a little better now. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-30 23:10:03 +01:00
Adrian Conlon
042e066a0c Correct status handling in the MC6850, and improve documentation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-30 23:07:07 +01:00
Adrian Conlon
8ea7bf5d68 Refactoring on the MC6850 and associated test board code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-29 14:31:50 +01:00
Adrian Conlon
8d3551e681 Refactor bit set/get routines from processor class to lower level chip class. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-29 14:08:44 +01:00
Adrian Conlon
de5a9963e0 More MC6850 updates 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-29 10:06:02 +01:00
Adrian Conlon
f6bd871757 Whoops: correct 6809 stack pointer increment/decrement order 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-29 10:02:53 +01:00
Adrian Conlon
861fc28bba Wire up the MC6850 events to the board 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-25 23:57:20 +01:00
Adrian Conlon
df7c7904f4 Whoops: correct a small layout (tabs) issue. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-25 23:56:28 +01:00
Adrian Conlon
4f567c75f9 Probably doesn't work, but this is another style of MC6850 event handling 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-25 23:55:14 +01:00
Adrian Conlon
9ab075d0f6 Incorporate the concepts of transmission and receipt into the events for the MC6850 (TBC) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-24 08:29:11 +01:00
Adrian Conlon
d77c2a1e9d Add more of the MC6850 internals. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-23 20:31:55 +01:00
Adrian Conlon
b3faa0bb2e Wire the MC6850 chip into the MC6809 test code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-23 13:14:10 +01:00
Adrian Conlon
754fc8e6a3 Refactor the processor class to give us a "Chip" class that gives up pin levels and power. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-23 13:10:58 +01:00
Adrian Conlon
91349eafa4 Updated MC6850 documentation. Bit more searchable... 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-23 10:19:39 +01:00
Adrian Conlon
be2f5abdb5 Correct a couple of small layout issues in the MC6850 code 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-23 00:08:16 +01:00
Adrian Conlon
e2f69b1dc8 Start adding support for the Motorola serial device, the MC6850 ACIA (most incomplete!) 2018-09-22 23:11:13 +01:00
Adrian Conlon
30ac7dc268 Whoops: missed movement of stdafx.h for MC6809 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-22 23:09:10 +01:00
Adrian Conlon
d45401d9b1 Tidy a couple of MC6809 niggles: 
1) Move the stdafx.h to the correct place (out of the include search path)
2) Simplify long branch extra cycle handling
3) Rename derived flag handling, to remove B prefix
4) Make interrupt mask flag handling a little easier to read

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-22 10:54:05 +01:00
Adrian Conlon
7c03521025 Refactor plsu/s pshu/s to share code more easily 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-21 00:28:08 +01:00
Adrian Conlon
6bb8118c7f Add miscellaneous documentation and test gubbins 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-21 00:17:25 +01:00
Adrian Conlon
7adefd380a Sort a bunch of missing argument const specifications. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-21 00:16:00 +01:00
Adrian Conlon
9e91d2adad Plug the 8K hole in the address space of the Grant Searle SBC with 0xff (held high) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-16 19:49:52 +01:00
Adrian Conlon
54bb9743be Correct 10/11 opcode prefix disassembly on the 6809 processor. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-16 17:56:55 +01:00
Adrian Conlon
2d93087e5f Correct the hex loader, using the new mapping mechanism. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-16 17:54:53 +01:00
Adrian Conlon
fe3794e011 Simplify register16_t usage a little. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-16 12:00:29 +01:00
Adrian Conlon
6256d0bf8d Correct compilation warnings. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-15 18:33:33 +01:00
Adrian Conlon
7d840f1a42 Modifying the manner in which memory is mapped, allows a fairly clean mechanism for loading Intel "hex" files. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-15 14:35:59 +01:00