Commit Graph

21 Commits

Author SHA1 Message Date
Adrian Conlon
7d840f1a42 Modifying the manner in which memory is mapped, allows a fairly clean mechanism for loading Intel "hex" files.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-09-15 14:35:59 +01:00
Adrian Conlon
97272d650d Simplify processor bus access a little by further allowing register16_t address access.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-08-29 13:52:25 +01:00
Adrian Conlon
a8cc289149 Whoops: The "Bus" class *really* isn't allowed to know the "endianness" of the attached processor!
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-08-27 11:27:33 +01:00
Adrian Conlon
15e1258f40 Rearrange the 6809 code such that I can fire memory events.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-08-19 00:55:59 +01:00
Adrian Conlon
ab1d84703b Add a skeletal 6809 processor.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-08-19 00:18:08 +01:00
Adrian Conlon
1abe3ae456 Adding a couple of const member accessors allows some event handlers to be marked const
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-08-12 17:08:03 +01:00
Adrian Conlon
e40240694f More removal of duplicated code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-06-24 22:33:02 +01:00
Adrian Conlon
cac871cf2b Remove duplicated code (from const definitions) the performance benefit isn't worth the amount of duplicated code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-06-24 20:58:20 +01:00
Adrian Conlon
67487b5b6e Simplify the usage of the register16_t union.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-06-16 00:55:32 +01:00
Adrian Conlon
fbf098ae00 Simplify memory event handlers and ROM recognition a little (bit of speed difference)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-06-10 22:00:52 +01:00
Adrian Conlon
3e854c7c49 Const some more bus/processor usage, and ensure the data bus is a member, not a reference to memory.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-06-10 00:40:56 +01:00
Adrian Conlon
7f501ff29c Temporarily perhaps, reintroduce post-read and pre-write bus events (for the NES)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2018-02-07 23:00:38 +00:00
Adrian Conlon
d70f6b375b Ensure each header file has a newline on its own at the end of each file.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-11-30 23:19:17 +00:00
Adrian Conlon
4b2d84dba3 Whoops: missed clang warning.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-11-30 16:55:10 +00:00
Adrian Conlon
d010e3ca2f Start incorporating CPP core guidelines (as an experiment!)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-11-10 22:41:50 +00:00
Adrian Conlon
a22e59546b Tidy the gameboy core a little. Mainly by moving the execution loops into the bus class.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-10-24 00:04:13 +01:00
Adrian Conlon
10913bf1b8 Remove some unused signals.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-10-01 22:22:25 +01:00
Adrian.Conlon
b445457b37 Fire pre/post memory read/write events
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-09-14 15:00:57 +01:00
Adrian.Conlon
a77e57e5fc Add pre/post read/write memory events.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-09-13 23:12:47 +01:00
Adrian.Conlon
b0923bd472 (Coverity) Initialise Bus variables in constructor.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-09-07 13:45:16 +01:00
Adrian.Conlon
64b7335a79 Attempted move to a "BUS" oriented memory architecture (TBC!)
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-09-06 13:22:23 +01:00