Adrian Conlon
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dfc4c49454
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Correct 5-bit sign extension on the 6809 processor. Allows CLR 5-bit offset indexed disassembly to work correctly.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-27 12:57:44 +01:00 |
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Adrian Conlon
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a8cc289149
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Whoops: The "Bus" class *really* isn't allowed to know the "endianness" of the attached processor!
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-27 11:27:33 +01:00 |
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Adrian Conlon
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c105ee37bf
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Have a stab at sorting out processor pin handling.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-25 12:09:26 +01:00 |
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Adrian Conlon
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6d4223c368
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Start moving towards reset being just another style of interrupt.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-25 01:34:30 +01:00 |
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Adrian Conlon
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2a3b0a5291
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Add JMP and JSR instructions to the 6809 processor.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-21 18:10:38 +01:00 |
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Adrian Conlon
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cc64e114a9
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Start refactoring the processor classes to allow big/little endian processors to be specified.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-17 21:53:49 +01:00 |
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Adrian Conlon
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ed76038bfa
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More memptr adjustments
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-17 13:59:59 +01:00 |
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Adrian Conlon
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70c70af969
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Sort out some exception and member initialisation rules.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-08-11 21:19:19 +01:00 |
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Adrian Conlon
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e40240694f
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More removal of duplicated code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-06-24 22:33:02 +01:00 |
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Adrian Conlon
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67487b5b6e
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Simplify the usage of the register16_t union.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-06-16 00:55:32 +01:00 |
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Adrian Conlon
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3e854c7c49
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Const some more bus/processor usage, and ensure the data bus is a member, not a reference to memory.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-06-10 00:40:56 +01:00 |
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Adrian Conlon
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116f9961c4
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Add a higher/lower nibble mask
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-05-25 22:36:10 +01:00 |
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Adrian Conlon
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9de0f597f6
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Remove some "tricksy" code from the Z80 emulator chain.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-04-14 09:39:06 +01:00 |
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Adrian Conlon
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d818095815
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MEMPTR is really only a concept of Intel style processors.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-03-18 22:40:23 +00:00 |
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Adrian Conlon
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45dc274167
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Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-03-10 01:53:57 +00:00 |
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Adrian Conlon
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adf506a41e
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Optimisation: Prefer return by value to return by reference. ~10% speed-up!
Just watch a video by Chandler Carruth from 2015, where he talked about C++ optimisers...
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-02-25 19:48:01 +00:00 |
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Adrian Conlon
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21bd8a06e6
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Power on conditions are chip specific and *not* directly related to construction/destruction.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-18 17:50:15 +00:00 |
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Adrian Conlon
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108f66632e
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Performance: watch out for unnecessary virtualised methods.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2018-01-06 17:13:02 +00:00 |
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Adrian Conlon
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1edabd79f3
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More pinout oriented method of executing instructions (especially interrupts)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-12-10 21:41:48 +00:00 |
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Adrian Conlon
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7e3957d4db
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Rewrite i8080 interrupts to be more closely related to the hardware.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-12-02 23:50:59 +00:00 |
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Adrian Conlon
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d70f6b375b
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Ensure each header file has a newline on its own at the end of each file.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-30 23:19:17 +00:00 |
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Adrian Conlon
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12385dcc6f
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More clang warnings corrected.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-30 23:15:40 +00:00 |
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Adrian Conlon
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a0f7d584b6
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Correct a few warnings reported by "clang"
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-30 14:37:18 +00:00 |
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Adrian Conlon
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c513f0cab1
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GSL was too problematic when used with GCC. Removed.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-20 19:17:49 +00:00 |
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Adrian Conlon
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67c27d4a3e
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GSL + CPP core guidelines changes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-18 14:29:30 +00:00 |
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Adrian Conlon
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47446a617d
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the "run" method is probably better off not being overridden.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-11 15:50:55 +00:00 |
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Adrian Conlon
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d010e3ca2f
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Start incorporating CPP core guidelines (as an experiment!)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-10 22:41:50 +00:00 |
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Adrian Conlon
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8143f8a506
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Try to correct "one definition rule" problems:
1) No forward declarations
2) No virtual methods defined inline.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-05 12:47:42 +00:00 |
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Adrian Conlon
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926ac48224
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Move to VS2017
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-04 23:15:55 +00:00 |
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Adrian Conlon
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c292fb552e
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A whole bunch of consistency changes. No functional changes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2017-11-03 22:05:01 +00:00 |
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Adrian.Conlon
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64b7335a79
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Attempted move to a "BUS" oriented memory architecture (TBC!)
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
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2017-09-06 13:22:23 +01:00 |
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Adrian.Conlon
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da806bddcb
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Tidy some more Windows/Linux compatibility issues.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-09-03 21:30:46 +01:00 |
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Adrian.Conlon
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640b2be670
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Parts of the EightBit library become linux compatible (TBC!)
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-09-03 12:11:14 +01:00 |
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Adrian.Conlon
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9b43b74c28
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Rationalise some of the reset/initialise logic across pProcessor implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-09-01 16:01:40 +01:00 |
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Adrian.Conlon
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1eb127ed72
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Add power support to processor base class.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-31 12:13:00 +01:00 |
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Adrian.Conlon
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e70686c5de
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Some more rationalisation of processor execution/stepping strategies.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-30 23:17:34 +01:00 |
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Adrian.Conlon
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ec15a2c90c
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Correct SP arithmetic methods: All Blargg CPU tests now pass. Hurrah!
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-28 23:04:25 +01:00 |
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Adrian.Conlon
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d710a28526
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More consolidation of instruction implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-28 21:18:08 +01:00 |
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Adrian.Conlon
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329fd269ed
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Share some more code from the 6502 processor implementation.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-28 18:52:48 +01:00 |
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Adrian.Conlon
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59e9adf57c
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Share more of push/pop implementation across processors.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-28 13:19:17 +01:00 |
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Adrian.Conlon
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448ee2f09f
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Refactor the MBC implementation to allow a single point of definition.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-24 10:28:31 +01:00 |
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Adrian.Conlon
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8716035396
|
Second stage halt implementation: allow halt state to be exited by an interrupt.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-20 20:09:21 +01:00 |
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Adrian.Conlon
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016b3bca59
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Switch to a memory read/write event driven model. All tests passing.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-08-06 17:06:48 +01:00 |
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Adrian.Conlon
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b6dd48ca63
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Some more small clarifications of shared processor implementation.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-25 18:56:43 +01:00 |
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Adrian.Conlon
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4f491f110e
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Make the 6502 a little more compatible with other processor implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-17 13:46:06 +01:00 |
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Adrian.Conlon
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8c81a27224
|
"Modernise" the 6502 emulator a little. Not complete, but does successfully complete Klaus Dormann tests.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-11 21:34:01 +01:00 |
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Adrian.Conlon
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3c0a1697fd
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Fetching bytes/words and stack access are more processor specific than I thought.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-07-07 09:27:06 +01:00 |
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Adrian.Conlon
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c9bf24d1fa
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Tidy up register and static method access.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
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2017-06-19 13:53:00 +01:00 |
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Adrian.Conlon
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627e41bf35
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Introduce an IntelProcessor base class to allow known good implementation to be shared.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-11 09:45:34 +01:00 |
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Adrian.Conlon
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b1aa523dcc
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Small simplifications to base Processor class.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
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2017-06-10 12:42:55 +01:00 |
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