6502/EightBit
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64 Commits

Author SHA1 Message Date
Adrian Conlon
c105ee37bf Have a stab at sorting out processor pin handling. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 12:09:26 +01:00
Adrian Conlon
cc64e114a9 Start refactoring the processor classes to allow big/little endian processors to be specified. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-17 21:53:49 +01:00
Adrian Conlon
70c70af969 Sort out some exception and member initialisation rules. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-11 21:19:19 +01:00
Adrian Conlon
cac871cf2b Remove duplicated code (from const definitions) the performance benefit isn't worth the amount of duplicated code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-24 20:58:20 +01:00
Adrian Conlon
67487b5b6e Simplify the usage of the register16_t union. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-16 00:55:32 +01:00
Adrian Conlon
3e854c7c49 Const some more bus/processor usage, and ensure the data bus is a member, not a reference to memory. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-10 00:40:56 +01:00
Adrian Conlon
d818095815 MEMPTR is really only a concept of Intel style processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-18 22:40:23 +00:00
Adrian Conlon
45dc274167 Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 01:53:57 +00:00
Adrian Conlon
c6eb68ba13 Further return by value, rather than reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-26 19:47:35 +00:00
Adrian Conlon
adf506a41e Optimisation: Prefer return by value to return by reference. ~10% speed-up! 
Just watch a video by Chandler Carruth from 2015, where he talked about C++ optimisers...

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-25 19:48:01 +00:00
Adrian Conlon
9124f10008 6502: Implement some more undocumented instructions (for the Blargg nes cpu tests) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-21 10:45:25 +00:00
Adrian Conlon
b5fee5b5d9 Make explicit the notion of page based loads in M6502. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-18 21:17:45 +00:00
Adrian Conlon
21bd8a06e6 Power on conditions are chip specific and *not* directly related to construction/destruction. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-18 17:50:15 +00:00
Adrian Conlon
19aea5244b The vector of instructions was good, but a switch is fastest and probably easiest to read/modify. (Running at 101Mz, 32M instructions per second) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-17 22:17:08 +00:00
Adrian Conlon
d57cb8c9be 6502: I might regret this, but move to a vector of instructions, rather than decoding them one at a time 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-16 23:54:43 +00:00
Adrian Conlon
43573ac699 6502: Rotate and shift by value, not reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-14 21:03:29 +00:00
Adrian Conlon
ac95670cfc Add support for 6502 pin 38 (SO: set overflow) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-12 20:13:35 +00:00
Adrian Conlon
847e07be86 Add undocumented 6502 instruction RRA. nestest.nes now runs to completion: Hurrah! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-07 23:42:26 +00:00
Adrian Conlon
4d9c0b490a Add undocumented 6502 instruction: SRE 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-07 23:16:24 +00:00
Adrian Conlon
65b856611e Undocumented 6502 instruction RLA added. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-07 22:50:14 +00:00
Adrian Conlon
5c3568aebd Undocumented instruction: SLO added 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-04 22:46:44 +00:00
Adrian Conlon
cb89eb8c82 Add undocumented 6502 instruction: ISB 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-04 21:47:50 +00:00
Adrian Conlon
12565966de Remove some assertions from the 6502 implementation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-02 23:24:52 +00:00
Adrian Conlon
4d5afb67a3 Refactor the 6502 code a little. No functional changes and tests still seem to work. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-02 21:20:47 +00:00
Adrian Conlon
345ab2e2c6 Undocumented instruction: DCP added 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-01 21:05:42 +00:00
Adrian Conlon
1beee9782f Undocumented instruction: SAX added 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-01 12:46:21 +00:00
Adrian Conlon
75aece30e3 Undocumented instruction: LAX added. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-01 12:28:00 +00:00
Adrian Conlon
82fe35891d Linux compatibility changes 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-30 15:22:27 +00:00
Adrian Conlon
2683999e2c Mild refactoring, no functional change... 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-30 14:33:48 +00:00
Adrian Conlon
8e4030a5aa Add some performance hints to conditionals. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-29 14:56:26 +00:00
Adrian Conlon
412a44fafd Correct some page crossing conditions affecting 6502 cycle counts. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-29 14:49:53 +00:00
Adrian Conlon
0604d5cf22 Actually, all 6502 getWord usage has an invariant high page indicator. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-29 11:50:24 +00:00
Adrian Conlon
7432e602f8 Correct a 6502 bug in absolute indirect addressing mode (unchanging page on address resolution). 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-28 16:15:22 +00:00
Adrian Conlon
dcf99bf65d Zero page indirection should completely ignore the high byte of the address line. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-28 15:16:21 +00:00
Adrian Conlon
81ed53ce11 First stab at a Ricoh 2A03: A 6502 minus decimal mode support. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-25 23:34:56 +00:00
Adrian Conlon
1edabd79f3 More pinout oriented method of executing instructions (especially interrupts) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-10 21:41:48 +00:00
Adrian Conlon
0b6ef3d4dd VS2017 and CPP core guidelines updates 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-11 15:13:26 +00:00
Adrian Conlon
c292fb552e A whole bunch of consistency changes. No functional changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-03 22:05:01 +00:00
Adrian.Conlon
c472d70c5c Ensure the MOS6502 unit tests run successfully to completion. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-07 00:58:56 +01:00
Adrian.Conlon
9b43b74c28 Rationalise some of the reset/initialise logic across pProcessor implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 16:01:40 +01:00
Adrian.Conlon
e70686c5de Some more rationalisation of processor execution/stepping strategies. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-30 23:17:34 +01:00
Adrian.Conlon
d710a28526 More consolidation of instruction implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 21:18:08 +01:00
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 18:52:48 +01:00
Adrian.Conlon
59e9adf57c Share more of push/pop implementation across processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 13:19:17 +01:00
Adrian.Conlon
12c9125e9b Correct warning in 6502 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-23 22:30:58 +01:00
Adrian.Conlon
99c2e2a719 Tidy up the 10 addressing mode write set to make it clearer when memory writes occur. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-07 21:25:21 +01:00
Adrian.Conlon
aa720c4c12 Pass all Klaus Dormann tests again: correct AM_10 write algorithm. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-07 21:02:31 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00
Adrian.Conlon
017b2a6442 Tidy up memory event handling to make it a bit easier to verify read/write events. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-17 21:00:05 +01:00