6502/EightBit
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191 Commits

Author SHA1 Message Date
Adrian Conlon
59d1e2789e Whoops: missed reference to RapidJson 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-11 19:39:37 +01:00
Adrian Conlon
7a7b0046cd Add an implementation that uses JsonCpp (pretty slow!) 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-11 19:13:05 +01:00
Adrian Conlon
f3f6452119 Add nlohmann json parser as an option to build. 
1/2 speed, compared to boost.json

Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-11 14:59:23 +01:00
Adrian Conlon
db106b1719 Performance: speed up message handling in TestRunner. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-11 11:41:50 +01:00
Adrian Conlon
5686906583 Add nodiscard attributes, where needed 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-11 10:43:33 +01:00
Adrian Conlon
4be61a9d54 Separate concerns a little between low level classes and high level classes in terms of report generation. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-11 10:20:18 +01:00
Adrian Conlon
760f5d5aec Correct filler memoryRead accesses to use PC() rather than the last location read. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-10 21:35:26 +01:00
Adrian Conlon
6a59bfbcd8 First stab at using the Harte randomised processor tests. Some failures detected in the M6502 run. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-10 21:26:30 +01:00
Adrian Conlon
6c3ef821bf Update for latest boost v1.77 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-10-10 21:25:21 +01:00
Adrian Conlon
22506ea56c Extensive change warning: lots of "noexcept" and "constexpr" changes. Not sure if I'll keep all of them, but interesting... 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-07-18 14:28:40 +01:00
Adrian Conlon
2f76e901f9 More tidying of include files for VS2019 compatibility (plus more correct!) 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-05-29 12:18:13 +01:00
Adrian Conlon
cab29e3ce4 Tidy some code formatting. No functional changes. 2021-04-07 21:37:30 +01:00
Adrian Conlon
2992a0e78a Event fire: use default arguments, where possible. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-04-07 21:36:53 +01:00
Adrian Conlon
2fa9ffd1e3 Tidy up some C++ a little 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-04-07 21:36:09 +01:00
Adrian Conlon
b1ca06447f Ensure 6502 uses memory rather than bus read/write mechanism 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2021-03-08 16:44:09 +00:00
Adrian Conlon
6285a397ab Tidy 6502 whitespace 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2020-02-22 09:02:37 +00:00
Adrian Conlon
c8bdabf34f Reflect that the I/O for Intel style processors isn't part of the CPU, but attached to the Bus and access controlled by the CPU. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2020-02-09 11:51:58 +00:00
Adrian Conlon
d9466082ec M-Cycle accurate Z80 modifications. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-12-29 01:18:54 +00:00
Adrian Conlon
d0467421ff Improve compatibility with .net emulator code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-09 18:58:23 +00:00
Adrian Conlon
ee3ecc682d Add R/W pins to the MC6809 and MOS6502 processors. Hoping it'll ease peripheral development. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-09-15 12:49:32 +01:00
Adrian Conlon
254cfbe342 Tidied up pin management to be synchronised with the .Net code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-09-06 23:55:57 +01:00
Adrian Conlon
6940a54355 Update all EightBit projects to VS2019 (Latest SDK, C++17) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-08-17 11:04:29 +01:00
Adrian Conlon
5e9014997a Upgraded to VS2019, default SDK. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-08-06 13:16:38 +01:00
Adrian Conlon
def1c58e9d Tidy project settings across the EightBit library to be more consistent. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-07-06 22:45:16 +01:00
Adrian Conlon
f5582df402 Add some more M6502 documentation. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-05-05 10:30:33 +01:00
Adrian Conlon
1a0d3ad77a Go through all projects for configuration consistency. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-05-05 10:25:44 +01:00
Adrian Conlon
f0376fa81e Use macros to define our device pins. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 23:17:54 +00:00
Adrian Conlon
7f853ec73f Add missing 6502 pin events 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 08:26:27 +00:00
Adrian Conlon
92d23d82d6 Start big refactor of device/CPU pin usage (to allow pin events throughout). 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-14 02:10:17 +00:00
Adrian Conlon
68030610d8 Move to an event driven clock tick event for all CPUs 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-09 23:24:33 +00:00
Adrian Conlon
8b187e7614 The clock still has to tick, even while held on RDY low, otherwise cycle timing won't work. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-09 09:05:12 +00:00
Adrian Conlon
a90ca6ba38 Move RDY initialisation to the CPU power-on sequence. Not strictly correct, but OK. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-09 00:33:56 +00:00
Adrian Conlon
87d86bcd84 Whoops: missed unneeded method declaration. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-09 00:08:03 +00:00
Adrian Conlon
01175cf9eb Add support for emulated SYNC and RDY lines. Untested, but feel close. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 23:55:27 +00:00
Adrian Conlon
047babbe7c Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 23:09:52 +00:00
Adrian Conlon
25321e78e7 Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-08 01:32:43 +00:00
Adrian Conlon
3faec680b0 I think this fixes one of my NES issues. The fix-up required for the PC is handled by the fetchByte associated with the BRK instruction. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-07 01:28:23 +00:00
Adrian Conlon
d7763d8215 Profile mode no longer exists on the 6502 test program. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-07 01:08:23 +00:00
Adrian Conlon
06e2a5c947 Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-07 01:06:07 +00:00
Adrian Conlon
b7b7c93a77 This tidies the last of 6502 cycle accurate instruction implementations. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 22:34:53 +00:00
Adrian Conlon
ad644f7013 Tidy the 6502 instruction switch statement a little to lessen the width a little. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 20:51:13 +00:00
Adrian Conlon
c3d2ef51d9 Cycle accuracy for a couple of the indexed write (store) instructions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 20:39:37 +00:00
Adrian Conlon
4d3be9e756 Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 12:58:13 +00:00
Adrian Conlon
baf32cef89 Get the memory access more correct for more of boundary crossing indexed addressing modes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 12:17:43 +00:00
Adrian Conlon
a13ad5042a Correct constructions of register16_t: the structure is "#ifdef"ed for different endian arrangements. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 11:27:43 +00:00
Adrian Conlon
3749585398 Cycle accuracy changes for BRK/RTI instructions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-06 11:13:49 +00:00
Adrian Conlon
3337f57747 More cycle accuracy changes, concentrating on stack operations. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-05 23:21:43 +00:00
Adrian Conlon
f5125b2a35 Add some documentation regarding instruction cycle timings. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-05 23:21:12 +00:00
Adrian Conlon
143e9a9e68 More cycle accuracy changes: 
1) implied instruction, pointless fetch
 2) branch pointless fetch when condition is met

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-05 17:23:50 +00:00
Adrian Conlon
3b7cec9c69 Spot a couple more addCycle patterns. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-01-04 09:17:59 +00:00