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47 Commits

Author SHA1 Message Date
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 18:52:48 +01:00
Adrian.Conlon
73a34f4fae Start a more careful documentation of the I/O registers. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-26 09:46:53 +01:00
Adrian.Conlon
246e6431ab Small correction to GB SP instructions passes a little more of the Blargg tests. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-25 10:33:22 +01:00
Adrian.Conlon
a087750d9c Interrupt handling doesn't use the current running cycles. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-21 09:34:17 +01:00
Adrian.Conlon
8716035396 Second stage halt implementation: allow halt state to be exited by an interrupt. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 20:09:21 +01:00
Adrian.Conlon
57e48e389f First stage "halt" reimplementation: allow the clock to run during halt, but nothing else. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 19:44:57 +01:00
Adrian.Conlon
42b0fdc23d Implement DIV timer (TBC) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 09:52:26 +01:00
Adrian.Conlon
86a4e22ae1 First stab at implementing GB timer control. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-18 19:00:10 +01:00
Adrian.Conlon
0457dffba4 Rewrite GB interrupt handling to properly document the trigger sequence. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-18 09:49:06 +01:00
Adrian.Conlon
039545bd08 Rearrange some of the shift/rotate code a little to make it easier to read. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-16 22:51:15 +01:00
Adrian.Conlon
87e97eea8c Fixes rotates and shifts zero flag use (i.e. 09 - op r,r,s now runs successfully) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-15 23:27:46 +01:00
Adrian.Conlon
6506b33436 Add comment noting GB: unique instruction. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 18:41:51 +01:00
Adrian.Conlon
fb13d9fdce Correct GB: SWAP r operation. The demoted high nibble was being effectively zeroed each time. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 21:34:19 +01:00
Adrian.Conlon
9fcb349e1f Brought the LR35902 a little closer to the Z80 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-08 13:32:51 +01:00
Adrian.Conlon
88d773708c Correct some outstanding LR35902 problems arising. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 22:04:13 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
261433bd6e Remove unneeded 16-bit operations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-27 21:44:24 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00
Adrian.Conlon
9a264c7c06 Bring the LR35902 and i8080 increment/decrement implementations in line with the Z80. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-22 10:23:13 +01:00
Adrian.Conlon
0a02c32695 Some things (namely shift.rotate instructions) don't need to be quite so close to the Z80 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 19:23:36 +01:00
Adrian.Conlon
beca76d733 Share instruction decoding mechanism between Intel derived processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 13:33:17 +01:00
Adrian.Conlon
7c3fc469a8 Bring LR35902 a little closer to the Z80 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-20 12:37:54 +01:00
Adrian.Conlon
1ee9a010b5 Finally: a working daa 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-20 10:42:18 +01:00
Adrian.Conlon
9c240b7ea8 Correct for CF not being the first bit of the flags register (why!!!!) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-19 23:16:17 +01:00
Adrian.Conlon
36fbee35fb Bring the various IntelProcessor derived processors a little closer together. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-07-19 13:59:28 +01:00
Adrian.Conlon
758574007d Ensure GB register accesses pass through bus notification code. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-18 21:41:10 +01:00
Adrian.Conlon
974c3353cc Simplify LR35902 memory read/write a little. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-07-18 11:28:06 +01:00
Adrian.Conlon
35def4184a Start adding enough infrastructure to support memory mapped IO on LR35902. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-18 00:13:41 +01:00
Adrian.Conlon
627d30e896 Merge branch 'master' of https://github.com/MoleskiCoder/EightBit 2017-07-17 21:39:13 +01:00
Adrian.Conlon
2b29c3fe64 Correct a couple of LR35902 issues. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-17 21:38:58 +01:00
Adrian.Conlon
3c0a1697fd Fetching bytes/words and stack access are more processor specific than I thought. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-07 09:27:06 +01:00
Adrian.Conlon
67174d74af Correct some memory access issues in LR35902 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-23 21:23:20 +01:00
Adrian.Conlon
af375ab10f Some more shared code. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-22 19:00:53 +01:00
Adrian.Conlon
052df61250 Remove get/getWord and set/setWord from memory class. Just use address and data lines on the memory. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-20 14:09:44 +01:00
Adrian.Conlon
c9bf24d1fa Tidy up register and static method access. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-19 13:53:00 +01:00
Adrian.Conlon
23108a8536 Bring performance back to par by: inlining and static flag register access, where possible. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-18 18:14:39 +01:00
Adrian.Conlon
71e6902aeb Simplify and remove a bunch of code. Getting there! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-15 22:21:26 +01:00
Adrian.Conlon
66d3a5ae29 Couple of small simplifications. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-13 23:43:21 +01:00
Adrian.Conlon
8f3aef1c3e Make LR35902 a little more like the Z80 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 23:56:11 +01:00
Adrian.Conlon
eb8a93726d Correct a few small LR35902 issues. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 22:07:48 +01:00
Adrian.Conlon
0291970427 Further work on uniting the 8080 family processor family. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 21:08:40 +01:00
Adrian.Conlon
627e41bf35 Introduce an IntelProcessor base class to allow known good implementation to be shared. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 09:45:34 +01:00
Adrian.Conlon
49d7a4c169 Whoops: missed a couple of flag adjustments. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-09 16:19:35 +01:00
Adrian.Conlon
838580cc3d More changes to bring LR35902 in line with the Z80 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-09 16:01:12 +01:00
Adrian.Conlon
93bac42547 Bring LR35902 a little more in line with the Z80 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-09 11:42:32 +01:00
Adrian.Conlon
f3fe475d44 Implement enough changes to build LR35902 2017-06-09 10:23:51 +01:00
Adrian.Conlon
105032f08a Dump of all my C++ emulators, only Intel8080 integrated so far... 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-04 21:38:34 +01:00