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97a121b8d4
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47 Commits

Author SHA1 Message Date
Adrian Conlon
97a121b8d4 Unneeded UNREACHABLEs can cause gcc to produce problematic code. TBC 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-17 23:34:27 +00:00
Adrian Conlon
bebc68539b Correct sneaky reference passing in heavily used method. (~205Mhz emulated speed) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 10:53:11 +00:00
Adrian Conlon
45dc274167 Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 01:53:57 +00:00
Adrian Conlon
c6eb68ba13 Further return by value, rather than reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-26 19:47:35 +00:00
Adrian Conlon
3bd01e211e Try to avoid so many virtual calls in the Z80 by hanging onto AF a little longer. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-09 23:30:51 +00:00
Adrian Conlon
1edabd79f3 More pinout oriented method of executing instructions (especially interrupts) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-10 21:41:48 +00:00
Adrian Conlon
3d88a8f6d1 Couple of small changes in LIKELY/UNLIKELY usage. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-05 21:40:23 +00:00
Adrian Conlon
f1b3fc1932 Correct at least some of the problems with the Z80 interrupt rewrite 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-04 21:59:38 +00:00
Adrian Conlon
23f7a88480 Further 8080/Z80 interrupt rewrite 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-03 00:57:47 +00:00
Adrian Conlon
55b989fe13 More likely/unlikely macro usages. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-02 14:53:35 +00:00
Adrian Conlon
a0f7d584b6 Correct a few warnings reported by "clang" 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-30 14:37:18 +00:00
Adrian Conlon
c513f0cab1 GSL was too problematic when used with GCC. Removed. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-20 19:17:49 +00:00
Adrian Conlon
67c27d4a3e GSL + CPP core guidelines changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-18 14:29:30 +00:00
Adrian Conlon
d010e3ca2f Start incorporating CPP core guidelines (as an experiment!) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-10 22:41:50 +00:00
Adrian Conlon
b3114ed520 Correct some possible one definition rule issues. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-05 14:48:15 +00:00
Adrian Conlon
c292fb552e A whole bunch of consistency changes. No functional changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-03 22:05:01 +00:00
Adrian Conlon
a134d935db More linux compatibility 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 19:53:15 +00:00
Adrian Conlon
899b84baa2 Linux compatibility. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 18:47:23 +00:00
Adrian.Conlon
cae34d61d1 Ensure the Z80 unit tests run successfully to completion. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-07 01:04:09 +01:00
Adrian.Conlon
9b43b74c28 Rationalise some of the reset/initialise logic across pProcessor implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 16:01:40 +01:00
Adrian.Conlon
e70686c5de Some more rationalisation of processor execution/stepping strategies. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-30 23:17:34 +01:00
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 18:52:48 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00
Adrian.Conlon
dfc02c7e54 Remove pointless comment. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-07-24 22:02:55 +01:00
Adrian.Conlon
19966f6ad8 Z80 eight bit increment/decrement can be simplified a little 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-22 10:05:35 +01:00
Adrian.Conlon
beca76d733 Share instruction decoding mechanism between Intel derived processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 13:33:17 +01:00
Adrian.Conlon
36fbee35fb Bring the various IntelProcessor derived processors a little closer together. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-07-19 13:59:28 +01:00
Adrian.Conlon
f52edaf8bc Tidy up 16-bit add/subtract to properly use MEMPTR. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-03 21:42:18 +01:00
Adrian.Conlon
6af1857cb0 A few minor consistency tweaks to the i8080 and z80 processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-02 17:38:19 +01:00
Adrian.Conlon
8f57fac3ee Use the same optimisation techniques on the Z80 header. Up to 233Mhz now. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-29 21:35:52 +01:00
Adrian.Conlon
954887217f Performance mods: probably about 30% speedup: the best yet. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-29 00:50:34 +01:00
Adrian.Conlon
7582d65ea3 Lots more method tidy ups in search of performance. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-28 15:39:31 +01:00
Adrian.Conlon
35efc86195 Simplify the use of the REFRESH register 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-27 14:02:29 +01:00
Adrian.Conlon
c803387023 A few modifications: 
1) Simplify REFRESH register handling via bit fields.
2) Use static methods in the Z80 emulator, if at all possible
3) Use a decoded opcode lookup, rather than decoding per instruction

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-26 23:22:32 +01:00
Adrian.Conlon
f776379e96 Share flag adjustments across implementations using templated methods. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-22 16:57:38 +01:00
Adrian.Conlon
c9bf24d1fa Tidy up register and static method access. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-19 13:53:00 +01:00
Adrian.Conlon
23108a8536 Bring performance back to par by: inlining and static flag register access, where possible. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-18 18:14:39 +01:00
Adrian.Conlon
5f288cf0e3 Some more small tidy ups. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-16 20:31:32 +01:00
Adrian.Conlon
327d391ecb Remove another chunk of shared code. This time by ensuring the basic layout of registers is consistent. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-16 13:52:10 +01:00
Adrian.Conlon
71e6902aeb Simplify and remove a bunch of code. Getting there! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-15 22:21:26 +01:00
Adrian.Conlon
828e081a6e More tidying of shareable code 2017-06-12 14:33:00 +01:00
Adrian.Conlon
0291970427 Further work on uniting the 8080 family processor family. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 21:08:40 +01:00
Adrian.Conlon
627e41bf35 Introduce an IntelProcessor base class to allow known good implementation to be shared. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 09:45:34 +01:00
Adrian.Conlon
d8977d32d3 More MEMPTR clarifications. 
This time to avoid temporary variables, in a similar manner to Z80 hardware.

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-07 22:54:55 +01:00
Adrian.Conlon
211c75d84d Add Z80 processor and tests. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-05 22:39:15 +01:00
Adrian.Conlon
105032f08a Dump of all my C++ emulators, only Intel8080 integrated so far... 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-04 21:38:34 +01:00