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179 Commits

Author SHA1 Message Date
Adrian Conlon
fc7b6e49ca Slightly nicer refactoring of the MEMPTR post increment saga 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-28 13:33:36 +00:00
Adrian Conlon
b3faae34ae Correct a couple of problematic changes picked up by fuse test 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-28 09:42:04 +00:00
Adrian Conlon
fac2da9ac4 Start refactoring CPU cores to use C++17/14 features. (This commit covers the 6502 and Z80) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-27 18:41:55 +01:00
Adrian Conlon
8dbb3eafec Switch to C++17 standard in all EightBit projects. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-27 14:28:14 +01:00
Adrian Conlon
1b2ddd8843 Don't expose the bus via the CPU any more: if a component needs the bus, it should be prepared to hold a reference to it. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-10-20 20:52:41 +01:00
Adrian Conlon
8d3551e681 Refactor bit set/get routines from processor class to lower level chip class. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-29 14:08:44 +01:00
Adrian Conlon
7adefd380a Sort a bunch of missing argument const specifications. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-21 00:16:00 +01:00
Adrian Conlon
fe3794e011 Simplify register16_t usage a little. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-16 12:00:29 +01:00
Adrian Conlon
7d840f1a42 Modifying the manner in which memory is mapped, allows a fairly clean mechanism for loading Intel "hex" files. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-09-15 14:35:59 +01:00
Adrian Conlon
97272d650d Simplify processor bus access a little by further allowing register16_t address access. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-29 13:52:25 +01:00
Adrian Conlon
a8cc289149 Whoops: The "Bus" class *really* isn't allowed to know the "endianness" of the attached processor! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-27 11:27:33 +01:00
Adrian Conlon
3a4235f651 Whoops: The NMI line needs to be powered on by individual processors now it's no longer part of the Processor base class. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 22:50:18 +01:00
Adrian Conlon
1212e8d4f0 Tidy some processor virtual specifications. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 13:35:53 +01:00
Adrian Conlon
c105ee37bf Have a stab at sorting out processor pin handling. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 12:09:26 +01:00
Adrian Conlon
6d4223c368 Start moving towards reset being just another style of interrupt. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 01:34:30 +01:00
Adrian Conlon
677b9a608e Default a couple of project configuration options. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-17 14:02:00 +01:00
Adrian Conlon
ed76038bfa More memptr adjustments 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-17 13:59:59 +01:00
Adrian Conlon
256e25e344 Tidy up the test suite usage between the 8080 and Z80 processors. 2018-08-12 16:30:32 +01:00
Adrian Conlon
228301573e Refactor Z80 block in/out routines. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-12 16:25:30 +01:00
Adrian Conlon
70c70af969 Sort out some exception and member initialisation rules. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-11 21:19:19 +01:00
Adrian Conlon
e40240694f More removal of duplicated code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-24 22:33:02 +01:00
Adrian Conlon
cac871cf2b Remove duplicated code (from const definitions) the performance benefit isn't worth the amount of duplicated code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-24 20:58:20 +01:00
Adrian Conlon
757d8f3c32 Reduce code density a little. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-16 10:09:28 +01:00
Adrian Conlon
7d25962f3c Remove commented block. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-16 09:56:16 +01:00
Adrian Conlon
67487b5b6e Simplify the usage of the register16_t union. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-16 00:55:32 +01:00
Adrian Conlon
7cb5e137f4 Some small simplifications of the 16-bit arithmetic operators. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-11 23:01:48 +01:00
Adrian Conlon
2d8c3d4b12 Simplify AF usage. Keeps speed roughly as before 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-11 00:50:46 +01:00
Adrian Conlon
fbf098ae00 Simplify memory event handlers and ROM recognition a little (bit of speed difference) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-10 22:00:52 +01:00
Adrian Conlon
3e854c7c49 Const some more bus/processor usage, and ensure the data bus is a member, not a reference to memory. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-10 00:40:56 +01:00
Adrian Conlon
116f9961c4 Add a higher/lower nibble mask 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-05-25 22:36:10 +01:00
Adrian Conlon
9de0f597f6 Remove some "tricksy" code from the Z80 emulator chain. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-04-14 09:39:06 +01:00
Adrian Conlon
4b4f6b1a49 Some *small* consistency changes. Perhaps some performance gains. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-04-11 23:53:26 +01:00
Adrian Conlon
d818095815 MEMPTR is really only a concept of Intel style processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-18 22:40:23 +00:00
Adrian Conlon
97a121b8d4 Unneeded UNREACHABLEs can cause gcc to produce problematic code. TBC 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-17 23:34:27 +00:00
Adrian Conlon
dac58b121a More small tidyups in the core emulator set. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-12 01:22:28 +00:00
Adrian Conlon
bebc68539b Correct sneaky reference passing in heavily used method. (~205Mhz emulated speed) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 10:53:11 +00:00
Adrian Conlon
45dc274167 Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 01:53:57 +00:00
Adrian Conlon
c6eb68ba13 Further return by value, rather than reference. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-26 19:47:35 +00:00
Adrian Conlon
adf506a41e Optimisation: Prefer return by value to return by reference. ~10% speed-up! 
Just watch a video by Chandler Carruth from 2015, where he talked about C++ optimisers...

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-25 19:48:01 +00:00
Adrian Conlon
d34b161255 Simplify some build options. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-19 23:18:21 +00:00
Adrian Conlon
29edc46966 Simplify some MEMPTR usage in Intel processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-10 23:08:14 +00:00
Adrian Conlon
3bd01e211e Try to avoid so many virtual calls in the Z80 by hanging onto AF a little longer. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-09 23:30:51 +00:00
Adrian Conlon
1edabd79f3 More pinout oriented method of executing instructions (especially interrupts) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-10 21:41:48 +00:00
Adrian Conlon
3d88a8f6d1 Couple of small changes in LIKELY/UNLIKELY usage. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-05 21:40:23 +00:00
Adrian Conlon
6a47f710b9 More consistency updates between i8080 and Z80. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-04 23:41:49 +00:00
Adrian Conlon
f1b3fc1932 Correct at least some of the problems with the Z80 interrupt rewrite 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-04 21:59:38 +00:00
Adrian Conlon
23f7a88480 Further 8080/Z80 interrupt rewrite 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-03 00:57:47 +00:00
Adrian Conlon
55b989fe13 More likely/unlikely macro usages. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-02 14:53:35 +00:00
Adrian Conlon
9cbf76daf2 Correct a couple of LIKELY/UNLIKELY usages. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-02 10:34:37 +00:00
Adrian Conlon
dc58969614 Whoops: missed Z80 test Makefile. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-30 15:02:58 +00:00
Adrian Conlon
033969bbe3 Add profile guided optimisation to build configuration (profile/profiled) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-30 14:59:24 +00:00
Adrian Conlon
a0f7d584b6 Correct a few warnings reported by "clang" 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-30 14:37:18 +00:00
Adrian Conlon
11062607e6 Start sharing parts of the linux build system. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-26 22:10:17 +00:00
Adrian Conlon
c513f0cab1 GSL was too problematic when used with GCC. Removed. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-20 19:17:49 +00:00
Adrian Conlon
67c27d4a3e GSL + CPP core guidelines changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-18 14:29:30 +00:00
Adrian Conlon
dea1847280 Unify more VS2017 build configurations 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-12 10:38:05 +00:00
Adrian Conlon
d010e3ca2f Start incorporating CPP core guidelines (as an experiment!) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-10 22:41:50 +00:00
Adrian Conlon
b3114ed520 Correct some possible one definition rule issues. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-05 14:48:15 +00:00
Adrian Conlon
7a0ebb9198 Port to VS2015 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-05 14:47:38 +00:00
Adrian Conlon
c292fb552e A whole bunch of consistency changes. No functional changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-03 22:05:01 +00:00
Adrian Conlon
ff2f44bbd2 ... and some more linux compatibility changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 20:15:49 +00:00
Adrian Conlon
a134d935db More linux compatibility 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 19:53:15 +00:00
Adrian Conlon
e43801ae4b More linux compatibility updates. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 19:48:47 +00:00
Adrian Conlon
899b84baa2 Linux compatibility. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-29 18:47:23 +00:00
Adrian Conlon
b232e6992c Get the Z80 test suite up and running again. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-28 13:06:10 +01:00
Adrian.Conlon
2c92e4d389 Updated for appveyor library location compatibility. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-12 13:30:56 +01:00
Adrian.Conlon
cae34d61d1 Ensure the Z80 unit tests run successfully to completion. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-07 01:04:09 +01:00
Adrian.Conlon
9b43b74c28 Rationalise some of the reset/initialise logic across pProcessor implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 16:01:40 +01:00
Adrian.Conlon
1eb127ed72 Add power support to processor base class. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-31 12:13:00 +01:00
Adrian.Conlon
e70686c5de Some more rationalisation of processor execution/stepping strategies. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-30 23:17:34 +01:00
Adrian.Conlon
91c8855183 Share i8080 and Z80 I/O implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 21:41:10 +01:00
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 18:52:48 +01:00
Adrian.Conlon
19c0b93262 Changes to the "const"ness of peek necessitate some changes. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-24 11:06:23 +01:00
Adrian.Conlon
2c7e32aa78 First stab at implementing MBC1 support for LR35902. Not complete, but all old tests still work. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-23 23:17:45 +01:00
Adrian.Conlon
787d9dd799 Missed an easy "assume" entry 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-08 13:38:27 +01:00
Adrian.Conlon
ab20fc6107 Place Z80 documentation close to the Z80 emulator. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-07 09:30:04 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00
Adrian.Conlon
dfc02c7e54 Remove pointless comment. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-07-24 22:02:55 +01:00
Adrian.Conlon
19966f6ad8 Z80 eight bit increment/decrement can be simplified a little 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-22 10:05:35 +01:00
Adrian.Conlon
beca76d733 Share instruction decoding mechanism between Intel derived processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 13:33:17 +01:00
Adrian.Conlon
d0e98fa585 Fix a missing file issue in the fuse test project. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-20 12:17:37 +01:00
Adrian.Conlon
bbbde22322 Modify some of the Z80 daa code to better reflect bool/integer differences. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-20 12:17:03 +01:00
Adrian.Conlon
36fbee35fb Bring the various IntelProcessor derived processors a little closer together. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-07-19 13:59:28 +01:00
Adrian.Conlon
179ec7435f Whoops: adjustment of the block output flag handling was quite wrong! Thanks fuse test suite! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-07 20:55:32 +01:00
Adrian.Conlon
3c0a1697fd Fetching bytes/words and stack access are more processor specific than I thought. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-07 09:27:06 +01:00
Adrian.Conlon
4cd2dc68e1 Correct some (but not all!) project configuration anomalies. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-05 19:36:25 +01:00
Adrian.Conlon
0e7ad4dd01 Correct a couple of inconsistencies in the test harness. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-05 17:40:16 +01:00
Adrian.Conlon
f52edaf8bc Tidy up 16-bit add/subtract to properly use MEMPTR. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-03 21:42:18 +01:00
Adrian.Conlon
6af1857cb0 A few minor consistency tweaks to the i8080 and z80 processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-02 17:38:19 +01:00
Adrian.Conlon
8f57fac3ee Use the same optimisation techniques on the Z80 header. Up to 233Mhz now. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-29 21:35:52 +01:00
Adrian.Conlon
3439523865 Some more optimisations, up to 225Mhz now. 
Reordered if statements to give "then" case "expected"
Better use of "__assume" in switch statements

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-29 21:25:58 +01:00
Adrian.Conlon
366c3fc601 Simplification of bitwise operators. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-29 12:19:22 +01:00
Adrian.Conlon
ea4588992d Whoops: missing switch/break was falling into an assume(0). Caused two fuse tests to fail... 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-29 10:18:07 +01:00
Adrian.Conlon
954887217f Performance mods: probably about 30% speedup: the best yet. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-29 00:50:34 +01:00
Adrian.Conlon
7582d65ea3 Lots more method tidy ups in search of performance. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-28 15:39:31 +01:00
Adrian.Conlon
35efc86195 Simplify the use of the REFRESH register 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-27 14:02:29 +01:00
Adrian.Conlon
c803387023 A few modifications: 
1) Simplify REFRESH register handling via bit fields.
2) Use static methods in the Z80 emulator, if at all possible
3) Use a decoded opcode lookup, rather than decoding per instruction

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-26 23:22:32 +01:00
Adrian.Conlon
a7d9cb0116 Fix an optimisation instruction ordering issue: fetchByte on both rhs/lhs. 
This caused two failing tests in the debug build of the fuse test suite.

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-24 21:38:42 +01:00
Adrian.Conlon
993fe5d2b4 Correct position of fuse test input. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-24 11:00:19 +01:00