Adrian Conlon
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467369d248
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MC6850: Add JSR/RTS unit tests
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:30:10 +01:00 |
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Adrian Conlon
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3441fd062e
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Simplify the usage of the MC6850
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:29:41 +01:00 |
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Adrian Conlon
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2c23289caa
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Expose the clock tick as an externally driven action.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:28:24 +01:00 |
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Adrian Conlon
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4f8d3287d4
|
Whoops: Missed one of the update projects.
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2019-05-05 10:27:08 +01:00 |
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Adrian Conlon
|
8f0dbe0dbc
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i8080: Small board level source layout change, no functional effect
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:26:36 +01:00 |
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Adrian Conlon
|
1a0d3ad77a
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Go through all projects for configuration consistency.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-05-05 10:25:44 +01:00 |
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Adrian Conlon
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bbf8b2230d
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Merge branch 'master' of https://github.com/MoleskiCoder/EightBit
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2019-03-02 21:59:00 +00:00 |
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Adrian Conlon
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934a1f7025
|
Use the virtual methods, busRead and busWrite for all processor bus actions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-03-02 21:58:34 +00:00 |
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Adrian Conlon
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ed47983928
|
Speed up the Intel 8080 disassembler.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-03-02 21:41:06 +00:00 |
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Adrian Conlon
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6c5b595529
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Update README.md
|
2019-02-07 00:01:04 +00:00 |
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Adrian Conlon
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382ae30d32
|
Correct a couple of minor mistakes found while working on the .net port.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-02-03 00:46:49 +00:00 |
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Adrian Conlon
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f0376fa81e
|
Use macros to define our device pins.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-01-14 23:17:54 +00:00 |
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Adrian Conlon
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4d08487513
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Merge branch 'master' of https://github.com/MoleskiCoder/EightBit
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2019-01-14 08:26:42 +00:00 |
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Adrian Conlon
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7f853ec73f
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Add missing 6502 pin events
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-14 08:26:27 +00:00 |
|
Adrian Conlon
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a44658ec94
|
Correct a coulple of newly introduced GB issues.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-14 02:23:48 +00:00 |
|
Adrian Conlon
|
92d23d82d6
|
Start big refactor of device/CPU pin usage (to allow pin events throughout).
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-14 02:10:17 +00:00 |
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Adrian Conlon
|
9755a5fcd2
|
Add the concept of a clocked chip
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2019-01-10 22:23:51 +00:00 |
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Adrian Conlon
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71daf6aa38
|
Split Chip class into Device and Chip.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-10 20:44:16 +00:00 |
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Adrian Conlon
|
68030610d8
|
Move to an event driven clock tick event for all CPUs
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-09 23:24:33 +00:00 |
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Adrian Conlon
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8b187e7614
|
The clock still has to tick, even while held on RDY low, otherwise cycle timing won't work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-09 09:05:12 +00:00 |
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Adrian Conlon
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a90ca6ba38
|
Move RDY initialisation to the CPU power-on sequence. Not strictly correct, but OK.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-09 00:33:56 +00:00 |
|
Adrian Conlon
|
87d86bcd84
|
Whoops: missed unneeded method declaration.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-09 00:08:03 +00:00 |
|
Adrian Conlon
|
01175cf9eb
|
Add support for emulated SYNC and RDY lines. Untested, but feel close.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-08 23:55:27 +00:00 |
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Adrian Conlon
|
047babbe7c
|
Rearrange the RESET handler for cycle accuracy. Use more of the general interrupt handler, but with "dummy" stack write access.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-08 23:09:52 +00:00 |
|
Adrian Conlon
|
25321e78e7
|
Now that HALT/RESET/NMI/IRQ and BRK have a unified architecture, I think this wraps up the instruction handler of the 6502.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-08 01:32:43 +00:00 |
|
Adrian Conlon
|
3faec680b0
|
I think this fixes one of my NES issues. The fix-up required for the PC is handled by the fetchByte associated with the BRK instruction.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-07 01:28:23 +00:00 |
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Adrian Conlon
|
741e005e0c
|
Add some more 6809 documentation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-07 01:09:24 +00:00 |
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Adrian Conlon
|
d7763d8215
|
Profile mode no longer exists on the 6502 test program.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-07 01:08:23 +00:00 |
|
Adrian Conlon
|
06e2a5c947
|
Start unifying 6502 interrupt handling. NMI/IRQ/BRK are all doing mostly the same work.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-07 01:06:07 +00:00 |
|
Adrian Conlon
|
b7b7c93a77
|
This tidies the last of 6502 cycle accurate instruction implementations.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 22:34:53 +00:00 |
|
Adrian Conlon
|
ad644f7013
|
Tidy the 6502 instruction switch statement a little to lessen the width a little.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 20:51:13 +00:00 |
|
Adrian Conlon
|
c3d2ef51d9
|
Cycle accuracy for a couple of the indexed write (store) instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 20:39:37 +00:00 |
|
Adrian Conlon
|
4d3be9e756
|
Use correct boundary crossing conditional for Read/Modify/Write Absolute,X addressing mode.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 12:58:13 +00:00 |
|
Adrian Conlon
|
baf32cef89
|
Get the memory access more correct for more of boundary crossing indexed addressing modes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 12:17:43 +00:00 |
|
Adrian Conlon
|
a13ad5042a
|
Correct constructions of register16_t: the structure is "#ifdef"ed for different endian arrangements.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 11:27:43 +00:00 |
|
Adrian Conlon
|
3749585398
|
Cycle accuracy changes for BRK/RTI instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 11:13:49 +00:00 |
|
Adrian Conlon
|
5b9c348ff1
|
Remove nodiscard instance where we're using the method for cycle/memory accuracy.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-06 11:10:05 +00:00 |
|
Adrian Conlon
|
3337f57747
|
More cycle accuracy changes, concentrating on stack operations.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-05 23:21:43 +00:00 |
|
Adrian Conlon
|
f5125b2a35
|
Add some documentation regarding instruction cycle timings.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-05 23:21:12 +00:00 |
|
Adrian Conlon
|
143e9a9e68
|
More cycle accuracy changes:
1) implied instruction, pointless fetch
2) branch pointless fetch when condition is met
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-05 17:23:50 +00:00 |
|
Adrian Conlon
|
3b7cec9c69
|
Spot a couple more addCycle patterns.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-04 09:17:59 +00:00 |
|
Adrian Conlon
|
d2e853f101
|
Explicitly note implied addressing mode instructions.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-04 08:20:23 +00:00 |
|
Adrian Conlon
|
556e06426e
|
Further work on the slow migration to a cycle accurate 6502
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2019-01-03 01:04:12 +00:00 |
|
Adrian Conlon
|
6c582f6349
|
Add a working(ish) 6502 ATX implementation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-30 17:12:45 +00:00 |
|
Adrian Conlon
|
5ade05a689
|
Add a bunch of undocumented 6502 instructions. Abandoned ATX implementation. Too poorly documented.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-30 12:01:23 +00:00 |
|
Adrian Conlon
|
815c99710a
|
Add enough undocumented 6502 instructions to get through "nestest".
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-29 22:22:31 +00:00 |
|
Adrian Conlon
|
c136b306ab
|
Use the new busRead/Write processor methods to simplify the 6502 cycle counting.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-29 22:18:01 +00:00 |
|
Adrian Conlon
|
adb60a6e90
|
Port the 6502 to the new bus architecture.
|
2018-12-29 19:40:02 +00:00 |
|
Adrian Conlon
|
f38d326ca7
|
Improve the flexibility of the BUS mapping/read/write architecture.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-29 19:17:36 +00:00 |
|
Adrian Conlon
|
722888ae66
|
Correct ROM loading issue discovered while resurrecting NES support.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
|
2018-12-29 19:06:24 +00:00 |
|